JPH11220749A - Camera signal processor and camera signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of a false color signal in an image, even in a band where a correlation cannot be detected by selecting the color difference signal whose value is the minimum among the color difference signals of interpolation pixel data in respective directions and the color difference signals of interpolation pixel data, to which the correlation values in the respective directions are added and generating an image signal based on selected interpolating pixel data. SOLUTION: An image data interpolation part 15 interpolates image data from a gamma-correction circuit 14 for respective pixels, generates respective interpolation pixel data and outputs them to a weight addition circuit 22. The weight addition circuit 22 weights interpolation pixel data in a vertical direction and a horizontal direction, based on the vertical correlation value from a correlation emphasis/reduction circuit 21, adds them and outputs them to a color difference signal suppression part 25 via a Y/C conversion part 24. The color difference signal suppression part 25 selects interpolation pixel data, whose absolute value of the color difference signal is the minimum among inputted interpolation pixel data so as to output it. Thus, the folded distortion of a color can be prevented, even in a frequency band where a correlation cannot be seen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a camera signal processing device and a camera signal processing method for processing a camera signal generated by a single-panel camera device.

[0002]

2. Description of the Related Art Conventionally, a CCD (Charge Coupled) has been used.
In a single-panel camera device using a solid-state imaging device such as a device, R, G,
A color filter corresponding to B is provided. In this camera device, a luminance signal is generated based on light input to the CCD, and the luminance signal is generated via a color filter.
A color signal is created according to the light input to the CD. At this time, in the camera device, C
The color signals corresponding to R, G, and B are created according to the light input to each pixel of the CD.

The CCD in such a camera device is
A color filter having R, G, B for each pixel is arranged, for example, in an array of R, G, R, G,... In the horizontal direction. In this camera device, a color signal is created corresponding to a color filter arranged corresponding to each pixel. Therefore, such a CCD
In the case of, a color signal corresponding to G is not generated in a pixel provided with the R color filter, and G
Needs to be generated by interpolating the color signal corresponding to.

In such a camera device, when obtaining an interpolated image by interpolating each pixel from the horizontal direction,
Interpolation is performed by adding pixel data adjacent in the horizontal direction and calculating the average. Also, when performing interpolation from the vertical direction, similar to the horizontal direction, interpolation is performed by adding pixel data adjacent in the vertical direction and calculating the average.

In such a camera device,
When, for example, a color filter indicating R is arranged on a pixel of the CCD, a signal indicating G is generated by performing the above-described interpolation on a color signal indicating G.

In a single-panel camera device, when pixel data is generated by performing interpolation, a correlation value indicating a correlation in a vertical direction and a horizontal direction is detected. When the correlation value is detected, the signal of the pixels arranged in the vicinity is calculated using a filter to calculate the correlation value in the vertical direction and the correlation value in the horizontal direction. In this camera device, interpolation pixel data obtained by interpolation is weighted using the correlation value.

[0007]

In the above-described camera device, the gain is reduced near the lower limit of the sampling frequency and the limit of the Nyquist frequency when the frequency of the luminance signal generated from the interpolated pixel data obtained by the interpolation is reduced. Is inevitable. As described above, when the gain decreases near the frequency of the luminance signal near the Nyquist frequency, the resolution of the output image generated by the camera device deteriorates. This means that in the single-panel camera device, even if the frequency of the luminance signal is １ ／ of the sampling frequency, the frequency of the chrominance signal is １ ／.
It depends only on.

As described above, in the camera device, the correlation value cannot be detected in the frequency band near the Nyquist limit. Therefore,
In such a band, for example, a false color signal may be generated at a color edge or the like.

Therefore, the present invention has been proposed in view of the above-mentioned situation, and does not generate a false color signal in an image even in a band where a correlation cannot be detected. It is an object to provide a camera signal processing device and a camera signal processing method.

[0010]

A camera signal processing apparatus according to the present invention which solves the above-mentioned problems comprises a solid-state image pickup device to which image pickup light enters via color filters having different spectral sensitivities corresponding to respective pixels. Interpolation pixel data generation means for generating interpolation pixel data in each direction by interpolating from at least two or more directions based on the position and / or surrounding pixel data of the pixel data generated based on the imaging signal of Correlation detection means for detecting correlation values indicating the degree of correlation in two or more directions of the interpolation pixel data generated by the interpolation pixel data generation means, and interpolation pixel data and correlation detection for each direction generated by the interpolation pixel data generation means Means for detecting a color difference signal of the interpolated pixel data to which the correlation value of each direction generated by the means is added, and a color difference signal of the interpolated pixel data in each direction. Selecting means for selecting and outputting the smallest color difference signal among the color difference signals of the interpolated pixel data to which the correlation values in each direction are added; and generating an image based on the interpolated pixel data selected by the selecting means. Image generating means.

Further, according to the camera signal processing method of the present invention, a pixel generated based on an image pickup signal from a solid-state image pickup device to which image pickup light is incident via a color filter having a different spectral sensitivity corresponding to each pixel. Interpolated from at least two or more directions based on the position and / or surrounding pixel data of the data, to generate interpolated pixel data in each direction, and to generate two or more directions of the interpolated pixel data generated by the interpolated pixel data generating means. And a color difference signal of the interpolated pixel data to which the interpolated pixel data in each direction and the interpolated pixel data in each direction added by the correlation detection means are detected, and the interpolated pixel data in each direction is detected. The color difference signal having the smallest value is selected from among the color difference signals of the interpolation pixel data to which the correlation values of the respective directions are added and the correlation value of each direction is added, and based on the selected interpolation pixel data And generating an image.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a camera signal processing apparatus and a camera signal processing method according to the present invention will be described with reference to the drawings.

FIG. 1 shows a camera signal processing apparatus according to the present invention.
As shown in FIG. 7, the present invention can be applied to a camera device 1 that generates, for example, a still image according to input light.

The camera device 1 is a CCD (Charge Coup).
led Device) An optical system 2 for forming an image of a subject on an imager (hereinafter referred to as a CCD), a CCD 3, and the CC
A timing generator 4 for driving D3;
/ Hold circuit 5 to which an imaging signal is input from
An AGC circuit 6 which receives an image signal from the sample / hold circuit 5 and adjusts a gain; an A / D conversion circuit 7 which converts the input image signal into digital image data; , A CCD detection unit 9 for detecting an image signal generated by the CCD 3, and a control unit 10 for controlling these units.

Here, in the CCD 3, a region transmitting R (red) light, a region transmitting G (green) light, and a region transmitting B (blue) light are formed in a matrix. A color filter is provided, and light transmitted through the color filter is input to each pixel. In this color filter, for example, regions that transmit light of each color are arranged in the horizontal direction as R, G, R, G,... Or G, B, G, B,. That is, the CCD 3 generates pixel data R, pixel data G, and pixel data B based on the light corresponding to each color R, G, B for each pixel.

The CCD detector 9 receives the image data converted by the A / D converter 7 into a digital signal. The image data detected by the CCD detector 9 is, for example, an AE (auto exposure) circuit and an AF (auto focus).
us) circuit. Then, for example, the image data input to the AE circuit is used to adjust the shutter speed or the aperture of the electronic shutter, and automatically switches the brightness of the light incident on the CCD 3.

The camera processing unit 8 includes a defect correction circuit 11 to which image data is input from the A / D conversion circuit 7 and a CLP circuit 12 to which image data is input from the defect correction circuit 11.
A white balance circuit 13 to which image data is input from the CLP circuit 12, and a gamma correction circuit 14 to which image data is input from the white balance circuit 13.

The defect correction circuit 11 performs defect correction on the image data from the A / D conversion circuit 7. This defect correction circuit 1
1 corrects a defect of a pixel in which pixel data is not generated because of having a defect, and outputs image data to the CLP circuit 12.

The CLP circuit 12 subtracts optical black from the image data from the defect correction circuit 11.
As described above, the CLP circuit 12 corrects the black level of the input image data and outputs the image data to the white balance circuit 13.

The white balance circuit 13 adjusts the level of each color corresponding to the image data R, G, B from the CLP circuit 12. Thus, the white balance circuit 13
Outputs the image data whose level has been adjusted for each color to the gamma correction circuit 14.

The gamma correction circuit 14 performs gamma correction on the image data from the white balance circuit 13. And
The gamma correction circuit 14 outputs the gamma-corrected image data to an image data interpolation unit and a correlation value detection unit described later.

As shown in FIG. 2, the signal processing unit 8 includes an image data interpolation unit 15 to which image data is input from the gamma correction circuit 14 and a correlation value detection unit that detects a correlation value between pixel data. A noise removing unit 17 for removing noise of the correlation value, an offset circuit 18 for offsetting the correlation value, a normalizing circuit 19 for normalizing the correlation value,
Bias correction circuit 20 for correcting the bias in the direction of detecting the correlation
An emphasis / reduction circuit 21 for emphasizing and reducing the correlation;
A weighted addition circuit 22 for weighting the interpolated image data using a correlation value, an outline correction circuit 23 for correcting the outline of the image data, and an image data Y including a luminance signal (Y) and a color difference signal (C). Y / C converter 2 for converting to / C signal
4, a color difference signal suppression unit 25 for suppressing a false color signal due to the color difference signal, and an output unit 26.

The image data interpolation unit 15 includes a γ correction circuit 1
4, image data composed of a plurality of pixel data is input. The image data interpolating unit 15 interpolates the pixel data R, G, and B for each pixel to generate the interpolated pixel data R ', G', and B '. The image data interpolation unit 15 includes a horizontal interpolation circuit 15a for interpolating pixel data corresponding to pixels arranged in a horizontal direction, and a vertical interpolation circuit 15b for interpolating pixel data corresponding to pixels arranged in a vertical direction. Consists of

Pixel data R, G, and B corresponding to each pixel arranged in a matrix as shown in FIG. 3 are input to the horizontal direction interpolation circuit 15a. The horizontal interpolation circuit 15a calculates interpolation pixel data in the horizontal direction by using a filter expressed by the following equation 1. FIG. 3 is a diagram showing pixel data R, G, and B corresponding to each pixel, and is a diagram in which coordinates are indicated by numerals as the arrangement of each pixel.
In the following description, it is assumed that 0h, 1h, 2h, 3h, and 4h are arranged for each line in the horizontal direction.

[1,4,6,4,1] / 8 (Equation 1) That is, when calculating the interpolated pixel data R ′, G ′, and B ′, since the filter shown in Equation 1 is used, the horizontal The direction interpolation circuit 15a is configured as shown in FIG.

The horizontal direction interpolation circuit 15a generates the interpolated pixel data R ', G', B 'in the horizontal direction.
The configuration is as shown in FIG. This horizontal interpolation circuit 15
a is an input unit 30 to which pixel data is input from the γ correction circuit 14, a delay circuit 31 to which each pixel data is input from the input unit 30, and an interpolation pixel to which each pixel data in the horizontal direction is input from the delay circuit 31. The filter circuit 32 includes a filter circuit 32 for generating data, a selector circuit 33 to which interpolation pixel data is input via the filter circuit 32, and an output terminal 34 for outputting interpolation pixel data from the selector circuit 33.

Each pixel data in the horizontal direction is sequentially input from the gamma correction circuit 14 to the input section 30. The input unit 30 is sequentially input by a clock for each pixel data. The delay circuit 31 includes delay circuits 31a to 31d to which each pixel data input from the input unit 30 is input. The delay circuit 31 inputs the input pixel data to each of the delay circuits 31 a to 31 d in synchronization with the above clock and outputs the data to the filter circuit 32.

The filter circuit 32 includes an adder 32 to which pixel data is input via the input section 30 and the delay circuit 31d.
a, an adder 32b to which the pixel data is input via the delay circuit 31a and the delay circuit 31c, an adder 32c to which the pixel data is input via the delay circuit 31b, and an output from the adder 32a and the adder 32c. And an adder 32d to which an output is input.

The adder 32a receives the pixel data directly input from the input unit 30 and the pixel data via a delay circuit 31d, the adder 32c receives the pixel data via a delay circuit 31b, and the adder 32d receives Pixel data is input via the adders 32a and 32c. Also,
Pixel data is input to the adder 32b via the delay circuits 31a and 31c.

That is, the filter circuit 32 uses the adders 32a, 32c and 32d to generate [1, 0, 6, 0, 1] /
8, and [1, 0, 1] is added by the adder 32b.
/ 2 filter.

The selector circuit 33 includes selectors 33a and 33b to which the output from the adder 32d and the pixel data are input via the delay circuit 31b, and a selector to which the output from the selector 33a and the output from the adder 32b are input. 3
3c, and a selector 33d to which outputs from the adder 32b and the selector 33b are input.

The operation of each of the selectors 33a to 33d is controlled by receiving a control signal from the control unit 10.

The output section 34 has a terminal 34a for outputting an output from the selector 33c and a terminal 34b for outputting an output from the selector 33d to an edge processing circuit described later.

The horizontal interpolation circuit 1 constructed as described above
5a, for example for the pixel data G _22, interpolated pixel data R ₂₂ ', B _22' as well, also to calculate the interpolated pixel data G ₂₂ '.

When the horizontal interpolation circuit 15a calculates, for example, the interpolated pixel data G ₂₂ ′ for the pixel data G _{22 in} FIG. 3, the input unit 30 uses the pixel data G ₂₀ , R ₂₁ , G ₂₂ , R for 2h. ₂₃ and G ₂₄ are sequentially input.

Next, the pixel data G input by the input unit 30
₂₀ , R ₂₁ , G ₂₂ , R ₂₃ , and G ₂₄ are input to the filter circuit 32 by the delay circuit 31. That is, the input pixel data G ₂₀ to the adder 32a, an adder 32b pixel data R ₂₁
, The pixel data G ₂₂ is input to the adder 32c, the pixel data R ₂₃ is input to the adder 32b, and the pixel data G ₂₄
Is input to the adder 32a.

Next, each pixel data G
_20, the G _22, G _24, performs calculation of the interpolated pixel data G ₂₂ 'for the pixel data G _22. That is, the adder 32a
In output to the adder 32d adds processing and pixel data G ₂₀ and the pixel data G _24. Moreover, the adder 32c, and outputs to the adder 32d adds treat them as twice as well as four times the pixel data G _22. Then, the adder 32d receives the outputs from the adders 32a and 32c, performs an addition process on them, performs a １ ／ multiplication process, and outputs the result to the selector circuit 33. Further, the adder 32b, and outputs to the selector circuit 33 performs 1/2 multiplication processing while adding process these enter the pixel data R ₂₁ and pixel data R _23.

As described above, the adders 32a, 32c, 32d
加 算 pixel data G ₂₀ + 6 ×
An operation of pixel data G ₂₂ + pixel data G ₂₄ ｝ / 8 is performed. On the other hand, by performing the addition process in the adder 32b,
An operation of {pixel data R ₂₁ + pixel data R ₂₃ } / 2 is performed. That is, in the filter circuit 32, the adder 3
2b forms a filter of [1, 0, 1] / 2, and adders 32a, 32c, 32d form [1, 0, 6, 0, 1].
/ 8, and the pixel data G ₂₀ , G ₂₂ ,
The G ₂₄ is passed through the filter shown in Equation 1 described above. Therefore, according to the filter circuit 32, the pixel data R
₂₂ interpolated pixel data R ₂₂ for, G ₂₂ ', G _22' to create.

Next, the selector 33a and the selector 33b
In inputs the interpolated pixel data G ₂₂ ', inputs the pixel data G _22. The control signal H or the control signal L is input from the control unit 10 to the selectors 33a and 33b. Here, when the control signal H is input to the selectors 33a and 33b, the interpolation pixel data G ₂₂ ′ from the filter circuit 32 is output to the selectors 33c and 33d as they are, and when the control signal L is input, the pixel and outputs the data G ₂₂ selector 33c, the 33d.

Next, in the control unit 10, the pixel data G
Interpolated pixel data G ₂₂ 'is a filter circuit 32 for ₂₂
, The control signal L is supplied to the selector 33.
c and the selector 33d. Thus, when the control signal L is input to the selectors 33c and 33d, the selector 33c outputs the interpolated pixel data R ₂₂ ′, and the selector 33d outputs the pixel data G ₂₂ or the interpolated pixel data G ₂₂ ′.

On the other hand, when the control signal H is input from the control unit 10 to the selectors 33c and 33d, the selector 33c outputs the data input from the selector 33a, and the selector 33d outputs the data input from the adder 32b. Output.

That is, when outputting the interpolated pixel data G ₂₂ ′ for the pixel data G ₂₂ , for example, the selector 33 d outputs the input from the selector 33 b, and FIG.
When outputting the interpolated pixel data G ₂₃ ′ for the middle pixel data G ₂₃ , control is performed so as to output the input from the adder 32b. Then, the selector 33c is connected to the terminal 34.
Output the interpolated pixel data R ₂₂ ′ for the pixel data R or the pixel data B to a, and the selector 33 d outputs the interpolated pixel data G ₂₂ ′ for the pixel data G to the terminal 34 b.

When calculating the interpolated pixel data G 'for the pixel data G in this manner, the interpolation is performed by assuming the CCD 3 consisting only of the pixel data G as shown in FIG. The pixel data G ′ is calculated. Therefore, when calculating the interpolated pixel data G 'for a pixel having no pixel data G, the horizontal direction interpolation circuit 15a calculates the interpolated pixel data G' using a filter of [1, 0, 1] / 2. When calculating the interpolated pixel data G 'for the pixel in which the pixel data G exists, the interpolated pixel data G' is calculated using a filter of [1, 0, 6, 0, 1] / 8. Therefore, in the horizontal direction interpolation circuit 15a that calculates the interpolation pixel data G 'using such filters, the frequency characteristics of these filters are as shown in FIGS. That is, this [1,0,6,0,1] / 8 filter shows frequency characteristics as shown in FIG.
The filter [1, 0, 1] / 2 shows frequency characteristics as shown in FIG. According to the frequency characteristics of the filters shown in FIGS. 6 and 7, in the horizontal direction interpolation circuit 15a, the frequency characteristics of the interpolated pixel data G ′ and the pixel data of the pixel where the pixel data G exists are determined by using these filters. The difference from the frequency characteristic of the interpolated pixel data G ′ in which G does not exist can be reduced.

Therefore, by calculating the interpolated pixel data G 'for each pixel data G in this way, the interpolated image data G' as shown in FIG. 8 can be obtained.

The horizontal direction interpolation circuit 15a
Calculated the interpolated pixel data R ₂₂ ′ for the pixel data G ₂₂ using the filter of [1, 0, 1] / 2 in 2h, but in 1h, the pixel data G ₂₂
It is also possible to calculate the interpolated pixel data B ₁₁ 'for _11.

Next, when calculating the interpolation pixel data B ₂₂ ′ for the pixel data G _{22 in} 2h, the calculation is performed using the filter shown in FIG. That is, in the following description, an example of calculating the interpolation pixel data B ′ in a line where no pixel data B exists will be described.

The interpolated image data B ₂₂ of the pixel data G ₂₂ 'when calculating the horizontal direction interpolation circuit 15a configured as shown in FIG. 9' to calculate the interpolated pixel data B ₂₂ 'with. In the following description of the horizontal interpolation circuit 15a ', the same parts as those of the horizontal interpolation circuit 15a shown in FIG. That is, in the horizontal direction interpolation circuit 15a 'shown in FIG. 9, the terminal 30a of the pixel data is input in the order of _{B 10, G 11, B 12} , G 13, B 14 at the input unit 30 for example 1h, 3h Terminal 3 to which pixel data at is input in the order of B ₃₀ , G ₃₁ , B ₃₂ , G ₃₃ , B ₃₄
0b. The horizontal interpolation circuit 15a 'shown in FIG. 9 includes terminals 30a and 30b
And an adder 35 to which the pixel data is input.
The adder 35 receives the pixel data from the terminal 30a and the terminal 30b and performs an addition process and a division process. That is, the adder 35 performs a process of {pixel data B ₁₀ + pixel data B ₃₀ } / 2, for example. In the horizontal direction interpolator 15a 'of FIG. 9, the interpolated pixel data G', B via delay circuits 31a to 31d, an adder 32, and a selector circuit 33, similarly to the horizontal direction interpolator 15a shown in FIG. 'Is output.

That is, the horizontal direction interpolation circuit 15a '
First, the pixel data B of each pixel arranged as shown in FIG. 10 is interpolated in the vertical direction by an arithmetic mean of the pixel data B corresponding to the pixels arranged in 1h and 3h adjacent to each other in the vertical direction. Is interpolated in the vertical direction as shown in FIG. 11 to calculate interpolated pixel data B ′.

Next, the pixel data B in the vertical direction
And the interpolated pixel data B ′ obtained by interpolation are [1, 0, 6,
Interpolated pixel data B ′ of the pixel data B in the horizontal direction is calculated via a [0,1] / 8 filter and a [1,0,1] / 2 filter.

That is, the horizontal interpolation circuit 15a '
Then, the interpolated pixel data B ₂₂ ′ for a line in which the pixel data B does not exist in the horizontal direction is created as follows.
First, a filter consisting of [1,0,6,0,1] / 8 is applied to the pixel data B at 1h and 3h by passing through the adders 32a, 32c and 32d by the filter circuit 32. [1,0,
1] / 2 is applied by passing through the adder 32b. The horizontal direction interpolation circuit 15a 'further filters the filter [1,0,1] / 2 from the value of the pixel data B obtained by passing through the filter [1,0,6,0,1] / 8. A subtraction processing circuit for subtracting the value of the pixel data G obtained by passing through, and the interpolation pixel data G obtained by the horizontal interpolation circuit 15a shown in FIG.
₂₂ ′.

That is, the horizontal direction interpolation circuit 15a '
Then, from the value of the pixel data B obtained by passing through the filter consisting of [1, 0, 6, 0, 1] / 8, [1, 0, 1] / 2
, And subtracts the value of the pixel data G obtained by passing through the filter consisting of the pixel data G, adds the pixel data G ′, and outputs the interpolated pixel data B ′ to the weighted addition circuit 22.

As described above, the horizontal direction interpolation circuit 15 shown in FIG.
As for a ′, interpolation pixel data B ₂₂ ′ can be calculated as shown in FIG. 12, even for pixel data G ₂₂ corresponding to a pixel having no pixel data B, such as 2h.
That is, according to the horizontal direction interpolation circuit 15a 'in FIG. 9, the interpolation pixel data B' can be calculated for all (all) pixels.

Further, such a horizontal direction interpolation circuit 15
a ′ is the interpolation pixel data B ₂₂ ′ for the pixel data G _22.
May be calculated using the interpolated pixel data calculated by Equation 2 below and Equation 1 above.

B ₂₂ ′ = {(B ₁₂ ′ −G ₁₂ ′) + (B ₃₂ ′ −G ₃₂ ′)} / 2 + G ₂₂ ′ (Equation 2) According to the equation 2, the interpolation pixel data B ₂₂ ′ is At the time of calculation, G ₁₂ ′, G ₃₂ ′, and G ₂₂ ′ calculated using the horizontal direction interpolation circuit 15 a of FIG.
Interpolated pixel data B ₂₂ ′ can be calculated using ₃₂ ′ B ₁₂ ′. On the other hand, the vertical direction interpolation circuit 15b
It is configured as shown in FIG. In the following description of the vertical direction interpolation circuit 15b, the same parts as those of the above-described horizontal direction interpolation circuit 15a are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 13, the vertical direction interpolator 15b operates the pixel data R, G, B in the vertical direction.
Are sequentially provided. The input unit 30 is a terminal 30 to which pixel data in 1h is input.
a and terminal 30b to which pixel data at 3h is input
And a terminal 30c to which pixel data at 0h is input
And a terminal 30d to which pixel data at 4h is input
And a terminal 30e to which pixel data at 2h is input.

The vertical direction interpolation circuit 15b has a filter circuit 32, a selector circuit 33, and an output section 34, like the horizontal direction interpolation circuit 15a. In the vertical direction interpolation circuit 15b, each of the terminals 30a to 30a
When pixel data B ₁₀ , B ₃₀ , G ₀₀ , G ₄₀ , and G ₂₀ are input to ₃₀ e, the pixel data input to terminals 30 a and 30 b are output to adder 32 b and input to terminals 30 c and 30 d. The output pixel data is output to the adder 32a, and the pixel data input to the terminal 30e is output to the adder 32c.
Output to Then, in the vertical direction interpolating circuit 15b, similarly to the horizontal direction interpolating circuit 15a, the input pixel data is filtered by the filter circuit 32 using the above-described equations 1 and 2.
To obtain the interpolated pixel data R ′, G ′, B ′ for the pixel data R, G, B.

The horizontal interpolation circuit 15a and the vertical interpolation circuit 15b constituting the image data interpolation section 15
Are connected to the edge processing circuit 15c. As shown in FIG. 14, the edge processing circuit 15c includes an input unit 40 including terminals 40a to 40c to which the pixel data G subjected to the delay adjustment from the above-described γ correction circuit 14 is input. Delay circuits 41 a to 41 d to which the pixel data G is input, a comparing unit 42 for comparing the input pixel data G, an operating unit 43 for performing an arithmetic process on the comparison result of the comparing unit 42, The output unit 44 controls the output according to the calculation result, and the output terminal 45 outputs pixel data from the output unit 44. Further, the edge processing circuit 15 c
4, the respective pixel data G are input. Here, an example in which the edge processing unit 15c described below controls, for example, the value of the interpolation pixel data G ′ in FIG. 15 will be described.

The input section 40 supplies pixel data G around the interpolated pixel data G 'in FIG. 15 obtained by interpolation by the horizontal interpolation circuit 15a and the vertical interpolation circuit 15b.
₁ ~G ₄ is input. The input unit 40 is, for example, 2h
Interpolation when pixel data performs edge processing on the 'a terminal 40a of pixel data G ₁ of 1h adjacent to the upper is input, the interpolated pixel data G' corresponding interpolated pixel data G both sides of the pixel data in the horizontal direction in It has a terminal 40b to which G ₂ and G ₃ are input, and a terminal 40c to which 3h of pixel data G ₄ adjacent below the interpolated pixel data G ′ is input. In addition, each terminal 40a-40
c is connected to the delay circuits 41a to 41d. In addition,
The pixel data G ₁ , G ₂ , G ₃ , G ₄ are input to the terminals 40 a to 40 c after being delayed.

The delay circuits 41a to 41d are connected to the comparing section 42 and the output section 44, and receive the pixel data G _{1 to} G ₄ output from the input section 40. These delay circuits 41a to 41
d outputs the pixel data G ₁ ~G ₄ to the comparator 42 and the output unit 44 at a clock synchronized with the clock input pixel data G ₁ ~G _4.

The comparing section 42 receives the 4
It is composed of comparators 42a to 42f to which two pixel data of one pixel data are input. That is, the comparison unit 42, comparator 42b and a pixel data G ₁ and pixel data G and the comparator 42a to the pixel data G ₁ and the pixel data G ₂ is input, the pixel data G ₁ and the pixel data G ₃ is input Comparator 4 to which ₄ is input
And 2c, and 42d comparator pixel data G ₂ and the pixel data G ₃ is input, the comparator 42e to the pixel data G ₂ and the pixel data G ₄ is input, the pixel data G _3, and pixel data G ₄ is input Comparator 42
f.

[0061] The comparator 42a is pixel data G ₁ at terminal A, the pixel data G ₂ is input at terminal B, the comparator 42b is the pixel data G ₁ at terminal A, the pixel data G ₃ at the terminal B is input, the comparator 42c is terminal A
In the pixel data G _1, pixel data G ₄ at the terminal B is inputted, 42d comparator pixel data G ₂ at the terminal A, the pixel data G ₃ is input at terminal B, the comparator 42e
The pixel data G ₂ at the terminal A, the pixel data G ₄ is input at terminal B, the comparator 42f is pixel data G at the terminal A
_{3. The} pixel data G ₄ is input at the terminal B.

The calculation unit 43 receives the comparison result from the comparison unit 42 and, based on the comparison result, calculates the second and third image data among the pixel data G _{1 to} G ₄ input by the input unit 40. select. Here, the arithmetic unit 43 is composed of a plurality of selectors. The calculation unit 43 includes, for example, a comparator 42a, a comparator 42b, and a comparator 42c.
From (L, H, H), (H, L, H),
(H, H, L), the pixel data G ₁
, And outputs the calculation result to the output unit 44. In addition, in the arithmetic unit 43, for example, the comparison result from the comparators 42a, 42d, and 42e is any one of (H, L, L), (H, L, H), and (H, H, L). In this case, the calculation result is output to the output unit 44 with the pixel data G ₂ as the third place.

The output unit 44 includes the input unit 40 and the arithmetic unit 43
Is connected to This output unit 44
Each pixel data G₁~ G_FourIs input and the operation unit 4
The calculation result is input from 3. This output unit 44 is second
Selector that outputs pixel data according to the operation result indicating
44a and pixel data G according to the calculation result indicating the third place. ₁
~ G_FourAnd a selector 44b that outputs Also,
Outputs the pixel data G input at the terminal 40a.
₁And the image input at terminal 40b.
Raw data G_TwoIs input at terminal 10b,
Input pixel data G_ThreeTerminal and the terminal
Pixel data G input at 40c_Four11 end where is input
With a child.

The output section 45 is connected to the output section 44, the horizontal direction interpolation circuit 15a, and the vertical direction interpolation circuit 15b. The output unit 45 converts the pixel data G _{1 to} G ₄ indicating the second and third places output from the output unit 44 into horizontal direction interpolation circuits 15.
a, Output to the vertical interpolation circuit 15b.

The edge processing circuit 15 thus configured
When performing the edge processing at c, as shown in FIG.
Interpolated pixel data G ′ obtained by the input unit 40 by, for example, the horizontal interpolation circuit 15a and the vertical interpolation circuit 15b.
The pixel data G ₁ , G ₂ , G ₃ , and G ₄ around the pixel are input by the input unit 40. Here, the numbers in each pixel data in FIG. 15 represent the size of each pixel data G _{1 to} G ₄ . Here, the input unit 40 inputs the pixel data G ₁ at the terminal 40a, and enter the pixel data G ₂ at the terminal 40b, and inputs the pixel data G ₃ at the terminal 40b, the terminal 4 pixel data G ₄
Input with 0c. Then, the pixel data G _{1 to} G ₄ are supplied to each comparator 42 via each of the delay circuits 41 a to 41 d.
a to 42f.

Next, each of these comparators 42a-42
In f, the input pixel data G _{1 to} G ₄ are compared in size and the comparison result is output to the arithmetic unit 43. At this time, when the pixel data input to the terminal A is larger than the pixel data input to the terminal B, each of the comparators 42a to 42f outputs the comparison result H to the arithmetic unit 43, and the pixel data input to the terminal A When the pixel data is smaller than the pixel data input to B, the comparison result L is output to the calculation unit 43.

Next, in the arithmetic section 43, each comparator 4
Among the pixel data G ₁ ~G ₄ inputted by the input unit 40 in accordance with the comparison result from 2A～42f, to determine the 2-position and 3-position of the pixel data G ₁ ~G _4, outputs the operation result 44 Output to Here, the calculation result indicating the second place is input by the selector 44a, and the calculation result indicating the third place is input by the selector 44b. Then, each selector 44a, 44b are operation result pixel data G ₁ based on, G _2, G _3, among the G _4, 2 and 3 positions to select the pixel data G ₁ ~G ₄ corresponding output Output to the unit 45.

Next, in the output unit 45, these second and third
The horizontal direction interpolation circuit 1 converts pixel data G _{1 to} G ₄ corresponding to
5a and the vertical direction interpolation circuit 15b.

Next, a possible in the horizontal direction interpolation circuit 15a and the vertical direction interpolation circuit 15b, the size of the interpolated pixel data G 'from the pixel data G ₁ ~G ₄ corresponding to the 2-position and 3-position are calculated Become.

Therefore, such an edge processing circuit 1
According to 5c, for example, the size of the pixel data G ₁ is 10
0, if the size is 100 pixel data G _2, the size is 100 pixel data G _3, the size of the pixel data G ₄ is 0, the pixel data representing between 2-position and 3-position, 1 together
00, the size of the interpolated pixel data G ′ is 100
Is limited to Therefore, the edge processing circuit 15c
According to the above, the interpolated pixel data G ′ obtained by interpolating the pixel data shown in FIG.
+0) = 50.

The correlation value detecting section 16 is provided with the above-described γ correction circuit 1.
4, pixel data is input. This correlation value detection unit 16
Comprises a horizontal correlation detection circuit 16a for detecting a horizontal correlation value and a vertical correlation detection circuit 16b for detecting a vertical correlation value.

The horizontal correlation detection circuit 16a uses a filter expressed by the following equation 3 for a pixel where the pixel data G exists, and uses a filter expressed by the following equation 4 for a pixel where the pixel data G does not exist. to calculate the C _h.

[0073]

(Equation 1)

[0074] That is, the horizontal correlation values C _h, in the vertical direction, there is no LPF, pixel data G [1,0,6,0,1] using Equation 3 in the case where the pixel data G exists In this case, the calculation is performed by multiplying the LPF of [1, 0, 1] using Expression 4. The horizontal correlation value C _h is in the horizontal direction, [- 1,0,2,0, -1] is calculated by multiplying the BPF of.

The horizontal direction correlation detecting circuit 16a is provided in the circuit shown in FIG.
As shown in 6, the input unit 50 from the γ correction circuit 14 pixel data is inputted from the terminal 50 a to 50 e, a filter circuit 52 for each pixel data to generate a horizontal correlation value C _h is input, the horizontal correlation value the selector circuit C _h is input 5
And 3, and an output unit 54 for outputting a horizontal correlation value C _h from the selector circuit 53.

The input section 50 sequentially inputs the pixel data arranged in the vertical direction shown in FIG. 3 from the γ correction circuit 14. The input unit 50 receives a terminal 50a to which pixel data at 1h is input, a terminal 50b to which pixel data at 3h is input, a terminal 50c to which pixel data at 0h is input, and a pixel data at 4h. It has a terminal 50d and a terminal 50e to which pixel data at 2h is input.

The filter circuit 52 has an adder 52a to which pixel data is inputted from the terminals 50a and 50b, an adder 52b to which pixel data is inputted from the terminals 50c and 50d, and a pixel data to be inputted from the terminal 50e. And an adder 52d to which outputs from the adder 52b and the adder 52c are input. This filter circuit 52 includes [1, 0, 6, 0,...] At the adders 52b, 52c, and 52d, similarly to the filter circuit 33 shown in the horizontal interpolation circuit 15a and the vertical interpolation circuit 15b. 1] / 8, and the adder 52a forms a [1, 0, 1] / 2 filter.

The selector circuit 53 includes a selector 53a to which the output from the adder 52d and the pixel data from the terminal 50e are input, and a selector and an output from the adder 52a.
and a selector 53b to which an output from a is input.
The operation of each of the selectors 53a and 53b is controlled by inputting a control signal from the control unit 10. That is, when the control signal H is input from the control unit 10, the selector 53 a outputs the pixel data input via the adders 52 b, 52 c, and 52 d, and when the control signal L is input from the control unit 10, The pixel data input from 50e is output. In addition, the selector 53b is connected to the control unit 10
Whether to output horizontal correlation values C _h passing through the adder 52a according to the control signal from either outputs the pixel data that has passed through the selector 53a is controlled.

In the horizontal correlation detection circuit 16a, pixel data for which a correlation value is to be calculated may be input to the selector circuit 53 without passing through the filter circuit 52. Thus, the filter circuits 52b, 5
By using the pixel data G as it is as the correlation value without passing through the 2e and 52d, it is possible to suppress a decrease in the band of the pixel data G and to simplify the circuit.

The selector 53b is controlled to pass the output from the adder 52b, 52c, 52d or (or) the terminal 50e in the pixel where the pixel data G exists, and in the pixel where the pixel data G does not exist. Adder 52a
Is controlled to pass the output from

[0081] The output unit 54 outputs the horizontal correlation values C _h inputted from the selector 53b. The output unit 54 has a BPF of [−1, 0, 2, 0, −1] in a horizontal direction (not shown).
, And outputs the horizontal correlation value _Ch to the noise removing unit 17.

The vertical direction correlation detection circuit 16b uses the filter shown in the following equation 5 for the pixel where the pixel data G exists, and uses the filter shown in the following equation 6 for the pixel where the pixel data G does not exist. Calculate C _v .

[0083]

(Equation 2)

That is, the vertical correlation value C _v is calculated as [−1, 0,
2,0, -1]. Further, the vertical correlation value C _v is obtained by using the equation 5 in the horizontal direction when the pixel data G exists, the LPF of [1, 0, 6, 0, 1], and in the case where the pixel data G does not exist, the equation 6 [1,0,
1] is calculated by the LPF.

The vertical direction correlation detecting circuit 16b has the configuration shown in FIG.
As shown in FIG. 7, [−1,
[0,2,0, −1]], an input unit 55 to which pixel data is input via the BPF, delay circuits 56a to 56d to which each pixel data is input from the input unit 55, and delay circuits 56a to 56d.
A filter circuit 57 in which each pixel data to produce a vertical correlation value C _v is inputted from 56d, a selector circuit 58 which vertical correlation value C _v through the filter circuit 57 is input, the vertical correlation value from the selector circuit 58 And an output unit 59 for outputting _Cv .

The input unit 55 receives a signal of [−1, 0, 2, 0, −1] from the γ correction circuit 14 in the vertical direction (not shown).
Input sequentially via PF. The input unit 55 outputs each pixel data to the delay circuits 56a to 56d having the same configuration as the delay circuit 31 provided in the horizontal interpolation circuit 15a described above.

The filter circuit 57 has the same configuration as that of the filter circuit 52 provided in the horizontal correlation detection circuit 16a, and includes adders 57a, 57b, 57c, 5
7d. This filter circuit 52 includes [1, 0, 6, 0, 1] / 8 of [1, 0, 6, 0, 1] / 8 by an adder 57b, an adder 57c, and an adder 57d, similarly to the filter circuit 53 shown in the horizontal correlation detection circuit 16a described above. A filter is formed, and an adder 57a forms a [1, 0, 1] / 2 filter. In the vertical direction correlation detector circuit 16b, a selector similar to the horizontal correlation detection circuit 16a described above, the filter circuit 57b is the pixel data of interest to calculate a correlation value C _v, 57c, without passing through the 57d Circuit 5
8 may be input.

The selector circuit 58 has the same configuration as the selector circuit 53 provided in the horizontal correlation detection circuit 16a, and has selectors 58a and 58b.
The operation of each of the selectors 58a and 58b is controlled by receiving a control signal from the control unit 10.

The selector 58b is controlled to pass the output from the adder 57b, 57c, 57d or (or) the output from the delay circuit 56b in the pixel where the pixel data G exists, and to control the pixel in which the pixel data G does not exist. Then adder 5
It is controlled to pass the output from 7a.

[0090] The output unit 59 outputs the vertical correlation value C _v inputted from the selector 58b. The output unit 59 is connected to the noise removing unit 17 and outputs the vertical correlation value _Cv to the noise removing unit 17.

The correlation value detecting section 16 thus configured
Since the correlation value C is calculated only by the pixel data G, for example, by configuring a circuit using Expressions 3 to 6, the horizontal correlation value _Ch and the vertical correlation value are not affected by the color of the subject. The value C _v can be calculated.

As shown in FIG. 2, the noise removing unit 17
It comprises a noise elimination circuit 17a connected to the horizontal correlation detection circuit 16a and a noise elimination circuit 17b connected to the vertical correlation detection circuit 16b. These noise elimination circuits 17a and 17b have the same configuration as shown in FIG.

As shown in FIG. 18, the noise removing units 17a and 17b output the correlation values C from the correlation detection circuits 16a and 16b.
, A subtraction circuit 61 to which the absolute correlation value C is input, and a subtraction correlation value C
Is input to the limit circuit 62.

The absolute value conversion circuit 60 is, for example, an Ex. It comprises an OR gate 60a and an adder 60b. This absolute value conversion circuit 60 performs absolute value conversion on the input correlation value C,
Take a positive value. The absolute value conversion circuit 60 outputs the absolute value of the correlation value C to the subtraction circuit 61.

The subtraction circuit 61 comprises, for example, a subtractor 61a. The subtractor 61a receives the correlation value C from the absolute value conversion circuit 60. Further, a control signal indicating a subtraction value for subtracting a predetermined value from the correlation value C input from the control unit 10 is input to the subtractor 61a. And this subtractor 6
1a subtracts the subtraction value from the correlation value C according to the control signal. As described above, the subtractor 61a performs the subtraction process to subtract the output of the correlation value C as shown by the solid line in FIG. 19A, as indicated by the dotted line in FIG. 19A. Then, the subtraction circuit 61 outputs the subtracted correlation value C to the limit circuit 62.

The limit circuit 62 includes, for example, the inverter 6
2a and an AND gate 62b. The limit circuit 62 performs a process so that the correlation value C whose output has become a negative value after being subtracted by the subtraction circuit 61 becomes 0 as shown in FIG. 19B. Then, the limit circuit 62 outputs the correlation value C subjected to such processing to the offset circuit 18.

The noise removing unit 17 removes a small correlation value C by performing a subtraction process from the input correlation value C, so that noise in a small value can be removed. Therefore, the noise removing unit 17 can remove the correlation value C calculated for the noise of the CCD 3 itself or the like in order to calculate the correlation value C by passing through the BPF, for example. Further, according to the noise removing unit 17, when the pixel data generated by the CCD 3 includes a noise component, even if the correlation value C is calculated for the noise, a minute correlation value is subtracted. . Therefore, according to the noise removing unit 17, the interpolation pixel data can be weighted using the correlation value C with little noise, and a false color signal is generated in the output image,
The image does not deteriorate.

As shown in FIG. 2, the offset circuit 18 includes an offset circuit 18a to which the horizontal correlation value _Ch is input from the noise removal circuit 17a and an offset circuit to which the vertical correlation value _Cv is input from the noise removal circuit 17b. 18b. These offset circuits 18a and 18b have a similar configuration as shown in FIG.

The offset circuits 18a and 18b correspond to FIG.
As shown in FIG. The adder 65 receives the correlation value C from the above-described noise removal circuits 17a and 17b. The adder 65 is connected to the control unit 1
A control signal indicating an offset value from 0 to a predetermined value is input.

When the correlation value C is input from the noise removing units 17a and 17b, the adder 65 adds the offset value indicated by the control signal. And this adder 6
5 adds the input correlation value C and offset value and outputs the result to the normalization circuit 19. In other words, the offset circuits 18a and 18b include, for example, the noise removing units 17a and 17a.
By adding the offset value to the correlation value C as shown by the dotted line in FIG. 21 from 17b, the correlation value C as shown by the solid line in FIG. 21 is obtained.

As described above, the offset circuits 18a and 18b
By adding the offset value to the correlation value C, a large correlation value C can be provided even if the amplitude of the input correlation value C is about 0. For example, as shown in FIG. 22, the offset circuits 18a and 18b are not capable of obtaining the correlation value C by the above-described correlation value detection unit 16, for example, the pixel data constituting the image data whose color changes for each pixel. If it is, the signal and the high band, even if the amplitude of the vertical correlation value C _v and a horizontal correlation value C _h is very small, that the horizontal correlation value C _h a vertical correlation value C _v to prevent switching to rapidly Can be. That is, according to such offset circuits 18a and 18b, the offset value is set to the correlation value C
, The interpolation pixel data weighted by the correlation value C can be made closer to the direction in which interpolation is performed by arithmetic mean. Therefore, the offset circuits 18a, 18
According to b, even when the amplitude of the input correlation value C is very small, or when the horizontal correlation value _Ch is 1 and the vertical correlation value _Cv is 0 at adjacent pixels, the vertical correlation value _Cv is 0, a horizontal correlation value C _h is not such switching is 1.

[0102] Normalization circuit 19, as shown in FIG. 2, the adder 19 to the offset circuit 18a and a horizontal correlation value from the offset circuit 18b C _h and vertical correlation value C _v is inputted
consists of a, a divider 19b to output from the vertical correlation value C _v and the adder 19a is input.

Such a normalizing circuit 19 comprises an adder 19
In a, the vertical correlation value _Cv and the horizontal correlation value _Ch are added, and the addition result is output to the divider 19b. The divider 19b divides the vertical correlation value _Cv by the addition result. Then, the normalization circuit 19 calculates a vertical correlation value C _v of the following formula 7. Here, a horizontal correlation value C _h can be expressed as shown in the following formula 8 as a relative value of the vertical correlation value C _v.

[0104]

(Equation 3)

The bias correction circuit 20 comprises an adder 20a, as shown in FIG. This bias correction circuit 20
The vertical correlation value C _V represented by the above equation 7 is input from the normalization circuit 19. The adder 20a receives the correction value α from the control unit 10. The correction value α is generated by the control unit 10 and is adjusted within a range of −1 to 1 according to the setting of the CCD 3 and the like, for example.

The bias correction circuit 20 receives the vertical correlation value C _V , the correction value α input from the control unit 10, and adds the vertical correlation value C _V to the correction value α. . As described above, the bias correction circuit 20 performs the addition processing to set the vertical correlation value C _V to a value as shown in Expression 9 below.

[0107]

(Equation 4)

Accordingly, when the vertical correlation value C _v indicated by a dotted line in FIG. 24 is input, for example, as shown in FIG. It can be changed as shown by the solid line. That is, according to the bias correction circuit 20, by adding processing the correction value α to the vertical correlation value C _v, the same level by the distortion or the like of the vertical correlation value C _v and a horizontal correlation value C _h a signal from CCD3 However, by controlling the correction value α input from the control unit 10, the value of the vertical correlation value _Cv can be controlled and corrected. In addition, the bias correction circuit 20 cannot calculate the relationship between the correlation in the vertical direction and the correlation in the horizontal direction equally due to, for example, the aspect ratio of the CCD or distortion generated when detecting an analog signal output from the CCD. However, by controlling the correction value α from the control unit 10, the horizontal correlation value _Ch and the vertical correlation value C _v
And balance can be controlled.

[0109] enhancement and reduction circuit 21, as shown in FIG. 25, a subtractor 21a which vertical correlation value C _v is inputted from the bias correction circuit 20, subjected to subtraction processing vertical correlation value C _v is inputted It comprises a multiplier 21b, an adder 21c to which the vertical correlation value C _v subjected to the multiplication processing is inputted, and a limiter 21d to which the vertical correlation value C _v subjected to the addition processing is inputted.

The subtractor 21a outputs 0 from the bias correction circuit 20.
Enter the vertical correlation value C _v has a value of up to 1, the subtraction processing is performed on the vertical correlation value C _v. This subtracter 21a
Performs only subtraction 0.5 from the vertical correlation value C _v. The multiplier 21b multiplies the processing in the vertical correlation value C _v based on the control signal indicating the multiplication value to be input from the control unit 10. Adder 2
1c performs 0.5 only addition processing in the vertical correlation value C _v.
Limiter 21d limits the vertical correlation value C _v inputted within a certain range.

When the vertical correlation value C _v is input from the bias correction circuit 20, the enhancement / reduction circuit 21 first
Subtractor 21a performs 0.5 only subtracted from the vertical correlation value C _v in, then, the multiplication process is performed in a vertical correlation value C _v subjected to subtraction processing. In this case, changing to indicate the inclination of the vertical correlation value C _v of characteristics shown by the solid line in FIG. 26 in accordance with the multiplication value to be input from the control unit 10 by a dotted line or dashed line in FIG. 26. Next, the multiplied vertical correlation value C
_{The value obtained} by subtracting 0.5 from the above-described subtractor 21a into _v is added to _v.
Add by 1c. Next, the added vertical correlation value C
Limiter 21 so that _v takes a value in the range of 0 to 1.
Regulate with d.

[0112] emphasis-reduction circuit 21 in this way, due to the multiplication process is subjected to a vertical correlation value C _v multiplication values from the control unit 10, the input-output characteristic of the vertical correlation value C _v as shown in FIG. 26 Change the slope. Therefore, according to the highlight-reducing circuit 21, by changing the multiplication value from the control unit 10, it is possible to change the vertical correlation value C _v. Therefore, according to the emphasizing / reducing circuit 21, when weighting the interpolation pixel data described later, the value of the correlation value for weighting the interpolation pixel data is changed to determine whether the interpolation pixel data emphasizes the correlation. It is possible to control whether interpolation is performed so that the interpolated pixel data approaches the arithmetic mean. According to the emphasis / reduction circuit 21, for example, C
Since the amount of light input to the CD 3 is small, the output from the CCD 3 has a large amount of noise. Even if the correlation value cannot be calculated accurately, the correlation value can be controlled by changing the multiplication value.

As shown in FIG. 2, the weighted addition circuit 22
A subtractor 22a to produce a normalized horizontal correlation values C _h enter the vertical correlation value C _v, a multiplier 22b for normalized horizontal correlation values C _h is input, the vertical correlation value C _v is input And an adder 22d to which interpolation pixel data in the vertical and horizontal directions is input.

The weighted addition circuit 22 inputs the vertical correlation value _Cv from the enhancement / reduction circuit 21 to the subtractor 22a and the multiplier 22c. In the subtractor 22a, the vertical correlation value C
_The horizontal correlation value _Ch is generated by subtracting _v from 1. Then, the subtractor 22a outputs the horizontal correlation value _Ch to the multiplier 22b.

The multiplier 22b includes a vertical interpolation circuit 15b
From the pixel data in the vertical direction and the subtractor 22a
, The horizontal correlation value _Ch is input. The multiplier 22b
Multiplying process and an interpolation pixel data in the inputted vertical and horizontal correlation values C _h. Thus multiplier 22b performs weighting by multiplying a horizontal correlation value C _h to the interpolated pixel data in the vertical direction.

The multiplier 22c is provided with a horizontal interpolation circuit 15a.
, Horizontal pixel interpolation pixel data and a vertical correlation value C _v are input. The multiplier 22c calculates the input horizontal interpolation pixel data and the vertical correlation value C
Multiplies with _v . Thus multiplier 22c performs weighting by multiplying a vertical correlation value C _v to the interpolated pixel data in the horizontal direction.

In the adder 22d, the interpolation pixel data in the horizontal direction weighted by the multiplier 22c and the
The interpolation pixel data in the vertical direction weighted by 2b is input. The adder 22d performs an addition process on the input interpolation pixel data in the horizontal direction and the input interpolation pixel data in the vertical direction. As described above, the adder 22d performs the addition processing to obtain the interpolation pixel data weighted by the correlation values in the vertical and horizontal directions. Then, the adder 22d outputs the interpolated pixel data to the contour correction circuit 23.
Output to

The contour correction circuit 23 is connected to the adder 22d of the weighted addition circuit 22. This contour correction circuit 23
Is supplied with the interpolation pixel data from the adder 22d and the contour emphasis signal from the control unit 10. This contour emphasis signal is a signal for compensating the response deterioration of the CCD 3 and emphasizing the sharpness. Then, the contour correction circuit 23
Then, the input edge enhancement signal and the interpolated pixel data are added and output to the Y / C conversion unit 24.

The Y / C converter 24 is connected to the contour correction circuit 23, and receives interpolation pixel data from the contour correction circuit 23. The Y / C converter 24 converts the input interpolated pixel data composed of R, G, and B into a Y / C signal composed of a luminance signal (Y) and a color difference signal (C). Then, the Y / C converter 24 outputs the Y / C signal obtained by converting the interpolated pixel data to the color difference signal suppressor 25.

The color difference signal suppressing section 25 includes a Y / C converting section 24.
, And a Y / C signal is input from the Y / C converter 24. As shown in FIG. 27, the chrominance signal suppression unit 25 includes a BG data suppression circuit 25 to which a chrominance BG of pixel data in which one line includes pixel data G and B is input.
a, and an RG data suppression circuit 25b to which a color difference RG of pixel data in which one line is composed of pixel data G and R is input.

The BG data suppression circuit 25a is connected to the input section 7 to which the color difference B'-G 'of the interpolated pixel data G', B 'is input.
0a to 70c and the color difference B′− from the input units 70a to 70c.
G ′ is input to the absolute value converters 71a to 71c, and the color difference B′−G ′ that has been converted to the absolute value from the absolute value converters 71a to 71c.
, An arithmetic unit 73 to which the comparison results from the comparators 72a to 72c are input, a selector 74 to which the operation results from the arithmetic unit 73 are input, and pixel data to be input from the selector 74. And an output unit 75.

The input section 70a receives the color difference B'-
G ′ is input, the input unit 70b receives the color difference B′−G ′ in the horizontal direction, and the input unit 70c receives the color difference B′−G ′ weighted by the correlation value. Input unit 70a
Outputs the input color difference B'-G 'to the absolute value converter 71a, the input unit 70b outputs the input color difference B'-G' to the absolute value converter 71b, and the input unit 70c outputs the input color difference B ' −
G ′ is output to the absolute value converter 71c.

The absolute value converters 71a to 71c are, for example, E
x. It comprises an OR gate 76 and an adder 77. The absolute value converters 71a to 71c perform absolute value conversion on the input color difference B'-G 'to obtain positive values. Absolute value converter 71a
To 71c output the color difference B′-G ′ subjected to the absolute value conversion to the comparators 72a to 72c.

The comparator 72a includes an absolute value converter 71a
Is input at a terminal B, and the color difference B'-G 'that has passed through an absolute value converter 71c is input at a terminal A. The comparator 72b includes an absolute value converter 71
The color difference B′-G ′ that has passed through a is input at the terminal A, and the color difference B′-G ′ that has passed through the absolute value converter 71b is input at the terminal B. The comparator 72c includes an absolute value converter 71
The color difference B′-G ′ that has passed through b is input at a terminal A, and the color difference B′-G ′ that has passed through the absolute value converter 71c is input at a terminal B. These comparators 72a to 72c
By comparing the magnitudes of the color differences B'-G 'inputted at the terminals A and B, and judging that the color difference B'-G' inputted at the terminal A is large, the comparison result H is outputted to the arithmetic unit 73. When the color difference B′-G ′ input at the terminal A is determined to be small, the comparison result L is output to the arithmetic unit 73.

The arithmetic unit 73 includes comparators 72a to 72
The comparison result is input from c and a control signal is input from the control unit 10. The calculator 73 generates a calculation result based on the comparison result and the control signal, and
Output to

The arithmetic unit 73 outputs the operation result 11 when the control signal H is input, and generates the operation result based on the comparison results from the comparators 72a to 72c when the control signal L is input. When the comparison result of each of the comparators 72a, 72b, and 72c is (H, L, X), the arithmetic unit 73 outputs the calculation result 00, and the comparison result of each of the comparators 72a, 72b, and 72c is (X,
In the case of (H, L), the operation result 01 is output, and the comparison results of the comparators 72a, 72b, 72c are (L, X,
In the case of H), the calculation result 10 is generated and output to the selector 74.

The selector 74 receives the calculation result from the calculator 73 and also receives the color difference B'-G 'from the input units 70a-70c. This selector 74 has 11 terminals and 10 terminals, and the color difference B′− input by the input unit 70c.
G 'is input, the color difference B'-G' input at the input unit 70b is input at the 01 terminal, and the color difference B'-G 'input at the input unit 70a is input at the 00 terminal. Also, this selector 7
4 outputs the color difference B'-G 'input at terminal 11 when the operation result 11 is input, and outputs the color difference B'-G' input at terminal 10 when the operation result 10 is input. When the result 01 is input, the color difference B'-G 'input at the terminal 01 is input.
Is output, and when the calculation result 00 is input, the color difference B′-G ′ input at the 00 terminal is output.

The RG data suppression circuit 25b is connected to the input unit 70
The color difference R'-G 'is input to a to 70c, and the color difference R'-G' is passed through the absolute value generator 71, the comparator 72, the arithmetic unit 73, and the selector 74 to obtain the minimum color difference R'-G '.
G ′ is selected and output by the output unit 75.

Therefore, such a color difference signal suppressing section 2
According to FIG. 5, for example, as shown in FIG. 28A, for example, interpolation pixel data R _v , G _v for pixel data R, G arranged in the vertical direction and pixel data R, G for pixel data R, G arranged in the horizontal direction are used. The smallest interpolation pixel data R _h , G _h among the color differences between the interpolation pixel data R _h , G _h and the weighted interpolation pixel data R _c , G _c are selected. Further, the color difference signal suppressing unit 25
Selects the interpolated pixel data R'-G 'which is closest to 0 among the interpolated pixel data as shown in FIG. 28 (b).

The color difference signal suppressing section 25 selects and outputs the interpolated pixel data having the smallest absolute value of the color difference signal from the interpolated pixel data input from the input sections 70a to 70c. Therefore, such a color difference signal suppressing unit 25 prevents a false color from being added to a color edge or the like when image data is generated with interpolation pixel data weighted by a correlation value in a band where a correlation cannot be obtained. Can be. Therefore, according to the color difference signal suppressing section 25, it is possible to prevent the aliasing distortion of the color even in the frequency band where no correlation is observed.

The output section 75 outputs the interpolated pixel data output from the selector 74 to the output section 26. Output unit 26
Are a recording medium for recording pixel data, a display device, a terminal for outputting to the outside, and the like.

In the above description, an example of processing a camera signal generated by the camera device 1 using the CCD 3 of primary color coding has been described.
As shown in FIG. 29 (a) or FIG. 29 (b), if the solid-state imaging device is a coding solid-state imaging device in which the most colors among the colors indicated by the pixel data included in the image data are arranged in a checkered pattern. And complementary color CCDs.

[0133]

As described above in detail, the camera signal processing apparatus and the camera signal processing method according to the present invention interpolate from at least two directions to generate interpolated pixel data in each direction, and Correlation values indicating the degree of correlation in the two or more directions of the interpolated pixel data generated by the data generation means are detected, and the interpolated pixel data in each direction and the correlation values in each direction generated by the correlation detection means are added. Since the color difference signal of the interpolation pixel data is detected and the color difference signal of the interpolation pixel data in each direction and the color difference signal of the interpolation pixel data to which the correlation value in each direction is added is selected, the color difference signal of the smallest value is selected. Even in a band that cannot be detected, no false color signal is generated in the image. Therefore, according to such a camera signal processing device and a camera signal processing method, when image data is generated using interpolation pixel data weighted by a correlation value in a band where a correlation cannot be obtained, a false color appears at a color edge or the like. Can be prevented from being turned on. Therefore, according to the camera signal processing device and the camera signal processing method, it is possible to prevent color aliasing even in a frequency band where no correlation is seen.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of a camera device.

FIG. 2 is a block diagram illustrating an example of a configuration of a signal processing circuit.

FIG. 3 is a diagram showing an example of an arrangement of pixel data R, G, and B corresponding to each pixel.

FIG. 4 is a diagram illustrating an example of a configuration of a vertical direction interpolation circuit.

FIG. 5 is a diagram showing an example of an arrangement of pixel data G corresponding to each pixel.

FIG. 6 is a diagram illustrating a frequency characteristic of an LPF of [1, 0, 6, 0, 1].

FIG. 7 is a diagram illustrating frequency characteristics of an LPF of [1, 0, 1].

FIG. 8 is a diagram illustrating an example of interpolated pixel data G ′ generated after performing an interpolation process.

FIG. 9 is a diagram illustrating an example of a configuration of a horizontal interpolation circuit.

FIG. 10 is a diagram showing an example of an arrangement of pixel data B corresponding to each pixel.

FIG. 11 is a diagram showing an example of the arrangement of interpolated pixel data B ′ when an arithmetic mean is calculated in the hydraulic direction for pixel data B corresponding to each pixel.

FIG. 12 is a diagram illustrating an example of interpolated pixel data B ′ generated after performing an interpolation process.

FIG. 13 is a diagram illustrating an example of a configuration of a vertical direction interpolation circuit.

FIG. 14 is a diagram illustrating an example of a configuration of an edge processing circuit.

FIG. 15 is a diagram for explaining an example when edge processing is performed by an edge processing circuit.

FIG. 16 is a diagram illustrating an example of a configuration of a horizontal correlation detection circuit.

FIG. 17 is a diagram illustrating an example of a configuration of a vertical direction correlation detection circuit.

FIG. 18 is a diagram illustrating an example of a configuration of a noise removal circuit.

FIGS. 19A and 19B are diagrams illustrating an example when a process is performed on a correlation value input by a noise removal circuit, where FIG. 19A illustrates an example when a subtraction process is performed on the correlation value, and FIG. It is a figure showing an example at the time of limiting with a negative value.

FIG. 20 is a diagram illustrating an example of a configuration of an offset circuit.

FIG. 21 is a diagram illustrating an example of a change in input / output characteristics when an offset value is added to a correlation value input by an offset circuit.

FIG. 22 is a diagram illustrating an example of image data in which a color changes for each adjacent pixel data.

FIG. 23 is a diagram illustrating an example of a configuration of a bias correction circuit.

FIG. 24 is a diagram illustrating an example of a change in input / output characteristics when a correction value is added to a correlation value input by a bias correction circuit.

FIG. 25 is a diagram illustrating an example of a configuration of an emphasis / reduction circuit.

FIG. 26 is a diagram illustrating a change in input / output characteristics when a correlation value input by an emphasis / reduction circuit is multiplied.

FIG. 27 is a diagram illustrating an example of a configuration of a color difference signal suppression circuit.

FIG. 28 shows interpolated pixel data R _v and G _v for pixel data R and G arranged in the vertical direction and interpolated pixel data R _h and G _h for pixel data R and G arranged in the horizontal direction in the color difference signal suppression unit. FIG. 10 is a diagram showing an example of selecting interpolation pixel data R _h and G _h having the smallest absolute value among the color differences of weighted interpolation pixel data R _c and G _c .

FIG. 29 is a diagram showing another example of the arrangement of pixel data.

[Explanation of symbols]

Reference Signs List 1 camera device, 15 image data interpolation unit, 15a horizontal interpolation circuit, 15b vertical interpolation circuit, 16 correlation value detection unit, 16a horizontal correlation detection circuit, 16b
Vertical direction correlation detection circuit, 24 Y / C conversion unit, 25 color difference signal suppression unit

Claims (8)

[Claims] 1. A position and / or a surrounding pixel of pixel data generated based on an imaging signal from a solid-state imaging device to which imaging light is incident via a color filter having a different spectral sensitivity corresponding to each pixel. Interpolated pixel data generating means for interpolating from at least two directions based on data to generate interpolated pixel data in each direction, and correlation of the interpolated pixel data generated by said interpolated pixel data generating means in said two or more directions Correlation detection means for detecting a correlation value indicating the degree of the interpolation pixel data in each direction generated by the interpolation pixel data generation means and interpolation pixel data to which the correlation value in each direction generated by the correlation detection means is added. A color difference signal detecting means for detecting a color difference signal, a color difference signal of interpolation pixel data in each direction and a color difference signal of interpolation pixel data to which a correlation value in each direction is added Camera signal processing comprising: selecting means for selecting and outputting a color difference signal having the smallest value; and image generating means for generating an image based on the interpolated pixel data selected by the selecting means. apparatus. 2. A control means for controlling the selection means, wherein the control means selects one of a color difference signal of interpolation pixel data in each direction and a color difference signal of interpolation pixel data to which a correlation value in each direction is added. 2. The camera signal processing device according to claim 1, wherein the selection unit is controlled so as to select a signal. 3. The camera signal processing device according to claim 1, wherein the selection unit selects and outputs a color difference signal having the smallest value among color difference signals having a value equal to or greater than a predetermined value. 4. An absolute value conversion circuit for converting the interpolation pixel data in each direction and the color difference signal of the interpolation pixel data to which the correlation value in each direction is added, into an absolute value, wherein the selecting means includes an absolute value conversion circuit. 2. The camera signal processing device according to claim 1, wherein a color difference signal having the smallest value is selected from the color difference signals from the camera. 5. A position and / or surrounding pixels of pixel data generated based on an imaging signal from a solid-state imaging device to which imaging light is incident via a color filter having a different spectral sensitivity corresponding to each pixel. Interpolated from at least two or more directions based on the data to generate interpolated pixel data in each direction, and a correlation value indicating the degree of correlation in the two or more directions of the interpolated pixel data generated by the interpolated pixel data generating means. Respectively, and a color difference signal of the interpolation pixel data to which the interpolation pixel data in each direction and the correlation value in each direction generated by the correlation detection means are added is detected. Selecting the color difference signal having the smallest value from among the color difference signals of the interpolation pixel data to which the correlation value has been added, and generating an image based on the selected interpolation pixel data. Camera signal processing method according to claim. 6. The camera according to claim 5, wherein any one of a color difference signal of the interpolation pixel data in each direction and a color difference signal of the interpolation pixel data to which a correlation value in each direction is added is selected. Signal processing method. 7. The camera signal processing method according to claim 5, wherein a color difference signal having the smallest value is selected from color difference signals having a value equal to or greater than a predetermined value and output. 8. An absolute value of a color difference signal of the vertical interpolation pixel data, the horizontal interpolation pixel data, and the interpolation pixel data to which the correlation value is added, and selects a color difference signal having the smallest value from the absolute value of the color difference signals. The camera signal processing method according to claim 5, wherein