JP2005086625A - Defective pixel correction circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that deterioration of a high frequency signal is generated in defective pixel correction of a solid-state image pickup device, etc. <P>SOLUTION: To RGB video signals to be inputted, average value calculation circuits 2a, 2b, 2c output center pixel signals and interpolation average signals and a control circuit 11 outputs a defective pixel correction channel ch1 and a reference channel ch2. A channel switching circuit 3 selects interpolation average signals Zav, Fav equivalent to the correction channel and the reference channel and determines a correction coefficient Kdef according to ratio of its signal level by a coefficient determination circuit 5. A selection circuit 4 selects a center pixel signal Fcnt of the reference channel and calculates Fdef=Fcnt-Fav by a subtractor 6. Furthermore, the Fdef is added with the interpolation average signal Zav of a defective signal by an adder 8 after multiplying the correction coefficient Kdef by a multiplier 7. Clipping is performed in a prescribed signal level by a clipping circuit 9, switched to a signal as which is the defective pixel and outputted by an output switching circuit 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a defective pixel correction circuit that corrects pixel defects existing in a solid-state image sensor in an image pickup apparatus using a solid-state image sensor such as a CCD.

  In recent years, solid-state imaging devices, especially CCD (Charge Coupled Device) type imaging devices (hereinafter simply referred to as “CCD”) have come to be most widely used as imaging devices. In many types of video cameras, an imaging method called a three-plate type using three CCDs is often used. In this method, an optical signal incident from a lens is decomposed into optical signals of three primary colors of R, G, and B by a color separation prism, and each is converted into an electric signal by a solid-state imaging device.

  In many cases, a defective pixel is generated in a CCD due to a manufacturing process, and it is difficult to obtain a CCD having no defective pixel with a sufficient yield. For this reason, usually, a CCD including a defective pixel is often used as an imaging device. In this case, an output signal corresponding to the defective pixel is corrected by a defective pixel correction circuit.

  As a conventional defect correction apparatus, for example, there is one disclosed in Japanese Patent Laid-Open No. 9-284783, and the configuration is shown in FIG. In FIG. 8, 1a, 1b, and 1c are video signal input terminals, 2a, 2b, and 2c are average value calculation circuits, 71 is a channel switching circuit, 4 is a selection circuit, 72 and 73 are subtractors, 74 is a selection circuit, and 8 is a selection circuit. An adder, 9 is a clip circuit, 10 is an output switching circuit, 75 is a control circuit, and 20a, 20b, and 20c are output terminals. FIG. 2 shows the configuration of the average value calculation circuits 2a, 2b, and 2c. 51 and 52 are delay elements, 53 is an adder, and 54 is a gain circuit.

  The operation of the conventional defective pixel correction circuit configured as described above will be described below.

  In this conventional defect correction apparatus, when there is defect data (hereinafter referred to as “defect channel”) in a certain color channel, another color channel without defect data (hereinafter referred to as “correction channel”) is input. Correction data is generated using the signal, and the defect data is replaced with the correction data.

  In FIG. 8, video signal input terminals 1a, 1b, and 1c are input terminals of a defective pixel correction circuit, and a digital signal obtained by converting a CCD analog output signal corresponding to the three primary colors R, G, and B into a digital value is input. The Here, since the signal data is generally output from the CCD for each pixel, this digital signal is usually discretized at a period corresponding to one pixel.

  The R, G, B input signals are input to the average value calculation circuits 2a, 2b, 2c, respectively. In the average value calculation circuit shown in FIG. 2, the delay element 51 delays the input signal Xin by one data. The output signal of the delay element 51 is output as the center pixel signal Xcnt.

  The delay element 52 further delays the output signal of the delay element 51 by one data. The adder 53 adds the input signal Xin and the output signal of the delay element 52, and the gain circuit 54 multiplies the gain by 1/2 by bit shift or the like. In other words, the output of the gain circuit 54 is a signal obtained by adding and averaging the previous pixel and the next pixel with respect to the central pixel signal Xcnt, and outputs this as the interpolation average signal Xav. Note that the delay elements 51 and 52 described above can be configured by D flip-flops, for example.

  Among the output signals of the average value calculation circuits 2a, 2b, and 2c, the center pixel signals Rcnt, Gcnt, and Bcnt are input to the selection circuit 4 and the output switching circuit 10. Interpolated average signals Rav, Gav, and Bav are input to the channel switching circuit 71.

  Here, a channel signal C input from an external defect detection means (not shown) is input to the control circuit 75 to generate a channel signal ch1 designating the defective channel, and a channel indicating the other two channels. Signals chJ and chL are generated. These channel signals chJ, ch1, and chL are input to the channel switching circuit 71.

  The configuration of the channel switching circuit 71 is shown in FIG. In FIG. 9, reference numerals 81, 82, and 83 denote selectors, and three signals Rav, Gav, and Bav are input to each selector. Each selector selects a signal of a color channel specified by the channel signal chJ, ch1, or chL, and outputs it as signals SJ, SK, SL. Here, as described above, ch1 is a channel signal indicating a defective channel, and signal SK is a signal of a defective channel corresponding thereto. Further, chJ and chL are two channel signals other than the defective channel, and signals SJ and SL correspond to these, respectively. The subtracter 72 in FIG. 8 generates the difference signal DJ by the operation “DJ = SK−SJ”. The subtractor 73 generates the difference signal DL by the calculation of “DL = SK−SL”.

  The difference signals DJ and DL are input to the control circuit 75, and a control signal CD that specifies the smaller absolute value is output. That is, 0 is designated as the control signal CD when | DJ | <| DL |, and 0 is designated as the control signal CD when | DJ |> | DL |. Further, as the channel signal ch2, the channel signal chJ is selected when CD = 0, and the channel signal chL is selected and output when CD = 1. The selection circuit 74 outputs the smaller one of the difference signals DJ and DL as DM based on the control signal CD.

  The selection circuit 4 outputs a correction channel signal Fcnt based on the channel signal ch2, and the adder 8 adds it to the difference signal DM. Further, the clip circuit 9 outputs the clipped data within the video signal level as the correction data Dc.

  The output switching circuit 10 selects and outputs the correction data Dc to the channel having the defective pixel among the central pixel signals Rcnt, Gcnt, Bcnt according to the channel signal ch1 designating the defective channel. Note that the signals of the other two channels having no defective pixel are output as they are.

  The detailed operation of this conventional defective pixel correction circuit will be described with reference to FIGS. As shown in FIG. 10, it is assumed that signal data R (i), G (i), and B (i) are input from the input terminals 1a, 1b, and 1c, but G (i) is defective data.

  First, at time (i−1), signals R (i−1), G (i−1), and B (i−1) are input to the input terminals 1a, 1b, and 1c in FIG. Next, at time i, signals R (i), G (i), and B (i) are input to the input terminals 1a, 1b, and 1c, respectively, and outputs Rcnt, Gcnt, As Bcnt, R (i-1), G (i-1), and B (i-1), which are signals one pixel before, are output. Since there is no defective pixel at the position corresponding to (i-1), the signals R (i-1), G (i-1), and B (i-1) are output from the output switching circuit 10 as they are. The

Next, the operation at time (i + 1) will be described. At time (i + 1), signals R (i + 1), G (i + 1), and B (i + 1) are input to the input terminals 1a, 1b, and 1c, respectively, and the signal R (i) is output to the output switching circuit 10 and the selection circuit 4. , G (i), B (i) are input. In the average value calculation circuits 2a, 2b, and 2c, the interpolation average signals RAV, GAV, and BAV represented by the formula (Equation 1) are calculated and input to the channel switching circuit 71.
Rav = 1/2 * {R (i + 1) + R (i-1)}
Gav = 1/2 * {G (i + 1) + G (i-1)}
Bav = 1/2 * {B (i + 1) + B (i-1)} (Equation 1)
On the other hand, at the time (i + 1), the control circuit 75 inputs the G channel code corresponding to the defect data G (i) as the channel signal C as described above. As a result, a channel signal corresponding to G is output as the channel signal ch1. In addition, channel signals corresponding to R and B are output as channel signals chJ and chL, respectively. That is, the channel switching circuit 71 outputs SJ = Rav, SK = Gav, and SL = Bav.

Here, the difference signals DJ and DL are respectively generated as shown by the equation (Equation 2) and input to the selection circuit 74 and the control circuit 75.
DJ = SK-SJ = Gav-Rav
DL = SK-SL = Gav-Bav ―――― (Equation 2)
As can be seen from FIG. 10, the following equation (Equation 3) holds.
DL = Gav-Bav <DJ = Gav-Rav ―――― (Equation 3)
Therefore, the control circuit 75 outputs 1 that designates the L side as the control signal CD, and the selection circuit 74 outputs the difference signal DM represented by (Equation 4).
DM = Gav-Bav
= 1/2 * {G (i + 1) + G (i-1)}-1/2 * {B (i + 1) + B (i-1)} (Equation 4)
Further, the selection circuit 4 outputs a signal B (i) based on the channel signal ch2, and the adder 8 generates a signal G ′ (i) represented by the following equation (Equation 5).
G ′ (i) = B (i) + DM = B (i) + Gav−Bav
= B (i) + 1/2 * {G (i + 1) + G (i-1)}-1/2 * {B (i + 1) + B (i-1)} (Equation 5)
Thus, the correction data Dc is output from the clip circuit 9. In the output switching circuit 10, the defect data G (i) is output after being replaced with the correction data represented by (Equation 5). That is, as shown in FIG. 10A, by replacing the defective pixel data G (i) of the G channel with G ′ (i), highly accurate defect correction can be performed even in an image including a high frequency component. .
Japanese Patent Laid-Open No. 9-284783 (page 7-9)

  However, the above technique has a problem that it is easily affected by noise. Since the output signal level of the normal B signal is about 1/3 of that of the G signal, the S / N ratio is about 9 dB worse. In the above-described example of defective pixel correction, since the G signal is corrected using the information of the B signal, the noise component of the B signal often appears as a correction result of the G signal. That is, the defect-corrected G signal may show flickering and weakness due to the noise of the B signal.

  In order to avoid the influence of noise, it is not necessary to use the B signal. However, in the example of FIG. 10, when the G signal having a defective pixel is corrected with the R signal, the correction result is the G shown in FIG. "(I), the high-frequency component of the defective pixel portion is extremely reduced, and there is a possibility of coloring.

  In the example of FIG. 10C, the signal level is the largest in the R signal, the smallest in the G signal, and a defective pixel in the G signal. In this case, if the G signal is corrected with the R signal in order to avoid the influence of noise, a correction result protruding like G ″ (i) shown in the figure is obtained. That is, in an actual image, In the reddish image, the correction part appears as a white bright spot, which is very noticeable.

  The present invention solves the above-described conventional problems. In the defective pixel correction in the imaging apparatus, even when the video signal pattern around the defective data has a high frequency, the defective data is corrected correctly and the influence of noise is reduced. An object of the present invention is to provide a defective pixel correction circuit that is difficult to receive.

  In order to solve this problem, the present invention corrects defect data by changing the gain of a high-frequency component to be corrected according to the signal level of a color channel having defect data and the signal level of a reference color channel for generating correction data. To do.

  That is, the defective pixel correction circuit according to the present invention includes a first calculation unit that generates a first correction signal from a first video signal that is a defective pixel correction target, and a second video signal that is referred to for correction. Second computing means for generating a second correction signal; correction coefficient generating means for generating a correction coefficient from at least one of the first and second video signals; the first and second correction signals; And a third computing means for generating a third correction signal from the correction coefficient, and an output switching circuit for switching and outputting the first video signal and the third correction signal, wherein the third computing means comprises: A multiplier for multiplying the second correction signal and the correction coefficient, and an adder for adding the output of the multiplier and the first correction signal. If it corresponds to the high-frequency component of video signal 2 Since the defective pixels are corrected by changing the correction coefficient of the correction signal, that is, the gain, the defect data is corrected correctly regardless of whether the video signal pattern around the defect data has a high frequency or high saturation. can do.

  As described above, according to the present invention, it is possible to perform defective pixel correction with high accuracy even in an image with many high-frequency components, and it is possible to perform defective pixel correction with little correction error even in an image with high saturation. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a defective pixel correction circuit according to Embodiment 1 of the present invention.

  In FIG. 1, 1a, 1b, and 1c are video signal input terminals, 2a, 2b, and 2c are average value calculation circuits, 3 is a channel switching circuit, 4 is a selection circuit, 5 is a coefficient determination circuit, 6 is a subtractor, and 7 is A multiplier, 8 is an adder, 9 is a clip circuit, 10 is an output switching circuit, 11 is a control circuit, and 20a, 20b, and 20c are output terminals.

  The operation of the signal processing circuit according to the first embodiment configured as described above will be described below. In addition, about the same component as background art, the same code | symbol is used and description is abbreviate | omitted.

  In FIG. 1, video signal input terminals 1a, 1b and 1c are input terminals of a defective pixel correction circuit, and a digital signal obtained by converting a CCD analog output signal corresponding to the three primary colors R, G and B into a digital value is input. The Here, since the signal data is generally output from the CCD for each pixel, this digital signal is usually discretized at a period corresponding to one pixel.

  R, G, and B input signals are respectively input to average value calculation circuits 2a, 2b, and 2c having the configuration shown in FIG. Among the output signals of the average value calculation circuits 2a, 2b, and 2c, the center pixel signals Rcnt, Gcnt, and Bcnt are input to the selection circuit 4 and the output switching circuit 10. Interpolated average signals Rav, Gav, and Bav are input to the channel switching circuit 3. Here, a channel signal C input from an external defect detection means (not shown) is input to the control circuit 11 to generate a channel signal ch1 designating the defective channel, and to the channel switching circuit 3 and the output switching circuit 10. Entered. Further, a correction channel signal ch2 used for correcting the defective pixel is generated and input to the channel switching circuit 3 and the selection circuit 4.

The configuration of the channel switching circuit 3 is shown in FIG. In FIG. 3, reference numerals 61 and 62 denote selectors, and three signals Rav, Gav, and Bav are input to each selector. The selector 61 selects a color channel signal designated by the channel signal ch2 and outputs it as a signal Fav.
The selector 62 selects a color channel signal designated by the channel signal ch1 and outputs it as a signal Zav.

  Here, as described above, ch1 is a channel signal indicating a defective channel to be corrected, and signal Zav is a signal of a defective channel corresponding to this. Further, ch2 is a correction channel signal to be referred to for correcting the defective channel, and the signal Fav corresponds to this. The interpolated average signal Fav is input to the coefficient determining circuit 5 and the subtracter 6, and the interpolated average signal Zav is input to the coefficient determining circuit 5 and the adder 8. The coefficient determination circuit 5 calculates a correction coefficient Kdef from the interpolation average signal Zav of the defective channel and the interpolation average signal Fav of the correction channel, and outputs it to the multiplier 7. Here, the configuration of the coefficient determination circuit 5 is assumed to comprise a divider 66 as shown in FIG.

  The selection circuit 4 outputs the center pixel signal Fcnt of the correction channel based on the channel signal ch2, and the subtracter 6 subtracts it from the interpolation average signal Fav. The subtraction result Fdef is multiplied by the coefficient Kdef in the multiplier 7 and further added to the interpolation average signal Zav of the defective channel in the adder 8.

  Further, the clipping circuit 9 performs a clipping process so that the correction signal does not exceed the upper limit value and the lower limit value, and is output as correction data Dc. The output switching circuit 10 selects and outputs the correction data Dc to the channel having the defective pixel among the central pixel signals Rcnt, Gcnt, Bcnt according to the channel signal ch1 designating the defective channel. Note that the signals of the other two channels having no defective pixel are output as they are.

  The operation of the embodiment configured as described above will be described with reference to FIGS. Assume that signal data R (i), G (i), and B (i) shown in FIG. 5 are input from the input terminals 1a, 1b, and 1c, and G (i) is defective data.

  First, at time (i-1), signals R (i-1), G (i-1), and B (i-1) are input to the input terminals 1a, 1b, and 1c in FIG. Next, at time i, signals R (i), G (i), and B (i) are input to the input terminals 1a, 1b, and 1c, respectively, and outputs Rcnt, Gcnt, As Bcnt, R (i-1), G (i-1), and B (i-1), which are signals one pixel before, are output. Since there is no defective pixel at the position corresponding to (i-1), the signals R (i-1), G (i-1), and B (i-1) are output from the output switching circuit 10 as they are. The

Next, the operation at time (i + 1) will be described. At time (i + 1), signals R (i + 1), G (i + 1), and B (i + 1) are input to the input terminals 1a, 1b, and 1c, respectively, and the signal R (i) is input to the output switching circuit 10 and the selection circuit 4. , G (i), B (i) are input. In the average value calculation circuits 2a, 2b, and 2c, interpolation average signals Rav, Gav, and Bav represented by the equation (Equation 6) are calculated, and these are input to the channel switching circuit 3.
Rav = 1/2 * {R (i + 1) + R (i-1)}
Gav = 1/2 * {G (i + 1) + G (i-1)}
Bav = 1/2 * {B (i + 1) + B (i-1)} (Equation 6)
On the other hand, at the time (i + 1), the control circuit 11 receives the G channel code corresponding to the defect data G (i) as the channel signal C as described above. As a result, a channel signal corresponding to G is output as the channel signal ch1. A channel signal corresponding to R is output as the channel signal ch2. That is, the channel switching circuit 3 outputs Fav = Rav and Zav = Gav.

Next, the coefficient determination circuit 5 calculates the correction coefficient Kdef by the following equation (Equation 7) and outputs it to the multiplier 7.
Kdef = Zav / Fav = Gav / Rav
= [1/2 * {G (i + 1) + G (i-1)}] / [1/2 * {R (i + 1) + R (i-1)}] ――――― (Equation 7)
The selection circuit 4 outputs a signal R (i) based on the channel signal ch2, and the adder 8 generates a signal G ′ (i) represented by the following equation (Equation 8).
G ′ (i) = Zav + Kdef × (Fcnt−Fav)
= Gav + Gav / Rav × (R (i) −Rav) (Equation 8)
Thus, the correction data Dc is output from the clip circuit 9. In the output switching circuit 10, the defect data G (i) is output after being replaced with the correction data represented by (Equation 8).

  Here, FIG. 5A and FIG. 5B show operations when there is a large difference between the signal levels of the G channel having defect data and the R channel used as a reference for defect correction.

  In FIG. 5A, the signal level of the R channel used as a reference for defect correction is small, but the defect corrected G channel has a large amplitude as a high frequency component. In FIG. 5B, the signal level of the R channel used as a reference for defect correction is large, but the high-frequency component is suppressed small in the defect corrected G channel.

  As apparent from comparison with FIGS. 10B and 10C, the ratio of the signal levels of R, G, and B in each pixel, that is, the hue does not change greatly in the three adjacent pixels. This is close to the nature of the actual image, and the correction error due to defect correction is small.

  That is, even in an image having a high saturation and a high frequency component, highly accurate defect correction can be performed according to the present embodiment.

The coefficient determination circuit 5 may be configured by a divider 66 and a multiplier 67 as shown in FIG. 6, and may be multiplied by the coefficient K1. In this case, the calculation result Kdef of the coefficient determination circuit 5 is as shown in (Equation 9).
Kdef = K1 × Zav / Fav (Equation 9)
Further, the configuration of the coefficient determination circuit 5 may be configured by a subtracter 68 and a multiplier 67 as shown in FIG. In this case, the calculation result Kdef of the coefficient determination circuit 5 is as shown in (Equation 10).
Kdef = K2 × (Zav−Fav) ―――― (Equation 10)
Further, the coefficient determination circuit 5 may compare the signal levels of Zav and Fav and change the calculation formula of Kdef according to the result.

  The defective pixel correction circuit according to the present invention is useful as defective pixel correction in a device that handles a video signal, and is particularly suitable for pixel defect correction in an imaging apparatus using a solid-state imaging device.

1 is a block diagram showing a configuration of a defective pixel correction circuit according to Embodiment 1 of the present invention. The figure which shows the structure of the average value calculation circuit by Embodiment 1 of this invention. The figure which shows the structure of the channel switching circuit by Embodiment 1 of this invention. The figure which shows the structure of the coefficient determination circuit by Embodiment 1 of this invention. The figure which shows operation | movement of the defective pixel correction circuit by Embodiment 1 of this invention. The figure which shows the structure of the coefficient determination circuit by Embodiment 1 of this invention. The figure which shows the structure of the coefficient determination circuit by Embodiment 1 of this invention. The block diagram which shows the structure of the signal processing circuit of the conventional defective pixel correction circuit The block diagram which shows the structure of the channel switching circuit of the conventional defective pixel correction circuit The figure which shows operation | movement of the defective pixel correction circuit of the conventional defective pixel correction circuit

Explanation of symbols

1a, 1b, 1c Video signal input terminals 2a, 2b, 2c Average value calculation circuit 3 Channel switching circuit 4 Selection circuit 5 Coefficient determination circuit 5 Subtractor 7 Multiplier 8 Adder 9 Clip circuit 10 Output switching circuit 11 Control circuit 20a, 20b, 20c Output terminal 51, 52 Delay element 53 Adder 54 Gain circuit 61, 62 Selector 66 Divider 67 Multiplier 68 Subtractor 71 Channel switching circuit 72, 73 Subtractor 74 Select circuit 75 Control circuit 81, 82, 83 Selector

Claims (14)

A defective pixel correction circuit that corrects a pixel defect existing in a solid-state imaging device, and among video signals composed of a plurality of pixels input in time series,
Generating a first correction signal XL from the first video signal;
Generating a second correction signal YH from the second video signal;
Generating a correction coefficient Kd from at least one of the first and second video signals;
XL + YH × Kd
3. A defective pixel correction circuit, wherein the defect signal of the first video signal is replaced with a third correction signal obtained in (1). A first signal value obtained from the first video signal is Xav,
Yav is a second signal value obtained from the second video signal,
Kd = Xav / Yav
2. The defective pixel correction circuit according to claim 1, wherein the third correction signal is generated based on the correction coefficient Kd obtained in step (1). A first signal value obtained from the first video signal is Xav,
Yav is a second signal value obtained from the second video signal,
Kd = Xav−Yav
2. The defective pixel correction circuit according to claim 1, wherein the third correction signal is generated based on the correction coefficient Kd obtained in step (1). The values of the first video signal and the second video signal at an arbitrary time i are x (i) and y (i), respectively.
When x (i) is a defect signal, let t be a certain time width.
The first correction signal XL and the second correction signal YH are
XL = x (it), YH = y (i) -y (it)
The defective pixel correction circuit according to claim 1, wherein: The values of the first video signal and the second video signal at an arbitrary time i are x (i) and y (i), respectively.
When x (i) is a defect signal, let t be a certain time width.
The first correction signal XL and the second correction signal YH are
XL = x (i + t), YH = y (i) -y (i + t)
The defective pixel correction circuit according to claim 1, wherein: The values of the first video signal and the second video signal at an arbitrary time i are x (i) and y (i), respectively.
When x (i) is a defect signal, let t be a certain time width.
The first correction signal XL and the second correction signal YH are
XL = {x (it) + x (i + t)} / 2, YH = y (i)-{y (it) + y (i + t)} / 2
The defective pixel correction circuit according to claim 1, wherein: The values of the first video signal and the second video signal at an arbitrary time i are x (i) and y (i), respectively.
When x (i) is a defect signal, let t be a certain time width.
The first signal value Xav and the second signal value Yav are
Xav = x (it), Yav = y (it)
The defective pixel correction circuit according to claim 1, wherein: When the values of the first video signal and the second video signal at an arbitrary time i are x (i) and y (i), respectively, and x (i) is a defect signal, a certain time width is t As
The first signal value Xav and the second signal value Yav are
Xav = x (i + t), Yav = y (i + t)
The defective pixel correction circuit according to claim 1, wherein: The values of the first video signal and the second video signal at an arbitrary time i are x (i) and y (i), respectively.
When x (i) is a defect signal, let t be a certain time width.
The first signal value Xav and the second signal value Yav are
Xav = {x (it) + x (i + t)} / 2, Yav = {y (it) + y (i + t)} / 2
The defective pixel correction circuit according to claim 1, wherein: First computing means for generating a first correction signal from the first video signal;
Second computing means for generating a second correction signal from the second video signal;
Correction coefficient generating means for generating a correction coefficient from at least one of the first and second video signals;
Third computing means for generating a third correction signal from the first and second correction signals and the correction coefficient;
An output switching circuit for switching and outputting the first video signal and the third correction signal;
The third computing means is a multiplier for multiplying the second correction signal by a correction coefficient;
2. The defective pixel correction circuit according to claim 1, further comprising an adder for adding the output of the multiplier and a first correction signal. The second calculation means includes:
Generating a fourth correction signal in addition to the second correction signal;
The correction coefficient generation means includes
The defective pixel correction circuit according to claim 10, further comprising a divider that divides the first correction signal by a fourth correction signal. The second calculation means includes:
Generating a fourth correction signal in addition to the second correction signal;
The correction coefficient generation means includes
The defective pixel correction circuit according to claim 10, further comprising a subtracter that subtracts a fourth correction signal from the first correction signal. The correction coefficient generation means includes
Fourth arithmetic means for generating a first signal value from the first video signal;
Fifth arithmetic means for generating a second signal value from the second video signal;
And a sixth calculator that generates the correction coefficient from the first and second signal values. The sixth calculator includes a divider that divides the first signal value by the second signal value. The defective pixel correction circuit according to claim 10. The correction coefficient generation means includes
Fourth arithmetic means for generating a first signal value from the first video signal;
Fifth arithmetic means for generating a second signal value from the second video signal;
A sixth calculating means for generating the correction coefficient from the first and second signal values;
11. The defective pixel correction circuit according to claim 10, wherein the sixth arithmetic means comprises a subtracter that subtracts the second signal value from the first signal value.

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