JP3932842B2 - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon carbide semiconductor device including a J-FET and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, as a silicon carbide semiconductor device provided with a J-FET, there is one disclosed in Japanese Patent Laid-Open No. 2000-312008. FIG. 9 shows a cross-sectional configuration of the N-channel J-FET disclosed in this publication. As shown in FIG. 9, the N-channel J-FET is an N-channel made of silicon carbide. ⁺ N on mold substrate J1 ^- It is formed using the substrate on which the type drift layer J2 is grown. N ^- A P-type first gate region J3 is formed by ion implantation in the surface layer portion of the epitaxial layer J2, and penetrates through the first gate region J3. ^- A trench J4 reaching the type drift layer J2 is formed.
[0003]
The surface of the first gate region J3 including the inside of the trench J4 has N ^- The type channel layer J5 is epitaxially grown, and N in the trench J4 ^- A P-type second gate region J6 is formed on the surface of the type channel layer J5. N ^- Type ion channel layer J5 is ion-implanted into a portion not sandwiched between first and second gate regions J3 and J6. ⁺ A mold source region J7 is formed.
[0004]
The gate electrodes J8 and N electrically connected to the first and second gate regions J3 and J6 ⁺ A source electrode J9 electrically connected to the mold source region J7 is provided, and N ⁺ The drain electrode J10 is provided on the back surface side of the mold substrate J1, and the J-FET shown in FIG. 9 is configured.
[0005]
The J-FET having such a configuration controls the voltage applied to the gate electrode J8, so that N ^- By operating the extension amount of the depletion layer extending to the type channel layer J5 and forming the channel, an operation is performed so that a current flows between the source and the drain through the channel.
[0006]
[Problems to be solved by the invention]
However, in the J-FET disclosed in the above conventional publication, N ⁺ Since the type source region J7 is formed by ion implantation, crystal defects are easily formed. ⁺ This causes a decrease in breakdown voltage of a PN junction formed between the first gate region J3 of the mold and a leak.
[0007]
Also, a trench J4 formation process, a second gate region J6 patterning process, N ⁺ Since the photo process is used in the process of forming the mold source region J7 and the like, and the photo process is frequently used, there is a problem that miniaturization of the cell becomes difficult.
[0008]
An object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing the same that can prevent a decrease in breakdown voltage and occurrence of leakage between the source region and the gate region. Another object of the present invention is to provide a silicon carbide semiconductor device having a structure that can be easily miniaturized and a method for manufacturing the same.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, according to the first aspect of the present invention, a substrate (1) made of silicon carbide of the first conductivity type is formed on the substrate (1) and has a lower concentration than the substrate (1). A first conductivity type drift layer (2) made of silicon carbide, a second conductivity type first gate region (3) formed on the surface of the drift layer (2), and a first gate region (3) A first electric field relaxation region (4) of the first conductivity type formed on the surface and silicon carbide formed on the first electric field relaxation region (4) and having a higher concentration than the first electric field relaxation region (4). A first conductivity type source region (5), and a trench (6) penetrating the source region (5), the first electric field relaxation region (4) and the first gate region (3) and reaching the drift layer (2) A channel layer (7) of the first conductivity type made of silicon carbide formed on the inner wall side surface of the trench (6), In the wrench (6), a second gate region (8) formed on the surface of the channel layer (7), a first gate electrode (13) electrically connected to the first gate region (3), A second gate electrode (9) electrically connected to the second gate region (8), a source electrode (10) electrically connected to the source region (5), and a back surface side of the substrate (1) A J-FET having a formed drain electrode (12) is provided.
[0010]
As described above, the first electric field relaxation region having a low impurity concentration is provided between the source region where the PN junction is formed and the first gate region. For this reason, the electric field formed in the PN junction can be relaxed, and the breakdown voltage of the silicon carbide semiconductor device can be improved. According to the fifth aspect of the present invention, if the first electric field relaxation region is formed by epitaxial growth, it is possible to prevent a breakdown voltage drop and a leak from occurring between the source region and the gate region. Thereby, the breakdown voltage of the silicon carbide semiconductor device can be further improved.
[0011]
For example, as shown in claim 2, the second gate region (8) can be composed of silicon carbide of the second conductivity type configured with a concentration substantially equal to that of the first gate region. According to a third aspect of the present invention, the second gate region (8) can be composed of a second conductivity type compound semiconductor. When such a compound semiconductor is used, since the band gap is wider than that of silicon carbide, the parasitic diode does not turn on even if the second gate region is driven with a voltage larger than the theoretical value of the built-in potential of silicon carbide. Can be. For example, when AlN is used as the compound semiconductor, the driving voltage can be up to 3.4 V, which is higher than about 2.9 V, which is the theoretical limit of the built-in potential of silicon carbide. Thereby, the silicon carbide semiconductor device can be driven with better controllability.
[0012]
Furthermore, as shown in claim 4, the second gate region (8) can be formed of an insulator or a semi-insulator.
[0013]
In the invention described in claim 6, the first electric field relaxation region (4) and the source region become higher in concentration on the surface of the first gate region (3) as the distance from the first gate region (3) increases. The first conductive type semiconductor layer (40) is formed, the first electric field relaxation region (4) is formed by the low concentration portion of the semiconductor layer (40), and the source region (5) is formed by the high concentration portion. ) Is configured. With such a configuration, the source region and the first electric field relaxation region can also be configured.
[0014]
The invention according to claim 7 is characterized in that a portion of the drift layer (2) located in the lower layer of the trench (6) is provided with a second electric field relaxation region (60). When such a second electric field relaxation region is provided, electric field concentration occurring at the bottom of the trench, particularly at the corner, can be relaxed, and the breakdown voltage of the silicon carbide semiconductor device can be improved. In addition, as shown in claim 8, the second electric field relaxation region (60) is constituted by a second conductivity type semiconductor layer or an amorphous semiconductor layer.
[0015]
The invention according to claims 9 to 18 relates to a method for manufacturing a silicon carbide semiconductor device according to claims 1 to 8. By these methods, the silicon carbide semiconductor device shown in claims 1 to 8 can be manufactured.
[0016]
In the invention according to claim 12, in the step of forming the channel layer (7) and the step of forming the second gate region (8), the first conductive is formed in the trench (6) and on the surface of the source region (5). A step of epitaxially growing the mold layer (24), a step of epitaxially growing the second conductivity type layer (25) so as to embed the trench (6) on the first conductivity type layer (24), and a second conductivity type layer. (25) and the step of exposing the source region (5) by etching back the first conductivity type layer (24).
[0017]
As described above, if the channel layer and the second gate region are formed by etch back, the photo process is performed only when the trench is formed. Therefore, the number of photo steps can be reduced as compared with the conventional case, and a silicon carbide semiconductor device having a structure suitable for miniaturization can be obtained.
[0018]
In the invention described in claim 14, the second gate region (8) is constituted by an insulator layer (50) made of an insulator or a semi-insulator, and the same effect as that of claim 12 is obtained. In addition, since the insulator layer can be formed by spin coating or the like, the manufacturing process can be simplified more than when the second gate region is formed by epitaxial growth.
[0019]
In a seventeenth aspect of the present invention, the step of forming the trench (6) includes the step of forming the second electric field relaxation region (60) by performing ion implantation on the bottom surface of the trench (6). It is characterized by that. In this manner, the second electric field relaxation region can be formed by performing ion implantation on the bottom surface of the trench.
[0020]
In this case, as shown in claim 18, if the mask material used when etching the trench (6) is used as it is as an ion implantation mask, the mask can also be used, and the manufacturing process can be simplified. it can.
[0021]
In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 shows a cross-sectional configuration of a J-FET provided in the silicon carbide semiconductor device according to the first embodiment of the present invention. Hereinafter, the configuration of the J-FET will be described with reference to FIG.
[0023]
As shown in FIG. 1, for example, 1 × 10 ¹⁹ cm ^-3 N with high impurity concentration ⁺ A mold substrate 1 is used and this N ⁺ On the main surface of the mold substrate 1, for example, 1 × 10 ¹⁵ ~ 5x10 ¹⁶ cm ^-3 N with low impurity concentration ^- A type drift layer 2 is formed. N ^- P on the surface of the type drift layer 2 ⁺ A first gate region 3 made of a mold layer is epitaxially grown. The first gate region 3 is, for example, 5 × 10 ¹⁷ ~ 5x10 ¹⁹ cm ^-3 The impurity concentration is high.
[0024]
Furthermore, N 1 is formed on the surface of the first gate region 3. ^- The mold region 4 is epitaxially grown and N ^- On the surface of the mold region 4, for example, 1 × 10 ¹⁸ ~ 5x10 ¹⁹ cm ^-3 N with high impurity concentration ⁺ The type source region 5 is epitaxially grown. N ^- The mold region 4 is N ⁺ Type source region 5 and P ⁺ By being sandwiched between the first gate region 3 of the mold, electric field relaxation between high-concentration PN junctions is performed. Hereinafter, N ^- The mold region 4 is referred to as an electric field relaxation region (first electric field relaxation region). The thickness of the electric field relaxation region 4 is, for example, 0.5 μm or less, and the impurity concentration is N ⁺ Lower than the mold source region 5.
[0025]
N ⁺ N from the surface of the mold source region 5 ⁺ Penetrating through the source region 5, the electric field relaxation region 4 and the first gate region 3, N ^- A trench 6 reaching the mold drift region 2 is formed. N on the inner wall of the trench 6 ^- N having an impurity concentration almost equal to that of the type drift region 2 ^- The type channel layer 7 is epitaxially grown. ^- P having an impurity concentration almost equal to that of the first gate region 3 so as to bury the trench 6 in the surface of the type channel layer 7 ⁺ A second gate region 8 of the mold is epitaxially grown. These N ^- The surface of the type channel layer 7 and the second gate region 8 is N ⁺ It is flush with the surface of the mold source region 5.
[0026]
A second gate electrode 9 is electrically connected to the surface of the second gate region 8, and an interlayer insulating film 10 is formed so as to cover the second gate electrode 9. In addition, N is connected through a contact hole formed in the interlayer insulating film 10. ⁺ A source electrode 11 electrically connected to the mold source region 5 is formed. And N ⁺ A drain electrode 12 is formed on the back surface side of the mold substrate 1 to constitute the structure shown in FIG.
[0027]
1, the first gate region 3 is also electrically connected to the first gate electrode 13 so that the voltage applied to the first gate region 3 can be controlled via the first gate electrode 13. It has become.
[0028]
The J-FET configured in this way operates normally off. This operation differs depending on the connection mode of the first gate electrode 13 and the second gate electrode 9, and is performed as follows.
[0029]
(1) In the case where the potentials of the first and second gate electrodes 13 and 9 are controllable, the first and second gate regions 3 and 3 based on the potentials of the first and second gate electrodes 13 and 9 N from both sides of 8 ^- Double gate drive is performed to control the amount of extension of the depletion layer extending toward the mold channel layer 7 side. For example, when no voltage is applied to the first and second gate electrodes 13 and 9, N ^- The type channel layer 7 is pinched off by a depletion layer extending from both the first and second gate regions 3 and 8. Thereby, the source-drain current is turned off. The first and second gate regions 3 and 8 and N ^- When a forward bias is applied to the type channel layer 7, N ^- The extension amount of the depletion layer extending to the mold channel layer 7 is reduced. Thereby, a channel is set and a current flows between the source and the drain.
[0030]
(2) In the case where only the potential of the first gate electrode 13 can be controlled independently and the potential of the second gate electrode 9 is the same potential as the source electrode 11, for example, the potential of the first gate electrode 13 From the first gate region 3 side, N ^- Single gate drive is performed to control the amount of extension of the depletion layer extending to the type channel layer 7 side. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the first gate region 3 side.
[0031]
(3) In the case where only the potential of the second gate electrode 9 can be controlled independently and the potential of the first gate electrode 13 is the same potential as the source electrode 11, for example, the potential of the second gate electrode 9 N from the second gate region 8 side ^- Single gate drive is performed to control the amount of extension of the depletion layer extending to the type channel layer 7 side. In this case as well, basically the same operation as in the case of the double gate drive is performed, but the channel is set only by the depletion layer extending from the second gate region 8 side.
[0032]
Next, a method for manufacturing the silicon carbide semiconductor device shown in FIG. 1 will be described with reference to the manufacturing steps of the silicon carbide semiconductor device shown in FIGS.
[0033]
First, in the process shown in FIG. 2A, N made of 3C, 4H, 6H, or 15R-SiC having a thickness of about 400 μm cut out from the (0001) Si plane. ⁺ A mold substrate 1 is prepared. ⁺ N having a thickness of about 10 μm on the surface of the mold substrate 1 ^- Type drift layer 2, P having a thickness of about 1 μm ⁺ Mold layer 20, N having a thickness of about 0.5 μm ^- Mold layer 21 and N having a thickness of about 2 to 3 μm ⁺ The mold layer 22 is epitaxially grown in order.
[0034]
Next, in the step shown in FIG. ⁺ After the LTO film 23 serving as a mask material is formed on the surface of the mold layer 22, the LTO film 23 is patterned by photolithography, and a predetermined position of the LTO film 23 is opened. Then, etching using the LTO film 23 as a mask, for example, RIE (Reactive Ion Etching) is performed, and N ⁺ Mold layer 22, N ^- Mold layer 21 and P ⁺ N through the mold layer 20 ^- A trench 6 having a depth of about 4.5 to 5 μm reaching the type drift layer 2 is formed. At this time, it is desirable that the angle formed by the side wall surface with respect to the bottom surface of the trench 6 is about 60 to 90 ° C. As a result, the trench 6 ⁺ Mold layer 20, N ^- Mold layer 21 and N ⁺ The mold layer 22 is divided and P ⁺ The first gate region 3 is constituted by the mold layer 20 and N ^- The electric field relaxation region 4 is constituted by the mold layer 21 and N ⁺ N in mold layer 22 ⁺ A mold source region 5 is formed.
[0035]
Subsequently, after removing the LTO film 23 with hydrofluoric acid or the like, as a step shown in FIG. ⁺ N having a thickness of about 0.5 μm on the surface of the source region 5 ^- The mold layer 24 is epitaxially grown. In the step shown in FIG. ^- P on the surface of the mold layer 24 ⁺ The mold layer 25 is epitaxially grown and P ⁺ The trench 6 is filled with the mold layer 25.
[0036]
Next, in the process shown in FIG. 3B, P (Chemical Mechanical Polishing) is performed by CMP. ⁺ Mold layer 25 and N ^- The mold layer 24 is etched back and N ⁺ The mold source region 5 is exposed. As a result, P only in the trench 6 ⁺ Mold layer 25 and N ^- The mold layer 24 remains, and P ⁺ The mold layer 25 constitutes the second gate region 8 and N ^- N by mold layer 24 ^- A type channel layer 7 is formed.
[0037]
In the step shown in FIG. 3C, a metal film made of Al, Ti or the like that can make ohmic contact with the P-type semiconductor is disposed on the substrate surface, and then the metal film is patterned to form the second gate electrode 9. At the same time, the first gate electrode 13 is formed in a cross section different from that shown in FIG. Then, after forming the interlayer insulating film 10 on the substrate surface, a contact hole is opened in the interlayer insulating film 10. Further, a metal film made of Ni or the like that can make ohmic contact with the N-type semiconductor is disposed to form the source electrode 11. And N ⁺ After forming drain electrode 12 on the back side of mold substrate 1, a sintering process is performed to complete the silicon carbide semiconductor device including the J-FET shown in FIG. 1.
[0038]
As described above, in the silicon carbide semiconductor device shown in the present embodiment, N ⁺ The mold source region 5 is formed by epitaxial growth. For this reason, N ⁺ Crystal defects are unlikely to form in the source region 5, and P ⁺ The breakdown voltage of the PN junction formed between the first gate region 3 of the mold and the occurrence of leakage can be prevented, and the breakdown voltage of the silicon carbide semiconductor device can be prevented from decreasing.
[0039]
N where PN junction is formed ⁺ Type source region 5 and P ⁺ An electric field relaxation region 4 having a low impurity concentration is provided between the first gate region 3 of the mold. For this reason, the electric field formed in the PN junction can be relaxed, and the breakdown voltage of the silicon carbide semiconductor device can be further improved.
[0040]
In the present embodiment, the epitaxially grown first gate region 3, electric field relaxation region 4, and N ⁺ A trench 6 is provided so as to penetrate the mold source region 5. Then, N is formed in the trench 6 by epitaxial growth. ^- A type channel layer 7 is formed, and a second gate region 8 is formed thereon. For this reason, all dimensions are defined by the film thickness of each epitaxially grown layer and are determined in a self-aligning manner. For this reason, a silicon carbide semiconductor device having stable characteristics can be obtained.
[0041]
Further, in the present embodiment, except for the electrode forming process and the interlayer insulating film forming process, the photo process is performed only when the trench 6 is formed. Therefore, the number of photo steps can be reduced as compared with the conventional case, and a silicon carbide semiconductor device having a structure suitable for miniaturization can be obtained.
[0042]
(Second Embodiment)
In the present embodiment, the case where the silicon carbide semiconductor device shown in FIG. 1 of the first embodiment is formed by another manufacturing method will be described. In FIG. 4, the manufacturing process of the silicon carbide semiconductor device in this embodiment is shown. In addition, since the manufacturing method of this embodiment is substantially the same as that of 1st Embodiment, only the part different from 1st Embodiment is shown in FIG.
[0043]
First, in the step shown in FIG. 4A, as in FIG. 2A of the first embodiment, N ⁺ N on the main surface of the mold substrate 1 ^- Type drift layer 2, P ⁺ The mold layer 20 is epitaxially grown. Then P ⁺ On the mold layer 20, N ^- The mold layer 30 is epitaxially grown to a thickness of about 2 to 3 μm.
[0044]
Next, in the step shown in FIG. ^- N-type impurities (for example, nitrogen and phosphorus) are ion-implanted from the surface of the mold layer 30, and N ^- The upper layer portion of the mold layer 30 is increased in concentration, and N ⁺ A mold layer 31 is formed. At this time, N ⁺ The mold layer 31 is formed with a thickness of 1 to 1.5 μm, for example. Thereafter, the remaining N is performed by performing the steps after FIG. 2B shown in the first embodiment. ^- The electric field relaxation region 4 is formed by the mold layer 30 and N ⁺ N in mold layer 31 ⁺ Type source region 5 is formed, and the silicon carbide semiconductor device shown in FIG. 1 is completed.
[0045]
Thus, N ^- N formed by ion implantation into the mold layer 30 ⁺ N in mold layer 31 ⁺ It is also possible to form the mold source region 5. In this case, N ⁺ The type source region 5 is formed by ion implantation, and crystal defects can be formed. ⁺ N formed by epitaxial growth between the source region 5 and the first gate region 3 in which crystal defects are not easily formed. ^- Since the electric field relaxation region 4 composed of the mold layer 30 is provided, it is possible to prevent the breakdown voltage of the PN junction from decreasing and the occurrence of leakage, and the same effects as those of the first embodiment can be obtained.
[0046]
(Third embodiment)
In the present embodiment, the case where the silicon carbide semiconductor device shown in FIG. 1 of the first embodiment is formed by another manufacturing method will be described. In FIG. 5, the manufacturing process of the silicon carbide semiconductor device in this embodiment is shown. In addition, since the manufacturing method of this embodiment is substantially the same as that of 1st Embodiment, only a different part from 1st Embodiment is shown in FIG.
[0047]
First, in the step shown in FIG. 5, N is performed in the same manner as in FIG. 2A of the first embodiment. ⁺ N on the main surface of the mold substrate 1 ^- Type drift layer 2, P ⁺ The mold layer 20 is epitaxially grown. Then P ⁺ An N-type layer 40 is epitaxially grown on the mold layer 20 to a thickness of about 2 to 3 μm. At this time, by appropriately changing the atmosphere during the epitaxial growth, the N-type layer 40 becomes P ⁺ Gradation is such that the impurity concentration increases from the surface of the mold layer 20 in order, P ⁺ The portion in contact with the mold layer 20 is set to a low concentration.
[0048]
Thereafter, by performing the steps after FIG. 2B shown in the first embodiment, the electric field relaxation region 4 is formed in the low concentration portion located in the lower layer of the N-type layer 40. N in the high concentration part located in the upper layer ⁺ Type source region 5 is formed, and the silicon carbide semiconductor device shown in FIG. 1 is completed.
[0049]
As described above, the silicon carbide semiconductor device similar to that of the first embodiment can be formed even by using the N-type layer 40 having a gradation in the impurity concentration. Also in this case, since the N-type layer 40 is formed by epitaxial growth, the same effect as that of the first embodiment can be obtained.
[0050]
(Fourth embodiment)
In the silicon carbide semiconductor device of FIG. 1 shown in the first embodiment, the second gate region 8 can be formed of an insulator or a semi-insulator. In this case, the insulator or semi-insulator and N ^- The amount of extension of the depletion layer extending from the second gate region 8 is determined by the work function difference between the first channel region 7 and the depletion layer extending from the first and second gate regions 3, 8. ^- The inside of the type channel layer 7 is pinched off, and the extension amount of the depletion layer from the first gate region 3 is controlled based on the voltage applied to the first gate region 3, and the channel is controlled.
[0051]
As described above, the second gate region 8 can be formed of an insulator or a semi-insulator. Even with such a configuration, the same effect as in the first embodiment can be obtained.
[0052]
In FIG. 6, the manufacturing process of the silicon carbide semiconductor device of this embodiment is shown. Since the method for manufacturing the silicon carbide semiconductor device of the present embodiment is basically the same as that of the first embodiment, only different portions will be described.
[0053]
First, steps similar to those shown in FIGS. 2A to 2C shown in the first embodiment are performed, and N in trench 6 is formed. ^- The mold layer 24 is epitaxially grown. Thereafter, in the step shown in FIG. 6A, the P film formed in the step shown in FIG. ⁺ Instead of the mold layer 25, an insulator layer 50 is formed. At this time, the insulator layer 50 can be formed by epitaxial growth or spin coating. When formed by spin coating, P is used as in the first embodiment. ⁺ The manufacturing process can be simplified as compared with the case where the mold layer 25 is epitaxially grown.
[0054]
Subsequently, in the step shown in FIG. ^- The insulator layer 50 is planarized using the mold layer 24 as a stopper. Then, N by time control ^- The mold layer 24 is etched back and N ⁺ The mold source region 5 is exposed.
[0055]
In the step shown in FIG. 6C, a metal film made of Al, Ti, or the like that can make ohmic contact with the P-type semiconductor is disposed on the substrate surface, and then the metal film is patterned to obtain the structure shown in FIG. Forms a first gate electrode 13 in another cross section. After that, after forming the interlayer insulating film 10 on the substrate surface, a contact hole is opened in the interlayer insulating film 10 and a metal film made of Ni or the like that can make ohmic contact with the N-type semiconductor is disposed to form the source electrode 11. Thereafter, the silicon carbide semiconductor device according to the present embodiment is completed by performing a process for forming the drain electrode 12 and the like.
[0056]
Here, the case where the second gate region 8 of the first embodiment is formed of an insulator has been described, but it is of course possible to apply to the second and third embodiments.
[0057]
(Fifth embodiment)
In the structure shown in the first embodiment, the second gate region 8 is not silicon carbide but P ⁺ It can also be composed of a type compound semiconductor. As the compound semiconductor, for example, AlN, GaN, AlGaN, or the like can be used.
[0058]
Since such a compound semiconductor has a wider band gap than silicon carbide, even if the second gate region 8 is driven with a voltage larger than the theoretical value of the built-in potential of silicon carbide, the parasitic diode is not turned on. it can. For example, when AlN is used as the compound semiconductor, the driving voltage can be up to 3.4 V, which is higher than about 2.9 V, which is the theoretical limit of the built-in potential of silicon carbide. Thereby, the silicon carbide semiconductor device can be driven with better controllability.
[0059]
In addition, the manufacturing method of the silicon carbide semiconductor device in this embodiment only needs to change the material of the 2nd gate area | region 8 with respect to 1st Embodiment, and the manufacturing process shown in FIG. 2, FIG. 3 is applied as it is. .
[0060]
(Sixth embodiment)
In FIG. 7, the cross-sectional structure of the silicon carbide semiconductor device provided with J-FET in 6th Embodiment of this invention is shown. In the present embodiment, an electric field relaxation region (second electric field relaxation region) 60 is provided in the lower layer portion of the bottom surface of the trench 6 with respect to the silicon carbide semiconductor device shown in the first embodiment. About another structure, it is the same as that of 1st Embodiment.
[0061]
The electric field relaxation region 60 shown here is made of, for example, P-type silicon carbide or amorphous silicon carbide. When such electric field relaxation region 60 is provided, electric field concentration occurring at the bottom surface of trench 6, particularly at the corner portion, can be relaxed, and the breakdown voltage of the silicon carbide semiconductor device can be improved.
[0062]
FIG. 8 shows a manufacturing process of the silicon carbide semiconductor device of this embodiment. Since the method for manufacturing the silicon carbide semiconductor device of the present embodiment is basically the same as that of the first embodiment, only different portions will be described.
[0063]
First, the steps shown in FIGS. 2A and 2B shown in the first embodiment are performed to form the trench 6. Thereafter, in the step shown in FIG. 8, ion implantation is performed using the LTO film 23 used for forming the trench 6 as it is as a mask. At this time, a P-type impurity (for example, B or Al) may be implanted, or the implanted region is made amorphous by implanting an inert ion (for example, C, Ar, or Ne) to silicon carbide. You may make it let it. Thereby, the electric field relaxation layer 60 is formed in the lower layer portion at the bottom of the trench 6. Thereafter, the steps shown in FIGS. 2C and 3A to 3C shown in the first embodiment are performed, and the silicon carbide semiconductor device of this embodiment shown in FIG. 7 is completed.
[0064]
In FIG. 7, the electric field relaxation region 60 is shown so as to be in contact with the bottom surface of the trench 6, but may be in contact, or may be formed with a gap between the bottom surface of the trench 6.
[0065]
(Other embodiments)
In each of the above embodiments, N ^- Although the silicon carbide semiconductor device provided with the N-channel J-FET in which the channel layer 7 becomes the channel has been described, the P-channel J-FET in which the conductivity type of each component of the silicon carbide semiconductor device is inverted is described. The present invention can also be applied to the provided silicon carbide semiconductor device.
[0066]
In the above embodiment, a normally-off type J-FET has been described as an example. However, the present invention is not limited to a normally-off type J-FET, and is also applicable to a normally-on type J-FET. In this case, for example, N ^- The impurity concentration of the type channel layer 7 is 5 × 10 ¹⁶ ~ 1x10 ¹⁷ cm ^-3 It can also be a degree.
[Brief description of the drawings]
1 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device according to a first embodiment of the present invention.
2 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 1. FIG.
FIG. 3 is a diagram showing a manufacturing step of the silicon carbide semiconductor device continued from FIG. 2;
FIG. 4 is a diagram showing a manufacturing process of the silicon carbide semiconductor device in the second embodiment of the present invention.
FIG. 5 is a diagram showing a manufacturing process of a silicon carbide semiconductor device in a third embodiment of the present invention.
FIG. 6 is a diagram showing a manufacturing process of a silicon carbide semiconductor device in a fourth embodiment of the present invention.
FIG. 7 is a diagram showing a cross-sectional configuration of a silicon carbide semiconductor device in a sixth embodiment of the present invention.
8 is a diagram showing a manufacturing process of the silicon carbide semiconductor device shown in FIG. 7. FIG.
FIG. 9 is a diagram showing a cross-sectional configuration of a conventional silicon carbide semiconductor device.
[Explanation of symbols]
1 ... N ⁺ Mold substrate, 2 ... N ^- Type drift layer, 3 ... first gate region, 4 ... electric field relaxation region, 5 ... N ⁺ Type source region, 6 ... trench, 7 ... N ^- Type channel layer, 8 ... second gate region, 9 ... second gate electrode, 11 ... source electrode, 12 ... drain electrode, 13 ... first gate electrode.

Claims (18)

A substrate (1) made of silicon carbide of the first conductivity type;
A first conductivity type drift layer (2) made of silicon carbide formed on the substrate (1) and having a lower concentration than the substrate (1);
A first conductivity type first gate region (3) formed on the surface of the drift layer (2);
A first conductivity type first electric field relaxation region (4) formed on a surface of the first gate region (3);
A first conductivity type source region (5) formed on the first electric field relaxation region (4) and made of silicon carbide having a higher concentration than the first electric field relaxation region (4);
A trench (6) penetrating the source region (5), the first electric field relaxation region (4) and the first gate region (3) and reaching the drift layer (2);
A channel layer (7) of the first conductivity type made of silicon carbide formed on the inner wall side surface of the trench (6);
A second gate region (8) formed on the surface of the channel layer (7) in the trench (6);
A first gate electrode (13) electrically connected to the first gate region (3);
A second gate electrode (9) electrically connected to the second gate region (8);
A source electrode (10) electrically connected to the source region (5);
A silicon carbide semiconductor device comprising a J-FET having a drain electrode (12) formed on the back side of the substrate (1). 2. The silicon carbide semiconductor according to claim 1, wherein the second gate region is formed of silicon carbide of a second conductivity type having a concentration substantially equal to that of the first gate region. apparatus. 2. The silicon carbide semiconductor device according to claim 1, wherein the second gate region is made of a compound semiconductor of a second conductivity type. A substrate (1) made of silicon carbide of the first conductivity type;
A first conductivity type drift layer (2) made of silicon carbide formed on the substrate (1) and having a lower concentration than the substrate (1);
A first conductivity type first gate region (3) formed on the surface of the drift layer (2);
A first conductivity type first electric field relaxation region (4) formed on a surface of the first gate region (3);
A first conductivity type source region (5) formed on the first electric field relaxation region (4) and made of silicon carbide having a higher concentration than the first electric field relaxation region (4);
A trench (6) penetrating the source region (5), the first electric field relaxation region (4) and the first gate region (3) and reaching the drift layer (2);
A channel layer (7) of the first conductivity type made of silicon carbide formed on the inner wall side surface of the trench (6);
A second gate region (8) made of an insulator or a semi-insulator formed on the surface of the channel layer (7) in the trench (6);
A first gate electrode (13) electrically connected to the first gate region (3);
A source electrode (10) electrically connected to the source region (5);
A silicon carbide semiconductor device comprising a J-FET having a drain electrode (12) formed on the back side of the substrate (1). The silicon carbide semiconductor device according to any one of claims 1 to 4, wherein the first electric field relaxation region (4) is formed by epitaxial growth. The first electric field relaxation region (4) and the source region are formed on the surface of the first gate region (3) so as to increase in concentration with increasing distance from the first gate region (3). The first electric field relaxation region (4) is constituted by the low concentration portion of the semiconductor layer (40), and the source region (5) is constituted by the high concentration portion. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a silicon carbide semiconductor device. The part located in the lower layer part of the said trench (6) among the said drift layers (2) is equipped with the 2nd electric field relaxation area | region (60), The any one of Claim 1 thru | or 6 characterized by the above-mentioned. The silicon carbide semiconductor device described in 1. The silicon carbide semiconductor device according to claim 7, wherein the second electric field relaxation region (60) is configured by a semiconductor layer of a second conductivity type or an amorphous semiconductor layer. Preparing a substrate (1) made of silicon carbide of the first conductivity type;
Forming a first conductivity type drift layer (2) made of silicon carbide having a lower concentration than the substrate (1) on the substrate (1);
Forming a first conductivity type first gate region (3) on the surface of the drift layer (2);
Forming a first conductivity type first electric field relaxation region (4) made of silicon carbide on the surface of the first gate region (3) by epitaxial growth;
Forming a first conductivity type source region (5) made of silicon carbide at a higher concentration than the first electric field relaxation region (4) on the first electric field relaxation region (4);
Forming a trench (6) penetrating the source region (5), the first electric field relaxation region (4) and the first gate region (3) and reaching the drift layer (2);
Forming a first conductivity type channel layer (7) made of silicon carbide on the inner wall side surface of the trench (6);
Forming a second gate region (8) on the surface of the channel layer (7) in the trench (6);
Forming a first gate electrode (13) electrically connected to the first gate region (3);
Forming a second gate electrode (9) electrically connected to the second gate region (8);
Forming a source electrode (10) electrically connected to the source region (5);
Forming a drain electrode (12) on the back side of the substrate (1). A method for manufacturing a silicon carbide semiconductor device, comprising: 10. The silicon carbide according to claim 9, wherein, in the step of forming the second gate region (8), the second gate region is formed of silicon carbide having a concentration substantially equal to that of the first gate region. A method for manufacturing a semiconductor device. The method for manufacturing a silicon carbide semiconductor device according to claim 9, wherein in the step of forming the second gate region (8), the second gate region is formed of a compound semiconductor. In the step of forming the channel layer (7) and the step of forming the second gate region (8),
Epitaxially growing a first conductivity type layer (24) in the trench (6) and on the surface of the source region (5);
Epitaxially growing a second conductivity type layer (25) on the first conductivity type layer (24) so as to bury the trench (6);
10. The step of exposing the source region (5) by etching back the second conductivity type layer (25) and the first conductivity type layer (24). The manufacturing method of the silicon carbide semiconductor device as described in any one of thru | or 11. Preparing a substrate (1) made of silicon carbide of the first conductivity type;
Forming a first conductivity type drift layer (2) made of silicon carbide having a lower concentration than the substrate (1) on the substrate (1);
Forming a first conductivity type first gate region (3) on the surface of the drift layer (2);
Forming a first conductivity type first electric field relaxation region (4) made of silicon carbide on the surface of the first gate region (3) by epitaxial growth;
Forming a first conductivity type source region (5) made of silicon carbide at a higher concentration than the first electric field relaxation region (4) on the first electric field relaxation region (4);
Forming a trench (6) penetrating the source region (5), the first electric field relaxation region (4) and the first gate region (3) and reaching the drift layer (2);
Forming a first conductivity type channel layer (7) made of silicon carbide on the inner wall side surface of the trench (6);
Forming a second gate region (8) made of an insulator on the surface of the channel layer (7) in the trench (6);
Forming a first gate electrode (13) electrically connected to the first gate region (3);
Forming a source electrode (10) electrically connected to the source region (5);
Forming a drain electrode (12) on the back side of the substrate (1). A method for manufacturing a silicon carbide semiconductor device, comprising: In the step of forming the channel layer (7) and the step of forming the second gate region (8),
Epitaxially growing a first conductivity type layer (24) in the trench (6) and on the surface of the source region (5);
Forming an insulator layer (50) made of an insulator or a semi-insulator on the first conductivity type layer (24) so as to embed the trench (6);
The step of exposing the source region (5) by planarizing the insulator layer (50) and the first conductivity type layer (24) is provided. The manufacturing method of the silicon carbide semiconductor device as described in any one of these. In the step of forming the first electric field relaxation region (4) and the step of forming the source region (5),
Epitaxially growing a first conductivity type semiconductor layer (30) having a concentration equivalent to that of the first electric field relaxation region (4) on the surface of the first gate region (3);
By ion-implanting the first conductivity type impurity into the upper layer portion of the semiconductor layer (30), the upper layer portion of the semiconductor layer (30) is made high concentration, and the concentration of the semiconductor layer (30) is made high. The silicon carbide semiconductor according to any one of claims 9 to 14, wherein the source region (5) is constituted by a portion, and the first electric field relaxation layer (4) is constituted by a low concentration portion. Device manufacturing method. In the step of forming the first electric field relaxation region (4) and the step of forming the source region (5),
A first conductivity type semiconductor layer (40) is formed on the surface of the first gate region (3) so as to increase in concentration as the distance from the first gate region (3) increases. 15. The first electric field relaxation region (4) is constituted by a low concentration portion, and the source region (5) is constituted by a high concentration portion, according to any one of claims 9 to 14. A method for manufacturing a silicon carbide semiconductor device. The step of forming the trench (6) includes:
17. The method according to claim 9, further comprising a step of forming a second electric field relaxation region (60) by performing ion implantation on a bottom surface of the trench (6). A method for manufacturing a silicon carbide semiconductor device. In the step of forming the trench (6),
A mask material (23) is disposed on the surface of the source region (5), and the trench is formed by etching the source region (5), the first electric field relaxation region (4), and the first gate region (3). (6) is formed,
In the step of forming the second electric field relaxation region (60), the second electric field relaxation region (60) is formed by performing ion implantation using the mask material used for forming the trench (6) as a mask. The method for manufacturing a silicon carbide semiconductor device according to claim 17, wherein the silicon carbide semiconductor device is formed.

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