JP3927037B2 - Clock generation method and clock generation apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock generation method and a clock generation device, and more particularly, a clock generation device (communication device) that generates a clock for an interface in a communication device from an external basic clock input supplied from another device in a station building. About.
[0002]
In a DSLAM (line multiplexing apparatus) which is an xDSL (line standard; for example, ADSL) transmission apparatus, a clock to be supplied to the xDSL interface is extracted from a basic clock in a housing station. This clock is required to have very high precision (with little jitter). On the other hand, anti-tooth and noise countermeasures are required for the external basic clock supplied at the station.
[0003]
Conventionally, tank circuits and PLL circuits have been used to prevent tooth loss and noise, but the tank circuit can take measures against tooth loss, but it must take a mounting area and cannot be a noise countermeasure. However, the PLL circuit can supply the clock at the time of missing teeth, but has a problem that the above requirement cannot be satisfied because the jitter is large and it is not suitable for clock supply. Therefore, there is a need for a clock generator that satisfies the above requirements.
[0004]
[Prior art]
In the conventional technology, measures against missing teeth of the input clock (hereinafter abbreviated as CLK) (the number of protection stages. For example, reproducing one missing tooth is called one-stage protection. Regenerating missing teeth of two clocks. By using a tank circuit as a two-stage protection), it is possible to take measures against missing teeth. However, when noise is superimposed on the input CLK, the noise amount is directly input to the CLK generation unit via the tank circuit in the tank circuit, so that the CLK generation timing becomes abnormal and a malfunction occurs. For this reason, noise superposition cannot be avoided only by the tank circuit.
[0005]
FIG. 17 is a block diagram showing a configuration example of a conventional apparatus. The basic clock (bipolar signal) output from the basic clock supply device 1 enters the communication device 2. In the communication device 2, the CLK extraction unit 3 first extracts a clock. This extracted clock enters the tank circuit 10a and outputs CLK. This tank circuit is for preventing missing of CLK.
[0006]
On the other hand, the CLK monitoring unit 4 receives the output of the CLK extraction unit 3 and monitors the input CLK. The CLK monitoring unit 4 outputs input CLK information. The CLK information is given to the CLK state monitoring unit 9. The output of the CLK frequency dividing unit 8 is given to the line unit 11.
[0007]
In the device configured as described above, the basic CLK sent from the basic CLK supply device 1 is extracted by the CLK extraction unit 3 and then supplied to the CLK frequency dividing unit 8 through the tank circuit 10a. The extracted CLK is prevented from missing by the tank circuit 10 a and enters the CLK frequency divider 8. The CLK state monitoring unit 9 outputs the clock state to the outside as clock information as necessary. The output of the CLK frequency dividing unit 8 is given to the line unit 11, and the line unit 11 receives a predetermined CLK and performs a circuit operation.
[0008]
FIG. 18 is a diagram showing another configuration example of the conventional apparatus. The same components as those in FIG. 17 are denoted by the same reference numerals. In the figure, the basic CLK generated from the basic CLK supply device 1 is generated and enters the communication device 2. In the communication device 2, the CLK extraction unit 3 extracts CLK and enters the CLK monitoring unit 4 and the DPLL (digital PLL) unit 5. The input CLK signal output of the CLK monitoring unit 4 and the synchronization information of the DPLL unit 5 are given to the CLK state monitoring unit 9.
[0009]
On the other hand, the DPLL unit 5 receives the basic CLK and generates a free-running CLK. This free-running CLK is given to the CLK frequency divider 8. In this device, a free-running clock is supplied to the CLK frequency divider 8 instead of the original basic CLK. Accordingly, missing teeth can be prevented. The CLK output frequency-divided by the CLK frequency dividing unit 8 is given to the line unit 11, and the line unit 11 receives a predetermined CLK and performs a circuit operation.
[0010]
[Problems to be solved by the invention]
By using a PLL and generating a free-running CLK synchronized with the input CLK and not supplying the input CLK directly to the CLK generator, it is possible to prevent tooth loss and prevent malfunctions when noise is superimposed. Since it has a jitter of at least nsec, it cannot be used as a CLK to be provided to an interface (such as an xDSL interface) that requires a high precision CLK. In addition, there is a problem that a PLL with low jitter is very expensive.
[0011]
The present invention has been made in view of such a problem, and an object of the present invention is to provide a clock generation method and a clock generation apparatus capable of generating a highly accurate clock.
[0012]
[Means for Solving the Problems]
(1) FIG. 1 is a principle block diagram of the present invention. 17 and 18 are denoted by the same reference numerals. In the figure, 1 is a basic CLK supply device, and 2 is a communication device that receives the output of the basic CLK supply device 1. The communication device 2 includes a CLK generation unit 10 and a line unit 11. In the CLK generation unit 10, 3 is a CLK extraction unit that receives CLK from the basic CLK supply device 1 and extracts CLK, and 4 is a CLK monitoring unit that monitors CLK of the CLK extraction unit 3.
[0013]
5 is a DPLL (digital PLL) unit that receives the CLK component that is the output of the CLK extraction unit 3 and generates a free-running CLK, and 6 is a noise removal unit that receives the CLK component that is the output of the CLK extraction unit 3 and removes noise. , 7 is a CLK selection unit that selects a CLK by receiving various signals of the DPLL 5 and the extracted CLK that is the output of the noise removal unit 6, and 8 is a CLK frequency division unit that divides the frequency by receiving the output of the CLK selection unit 7. is there. 9 is a CLK state monitoring unit that receives the outputs of the CLK monitoring unit 4 and the DPLL unit 5 and monitors the CLK state, and 11 is a line unit that receives the CLK from the CLK frequency dividing unit 8.
[0014]
The basic CLK output from the basic CLK supply device 1 enters the CLK extraction unit 3 and extracts CLK components (P-side clock and N-side clock). The extracted CLK component is checked by the CLK monitoring unit 4 for the CLK signal rule (conditions that the clock must have). The CLK component extracted by the CLK extraction unit 3 creates a free-running CLK synchronized with the input CLK by the DPLL unit 5. The DPLL unit 5 outputs a signal indicating the position where the next CLK comes, and the noise removing unit 6 removes signals other than the CLK component from the CLK component.
[0015]
Based on information from the CLK monitoring unit and the DPLL unit 5, the CLK selection unit 7 switches the CLK component via the noise removal unit 6 and the CLK component created by the DPLL unit and provides them to the CLK frequency dividing unit 8. The CLK divider 8 divides the CLK output from the CLK selector 7 based on the information from the CLK monitor 4 to generate an output CLK.
[0016]
With this configuration, as long as there is a CLK component, it generates a highly accurate CLK that does not rely on the PLL, and has a protection function by preventing frequency division of the input CLK by continuing the frequency division by the CLK by the DPLL unit 5. By removing noise from the CLK component, it is possible to prevent malfunction due to noise superimposed on the input CLK, and by monitoring the signal law of the input CLK, it is possible to detect missing input signals and to generate a highly accurate clock. A clock generation method and a clock generation apparatus that can be generated can be provided.
[0017]
In the case of the conventional device, only accuracy or anti-tooth measures are taken, and therefore, when noise is superimposed on the basic CLK in the station, a malfunction is caused. In the worst case, all the interfaces using the CLK extracted from the basic CLK become unusable, which becomes a big problem in a communication apparatus that accommodates multiple lines such as DSLAM. By applying the present invention, it becomes possible to enhance the tolerance to noise superposition of the basic CLK in the station while maintaining accuracy, and there is a concern in the device configuration that becomes complicated with the diversification of access devices. It is possible to cope with noise in the office building and contribute to the stabilization of the access line.
[0018]
(2) FIG. 2 is a diagram for explaining the principle of the first operation of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 1 is a basic CLK supply device, 2 is a communication device, 3 is a CLK extraction unit that receives a basic CLK from the basic CLK supply device 1 and extracts CLK, and 6 is a noise that receives an output of the CLK extraction unit 3. 7 is a CLK selecting unit that receives the output of the noise removing unit 6 and selects CLK, 8 is a CLK dividing unit that receives the output of the CLK selecting unit 7 and divides CLK, 11 Is a line unit that receives CLK from the CLK frequency dividing unit 8.
[0019]
When the CLK is normally supplied from the basic CLK supply device 1 and there is no problem in the CLK extraction unit 3, the CLK extraction unit 3 extracts the CLK component, and the noise removal unit 6 generates the extracted CLK, and the CLK selection unit 7 Is supplied to the CLK frequency divider 8. The extracted CLK input to the CLK frequency divider 8 is a CLK with less jitter because it does not go through a PLL or the like. Since the CLK frequency divider 8 performs frequency division based on the extracted CLK, the jitter component of the output CLK is also small.
[0020]
With this configuration, by using the input CLK edge as it is and generating a CLK with less jitter, it is possible to realize a CLK applicable to an interface including xDSL without using an expensive PLL. This contributes to cost reduction of the device.
[0021]
(3) FIG. 3 is a diagram for explaining the principle of the second operation of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 5 is a DPLL section. In the DPLL unit 5, 21 is a CLK creation unit that receives a CLK component and creates a CLK, 22 is a violation check unit that receives the CLK component, 23 is a DPLL function unit that receives the output of the CLK creation unit 21, and 24 is The tooth missing monitoring unit receives the high-speed CLK and the output of the CLK creating unit 21. Reference numeral 6 denotes a noise removing unit that receives a CLK component and removes noise. Reference numeral 7 denotes a CLK selecting unit that receives outputs from the noise removing unit 6, the violation check unit 22, the DPLL unit 23, and the missing tooth monitoring unit 24. The CLK selector 7 is provided with a changeover switch for switching the connection between the case where there is no tooth loss and the case where there is a tooth loss.
[0022]
The DPLL unit 5 creates a CLK by the CLK creation unit 21 based on the CLK component extracted from the CLK extraction unit 3 in FIG. 1 and applies the DPLL by the DPLL function unit 23. Thereby, the position of the CLK edge of the input signal is predicted. This is realized by counting the interval of the input CLK component with the high-speed CLK input to the DPLL function unit 23 and the missing tooth monitoring unit 24. The DPLL unit 5 generates a free-running CLK. This free-running CLK is given to the noise removing unit 6 and the CLK selecting unit 7.
[0023]
If there is no edge before and after the predicted position of the input CLK edge, the tooth missing monitoring unit 24 determines that tooth missing has occurred in the input CLK signal and outputs a tooth missing monitoring signal. The missing tooth monitoring signal enters the CLK selector 7. Based on the missing tooth monitoring signal, the CLK selection unit 7 supplies the extracted CLK when there is no missing tooth of the input CLK, and supplies the free-running CLK when there is missing tooth to the CLK frequency dividing unit 8 (see FIG. 1). Therefore, it is possible to generate the output CLK by dividing by CLK with little jitter, and by switching to the free-running CLK and supplying it to the CLK dividing unit 8 at the time of missing teeth, the dividing is advanced, Enable protection.
[0024]
If comprised in this way, DPLL will be applied using an input CLK edge, self-running CLK will be generated, and it will switch to free-running CLK side only at the time of a missing tooth, and input CLK will become a missing tooth state, suppressing jitter. In addition, the influence on the CLK generation unit in the subsequent stage can be minimized during the number of protection stages, which can contribute to switching of the input CLK and enhancement of noise resistance.
[0025]
(4) FIG. 4 is a diagram for explaining the principle of the third operation of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 6 is a noise removal unit. In the noise removing unit 6, 31 is a CLK generating unit that receives the CLK component and generates CLK, 32 is a noise masking unit that receives the extracted CLK generated by the CLK generating unit 31 and masks the noise component, and 33 is from the DPLL 5. This is a mask signal generation unit that generates a mask signal in response to the self-running CLK. The output of the mask signal generator 33 is given to the noise mask unit 32.
[0026]
The DPLL unit 5 of FIG. 1 applies DPLL based on the CLK component extracted from the CLK extraction unit 3. Thereby, the mask signal generation unit 33 predicts the position of the CLK edge of the input signal. This is realized by counting the interval of the input CLK component with the high-speed CLK input to the DPLL unit 5.
[0027]
The noise masking unit 32 masks the input CLK component before and after the predicted position of the input CLK edge, so that even if noise is superimposed on the basic CLK from the basic CLK supply device 1 in FIG. Since the mask is masked, an erroneous CLK edge due to noise does not enter the CLK frequency divider 8 via the CLK selector 7 in FIG. 1, so that disturbance of the output CLK due to a malfunction can be prevented.
[0028]
With this configuration, the CLK position synchronized with the input CLK edge is generated by the DPLL unit 5 from the input CLK signal, so that the edge position is predicted in advance, and signals other than the CLK component are masked to the subsequent CLK generation unit. By supplying, the noise component of the input CLK is removed, and the malfunction of the subsequent CLK generation unit is eliminated, thereby contributing to the enhancement of noise resistance.
[0029]
(5) FIG. 5 is a diagram for explaining the principle of the fourth operation of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 4 is a CLK monitoring unit. In the CLK monitoring unit 4, reference numeral 41 denotes a counter clear pulse generating unit that inputs a CLK component to generate a counter clear pulse, and 42 is a CLK counter unit that receives the output of the counter clear pulse generating unit 41 in a crossed manner. There are two counter clear pulse generators 41 and CLK counters 42, # 1 and # 2.
[0030]
The basic CLK supplied from the basic CLK supply device 1 in FIG. 1 can superimpose a different CLK component on the basic CLK component according to a signal rule. The CLK monitoring unit 4 compares the CLK component extracted by the CLK extraction unit 3 in FIG. For example, when the basic CLK is supplied by the AMI code (bipolar signal as shown in FIG. 7), the P-side signal and the N-side signal come alternately.
[0031]
The counter clear pulse generator 41 generates a rising pulse by sampling the CLK component at high speed. Then, the CLK counter unit 42 counts the N-side continuity count and the P-side continuity count to check the continuity of the CLK. By monitoring whether the N-side CLK edge comes after receiving the P-side CLK edge or whether the N-side CLK edge comes after receiving the N-side CLK edge, it does not conform to a signal rule such as continuity of the same polarity only The state is detected, and it is possible to determine that a failure has occurred in the basic CLK input. For example, when the P-side clock is lost, the clock counter unit 42 of # 1 does not overflow, but the clock counter unit 42 of # 2 overflows by counting the N-side clock. As a result, a missing clock on the P side is detected.
[0032]
With this configuration, by monitoring the signal law of the input CLK signal, it is possible to detect the problem of the input CLK signal at an early stage and to isolate the fault information inside and outside the apparatus.
[0033]
(6) FIG. 6 is a diagram for explaining the principle of the fifth operation of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, 1 is a basic CLK supply device and 3 is a CLK extraction unit. In the CLK extraction unit 3, 51 is a comparator unit that receives a reference CLK and compares it with a reference voltage, 52 is a CLK phase comparison unit that receives the extracted CLK from the comparator unit 51 and compares the phase of CLK, and 53 is a comparator unit 51. A CLK generation unit 54 generates CLK by receiving the extracted CLK, and 54 is an integration circuit that receives the output of the CLK phase comparison unit 52. The output of the integration circuit 54 is given to the comparator unit 51. Then, a CLK component is output from the CLK creation unit 53.
[0034]
The basic CLK supply device 1 is connected to the communication device 2 in FIG. 1 by a cable or the like, but a jitter component may be generated when the CLK waveform is extracted due to the characteristics and distance of the cable and the circuit characteristics of the CLK extraction unit 3. There is.
[0035]
FIG. 7 is an explanatory diagram of jitter generation. (A) is a basic CLK, (b) is a P-side waveform, and (c) is an N-side waveform. The basic clock is separated into a P-side waveform and an N-side waveform using a reference voltage as shown in the figure, but the comparison reference level slightly changes depending on the characteristics of the comparator to be compared with the reference voltage. As a result, a difference in the width of the other edge from one edge of the CLK component occurs as a jitter component. Ideally, the period T1 and the period T2 shown in the figure coincide with each other, but T1 and T2 do not necessarily coincide with each other due to jitter.
[0036]
In the CLK extraction unit 3, the comparator unit 51 separates the P side CLK and the N side CLK. The CLK phase comparison unit 52 samples the input CLK component with the high-speed CLK, and measures the phase difference between the polarities of the CLK component. This phase difference is converted into a voltage by the integrating circuit 54 and fed back to the reference voltage of the comparator unit 51, so that the comparator operates in a direction in which jitter is reduced. Therefore, the phase difference between the polarities can be eliminated.
[0037]
With this configuration, by detecting and correcting the occurrence of jitter due to level fluctuations due to the path of the input CLK signal and component variations of the communication device, by supplying CLK with less jitter to the subsequent CLK generation unit, xDSL This contributes to satisfying an interface condition that requires a high-accuracy CLK.
[0038]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 8 is a block diagram showing an embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals. In the figure, reference numeral 1 denotes a DCS used in NTT as a basic CLK supply device. The DCS1 generates bipolar clocks including 64 kHz, 8 kHz and 400 Hz. Reference numeral 2 denotes a communication device 2 connected to the DCS 1. The internal configuration of the communication device 2 is the same as that shown in FIG. The output of the CLK divider 8 enters the subsequent xDSL line card 12a, PRI line card 12b, ISDN line card 12c, line card 12d, etc., and these circuits perform predetermined operations in response to clocks of 8 kHz and 400 Hz.
[0039]
The basic CLK signal transmitted from the DCS 1 is superposed with a 64 kHz / 8 kHz / 400 Hz CLK component, and is transmitted in the pattern shown in FIG. This basic CLK signal is vibrated every 125 μs to separate 8 kHz, and one of the 20 counts of 8 kHz is not vibrated (non-violation: nV). 5 ms (400 Hz) CLK is extracted. A bipolar signal is compared with a reference voltage to generate a P-side signal and an N-side signal, and a 64-kHz CLK is generated by taking the OR of these signals.
[0040]
The CLK extraction unit 3 includes a transformer and a comparator in order to extract a CLK component from the basic CLK signal waveform. FIG. 10 is a diagram illustrating a configuration example of the CLK extraction unit. The output waveform of DCS1 is a bipolar signal as shown in the figure. This signal is input to the CLK extraction unit 3 via the transformer T.
[0041]
Signals generated at both ends of the transformer T enter the comparators C1 and C2. The other inputs of the comparators C1 and C2 are connected to a reference voltage. The comparators C1 and C2 compare the input bipolar signal with the reference voltage, and generate a P-side signal and an N-side signal. The P-side signal and the N-side signal have a phase difference of 180 ° as shown in the figure. The CLK component separated into the P-side signal and the N-side signal is sent to the CLK monitoring unit 4, the DPLL unit 5, and the noise removal unit 6.
[0042]
The CLK monitoring unit 4 includes a signal rule check unit that receives a P-side signal and an N-side signal and checks a signal rule, and a level control unit that adjusts the balance between signals in the CLK component. In the signal pattern of DCS1, there is no possibility of continuous pulses with the same polarity other than during biolation. Therefore, continuous reception of the same polarity of P / N or simultaneous reception of P / N is an error of DCS1 or between DCS1 and communication device 2. Signal error and an abnormality of the CLK extraction unit 3 of the communication device 2. By monitoring the regularity of this P / N, it becomes possible to know the state of the DCS input.
[0043]
Further, the interval between P-N and the interval between N-P are sampled at a high-speed CLK (for example, several tens of MHz), the difference between the two intervals is converted into a voltage by an integration circuit, and the comparator C1 of the CLK extraction unit 3 By applying feedback to the reference voltage of C2, it is possible to suppress the jitter of the CLK component (see FIG. 6 and its description).
[0044]
The DPLL unit 5 receives the CLK component, generates a self-running 64 kHz CLK (64 KCLK), and monitors the violation. The DPLL unit 5 includes an input 64K generation unit, a self-running 64K generation unit, and a violation monitoring unit. FIG. 11 is a diagram illustrating a configuration example of the DPLL unit. In the figure, 61 is an input 64K generating unit that receives the CLK component and generates the input 64KCLK, 62 is a violation monitoring unit that receives the CLK component and monitors the violation, and 63 is 64KCLK that is the output of the input 64K generating unit 61. It is a free-running 64K generator that receives high-speed CLK and generates free-running 64KCLK.
[0045]
The input 64K generation unit 61 performs a logical sum of the CLK components separated into P / N and reproduces a 64K CLK edge. The free-running 64K generation unit 63 counts the width of 64K at high speed CLK based on the input 64K edge, detects the phase difference by comparing with the CLK edge of the actual input CLK, corrects the count value, and inputs CLK A free-running CLK synchronized with the
[0046]
FIG. 12 is an explanatory diagram of the operation of the input 64K generation unit 61. (A) is an input 64K clock, (b) is a sampling clock, (c) is a free-running 64K clock, and (d) is a count value. The width of input 64KCLK is counted by sampling CLK. At that time, the width of 64K is counted by the sampling CLK, the phase difference between the input 64KCLK and the free-running 64KCLK is detected, the count value is corrected, and the free-running CLK synchronized with the input CLK is generated.
[0047]
The violation monitoring unit 62 detects the 8 kHz / 400 Hz violation superimposed on 64 KCLK, and detects the synchronization timing and missing teeth of 8 kHz / 400 Hz. FIG. 13 is an explanatory diagram of synchronization timing and missing tooth detection. In the figure, 62 is a violation monitoring unit that receives the P / NCLK component and monitors the violation, and 64 is a missing tooth monitoring unit that receives the P / NCLK component and monitors missing teeth.
[0048]
The violation monitoring unit 62 receives the P / N clock and outputs a violation detection signal when the violation is detected at the timing shown in the figure. If there is a violation error, a violation error signal is output. The missing tooth monitoring unit 64 inputs a P / NCLK component and performs a logical sum to generate a 64K CLK. Then, the period between CLK is sampled at a high speed CLK, and the missing tooth is detected by whether or not the clock edge is in the expected position of the edge.
[0049]
The noise removing unit 6 creates a window for detecting the CLK edge from the 64K free-running CLK obtained from the DPLL unit 5. This window opens only to allow the input jitter and removes other CLK components, thereby allowing only a signal having a true CLK edge to pass through the CLK selector 7. FIG. 14 is an explanatory diagram of the operation of the noise removing unit 6. In the figure, reference numeral 71 denotes a mask signal generation unit that receives a free-running 64KCLK and generates a mask signal, and reference numeral 72 denotes a noise mask unit that receives a mask signal from the mask signal generation unit 71 and masks noise.
[0050]
The mask signal generation unit 71 generates a mask signal at the predicted position of the next CLK edge based on the self-running 64 KCLK of the DPLL unit 5. The noise mask unit 72 receives the mask signal from the mask signal generation unit 71 and masks it before and after the CLK edge. For this reason, other than the true CLK component is masked.
[0051]
The CLK selection unit 7 switches between the input CLK component via the noise removal unit 6 and the free-running CLK generated by the DPLL unit 5 according to the missing tooth information of the input CLK. Thus, it is possible to generate 8 kHz / 400 Hz by not stopping the CLK supply to the CLK frequency divider 8 even when the input CLK is missing.
[0052]
FIG. 15 is an explanatory diagram of the operation of the clock selector 7. In the figure, SW is a switch for switching signals, and its a contact is connected to the input 64K and the b contact is connected to the free-running 64K. The common contact is input to the CLK frequency divider 8. The switch SW is switched by an input CLK missing tooth monitoring signal. During normal operation, the input CLK tooth missing monitoring signal is inactive (eg, “L” level), and at this time, the common contact of the switch SW is connected to the a contact side.
[0053]
Here, when a missing tooth occurs in the input 64KCLK, the input CLK missing tooth monitoring signal becomes active (for example, “H” level). As a result, the common contact of the switch SW is connected to the b contact side, and the free-running 64KCLK is selected and supplied to the CLK frequency divider 8. Thus, according to the present invention, CLK can be constantly supplied to the CLK frequency divider 8.
[0054]
The CLK frequency divider 8 is composed of a counter. Then, based on the violation information from the DPLL unit 5, the output CLK (64 KHz) of the CLK selecting unit 7 is divided to output 8 kHz / 400 Hz.
[0055]
FIG. 16 is an explanatory diagram of the operation of the CLK frequency divider 8. In the figure, 81 is a 400 generation counter that receives a 400 Hz violation monitoring signal and generates a 400 Hz CLK, and 82 is an 8K generation counter that receives an 8K violation monitoring signal and generates an 8 kHz CLK. 64 KCLK is provided as a counting CLK in common to the 400 generation counter 81 and the 8K generation counter 82.
[0056]
These counters 81 and 82 divide the output of the CLK selector 7 based on the violation signal and output 8 kHz and 400 Hz.
The CLK state monitoring unit 9 captures the signal law error information in the CLK monitoring unit 4 and the synchronization state information of the DPLL unit 5, displays it as a register, and enables reading from an external processor or the like.
(Supplementary note 1) In a clock generation device having a function of generating a clock to be supplied to a line package from an external basic clock input to a communication device,
Clock generation means for generating a high-accuracy clock;
Tooth loss protection means for protecting against input clock tooth loss,
Noise removing means for removing noise superimposed on the input clock;
Missing detection means for detecting missing input signals;
A clock generation device comprising:
(Supplementary Note 2) In a clock generation method having a function of generating a clock to be supplied to a line package from an external basic clock input to a communication device,
Generating a high precision clock;
Providing protection against missing input clocks;
Removing noise superimposed on the input clock; and
Detecting missing input signals; and
A clock generation method comprising:
(Supplementary note 3) The clock generation device according to supplementary note 1, wherein a clock is extracted from an external basic clock input to the communication device, and noise extraction is performed to generate an extraction clock.
(Supplementary Note 4) A clock extracted from an external clock input to the communication device, passed through a noise removing unit, a DPLL means for receiving the external clock and generating a free-running clock, and a means for detecting a missing tooth from the input clock Receiving a clock that has passed through the noise removing unit and a free-running clock, and selecting means for selecting one of them, and means for giving a missing tooth monitoring signal to the selection means,
The selection means receives a missing tooth monitoring signal and selects a clock that has passed through a noise removing unit when no missing tooth is generated, and a free-running clock when missing tooth is generated. The clock generator according to appendix 1.
(Additional remark 5) It has a part which receives the self-running clock and generates a signal for masking other than the edge part of the clock, and means for masking noise by receiving the output of the clock generating part, the masking means comprising: The clock generation apparatus according to appendix 1, wherein a portion other than an edge portion of the clock is masked by an output of the signal generation means.
(Supplementary Note 6) A clock signal is extracted to separate the P-side clock and the N-side clock, and a means for counting the width of these clocks with a high-speed clock is provided. The clock generator according to appendix 1, wherein when any one of the counters carries out, it is determined that the input signal is missing.
(Supplementary Note 7) A means for inputting a basic clock, comparing the basic clock with a reference voltage using a comparator, creating a P-side clock and an N-side clock, and comparing a phase difference between these two clocks. The clock generation apparatus according to appendix 1, wherein the phase difference comparison means integrates the phase difference and feeds back the output to the reference voltage of the comparator.
[0057]
【The invention's effect】
As described above, according to the present invention, the following effects can be obtained.
(1) According to the first aspect of the present invention, as long as there is a CLK component, a highly accurate CLK that does not depend on the PLL is generated. It has a protection function and eliminates noise from the CLK component to prevent malfunction caused by noise superimposed on the input CLK. By monitoring the input CLK signal law, it is possible to detect missing input signals. It is possible to provide a clock generation method and a clock generation apparatus capable of generating a highly accurate clock.
[0058]
In the case of the conventional device, only accuracy or anti-tooth measures are taken, and therefore, when noise is superimposed on the basic CLK in the station, a malfunction is caused. In the worst case, all the interfaces using the CLK extracted from the basic CLK become unusable, which becomes a big problem in a communication apparatus that accommodates multiple lines such as DSLAM. By applying the present invention, it becomes possible to enhance the tolerance to noise superposition of the basic CLK in the station while maintaining accuracy, and there is a concern in the device configuration that becomes complicated with the diversification of access devices. It is possible to cope with noise in the office building and contribute to the stabilization of the access line.
[0059]
(2) According to the second aspect of the present invention, as long as there is a CLK component, a highly accurate CLK that does not depend on the PLL is generated. It has a protection function and eliminates noise from the CLK component to prevent malfunction caused by noise superimposed on the input CLK. By monitoring the input CLK signal law, it is possible to detect missing input signals. It is possible to provide a clock generation method and a clock generation apparatus capable of generating a highly accurate clock.
[0060]
(3) According to the invention described in claim 3,Predict the position of the edge of the clock, determine whether there is an edge before and after the predicted edge position, and if there is no edge, select the output of the PLL unit as missing tooth; When there is an edge, it is possible to generate a highly accurate clock by selecting the output of the noise removing unit and outputting it to the line package.
[0061]
Thus, according to the present invention, it is possible to provide a clock generation method and a clock generation apparatus that can generate a highly accurate clock.
[Brief description of the drawings]
FIG. 1 is a principle block diagram of the present invention.
FIG. 2 is a diagram illustrating the principle of the first operation of the present invention.
FIG. 3 is a diagram illustrating the principle of the second operation of the present invention.
FIG. 4 is a diagram illustrating the principle of the third operation of the present invention.
FIG. 5 is a diagram illustrating the principle of the fourth operation of the present invention.
FIG. 6 is a diagram illustrating the principle of the fifth operation of the present invention.
FIG. 7 is an explanatory diagram of jitter generation.
FIG. 8 is a block diagram showing an exemplary embodiment of the present invention.
FIG. 9 is a diagram illustrating a transmission waveform of a clock component.
FIG. 10 is a diagram illustrating a configuration example of a clock extraction unit.
FIG. 11 is a diagram illustrating a configuration example of a DPLL unit.
FIG. 12 is an operation explanatory diagram of an input 64K generation unit.
FIG. 13 is an explanatory diagram of synchronization timing and missing tooth detection.
FIG. 14 is an operation explanatory diagram of a noise removal unit.
FIG. 15 is an operation explanatory diagram of a clock selection unit.
FIG. 16 is an explanatory diagram of the operation of the clock divider.
FIG. 17 is a block diagram illustrating a configuration example of a conventional apparatus.
FIG. 18 is a diagram illustrating another configuration example of a conventional apparatus.
[Explanation of symbols]
1 Basic CLK supply device
2 Communication device
3 CLK extractor
4 CLK monitoring unit
5 DPLL section
6 Noise remover
7 CLK selector
8 CLK divider
9 CLK status monitor
10 CLK generator
11 Line section

Claims (5)

In a clock generation device having a function of generating a clock to be supplied to a line package from an external basic clock input to a communication device,
A clock extraction unit that receives a basic clock from a basic clock supply device and extracts and outputs the clock;
A digital PLL unit that receives an output clock from the clock extraction unit and generates and outputs a free-running clock;
A noise removing unit that receives an output clock from the clock extracting unit and removes and outputs noise;
A clock selection unit that selects and outputs either the output of the digital PLL unit or the output of the noise removal unit;
Have
When the input basic clock has no missing teeth, the clock selection section selects and outputs the output of the noise removing section. When the basic clock has a missing teeth, the clock selection section has the digital PLL section. A clock generation device configured to select and output the output of A clock generation method of a clock generation device having a function of generating a clock to be supplied to a line package from an external basic clock input to a communication device,
A clock extraction unit that receives a basic clock from a basic clock supply device and extracts and outputs the clock;
A digital PLL unit that receives an output clock from the clock extraction unit and generates and outputs a free-running clock;
A noise removing unit that receives an output clock from the clock extracting unit and removes and outputs noise;
A clock selection unit that selects and outputs either the output of the digital PLL unit or the output of the noise removal unit;
Have
When the input basic clock has no missing teeth, the clock selection section selects and outputs the output of the noise removing section. When the basic clock has a missing teeth, the clock selection section has the digital PLL section. The clock generation method is characterized in that the output is selected and output . In a clock generation device having a function of generating a clock to be supplied to a line package from an external basic clock input to a communication device,
A clock extraction unit for extracting the basic clock from the basic clock supply device;
A digital PLL unit that receives the clock extracted by the clock extraction unit and generates a free-running clock;
A noise removing unit for removing noise of the clock extracted by the clock extracting unit;
A clock selection unit that selects and outputs either a free-running clock generated by the digital PLL unit or a clock from which noise has been removed by the noise removal unit;
The digital PLL unit includes:
A DPLL function unit that counts clock intervals extracted by a clock extraction unit with a clock faster than the basic clock to predict the edge position of the clock and generates a free-running clock;
A missing tooth monitoring unit that determines that a missing tooth has occurred in the input basic clock and outputs a missing tooth monitoring signal when there is no edge before and after the predicted edge position;
The clock selection unit selects the output of the noise removal unit and outputs it to the circuit package when the missing tooth monitoring signal does not indicate the occurrence of missing tooth, and the missing tooth monitoring signal indicates occurrence of missing tooth. In the case shown, the clock generator is configured to select the output of the PLL unit and output it to the line package . The noise removing unit
  Based on the free-running clock output from the digital PLL unit, a mask signal generating unit that generates a mask signal at the predicted position of the input clock;
  4. The clock generation apparatus according to claim 3, further comprising: a noise mask unit configured to mask and output a clock extracted by the clock extraction unit by using the mask signal except for a real clock component. . In a clock generation device having a function of generating a clock to be supplied to a line package from an external basic clock which is a bipolar signal input to a communication device,
  A clock extraction unit for extracting the basic clock from the basic clock supply device;
  A digital PLL unit that receives the clock extracted by the clock extraction unit and generates a free-running clock;
  A noise removing unit for removing noise of the clock extracted by the clock extracting unit;
  A clock selection unit that selects and outputs either the free-running clock generated by the digital PLL unit or the clock from which noise has been removed by the noise removal unit;
  A clock monitoring unit that receives an output clock from the clock extraction unit and detects clock loss and outputs clock disconnection information;
Have
  The clock monitoring unit further counts the P-side clock of the output clock from the clock extraction unit and is counter-cleared by the N-side clock, and counts the N-side clock and counts by the P-side clock. An N-side clock counter unit that is cleared, and outputs an overflow of the P-side clock counter unit or the N-side clock counter unit to the clock selection unit as detection of a missing clock,
  The clock selection unit selects and outputs the output of the noise removal unit to the line package when the clock disconnection information does not indicate a clock loss, and the clock selection unit outputs the PLL when the clock disconnection information indicates a clock loss. The clock generator is configured to select the output of the unit and output to the line package.

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