JP3924471B2 - Semiconductor integrated circuit including standard cell or macro cell, and placement and routing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit including at least one standard cell or macro cell, and a placement and routing method thereof.
[0002]
[Prior art]
A semiconductor integrated circuit used in a digital electronic device such as a personal computer emits so-called power supply noise to the power supply line of the semiconductor integrated circuit when a large number of functional circuit elements (logic circuit elements) included in the semiconductor integrated circuit perform switching operations simultaneously. . The power supply noise also affects other functional circuit elements connected to the power supply line, and greatly affects the circuit operation itself. Power supply noise is a major cause of electromagnetic interference (EMI) that affects the outside of the semiconductor integrated circuit.
[0003]
Therefore, in general, as shown in FIG. 16, a bypass capacitor C (hereinafter simply referred to as “pass capacitor”) is provided between the power supply line (Vcc) and the ground line (GND) connected to the semiconductor integrated circuit IC. Means have been taken to suppress the generation of power supply noise by connecting in parallel with the circuit IC. When the load current i of the semiconductor integrated circuit IC increases rapidly, the bypass capacitor C supplies the charge charged to the bypass capacitor C to the semiconductor integrated circuit IC to prevent a voltage drop and prevent malfunction of the semiconductor integrated circuit. It was.
[0004]
[Problems to be solved by the invention]
However, high integration, high speed, and low voltage of semiconductor integrated circuits have been advanced in recent years. Especially, with the increase in the speed of semiconductor integrated circuit IC, residual inductance ESL (Equivalent Series Inductance) of bypass capacitor C shown in FIG. Is no longer negligible, and it has become difficult to completely eliminate power supply noise of high frequency components. Furthermore, as the voltage of the semiconductor integrated circuit is lowered, the voltage difference between the H (high) level signal and the L (low) level signal of the functional circuit element is reduced, and malfunction is more likely to occur.
[0005]
As shown in FIGS. 17 and 18, according to another form of the conventional bypass capacitor C, a normal functional standard cell (inverter circuit is illustrated) 102 and a gate capacitor 103 are formed in the semiconductor integrated circuit 101. Is done. The gate capacitor 103 has a gate electrode 112 and a diffusion region 114 through an insulating film 110 such as SiO _2, and is embedded in a region (an unused region) where the functional standard cell 102 such as a filler cell (feed) is not formed. . As described above, since the bypass capacitor C is embedded only in an unused area in the semiconductor integrated circuit 101, it is necessary to provide a large number (or a wide area) of unused areas in order to secure a sufficient capacity. It is necessary to enlarge the area of the circuit IC. This is contrary to the high integration of the semiconductor integrated circuit and is not preferable.
[0006]
Further, in another bypass capacitor C disclosed in Japanese Patent Laid-Open No. 5-41496, a metal capacitor composed of a power supply wiring layer and a ground wiring layer through an insulating layer such as SiO ₂ is disposed in the semiconductor integrated circuit. The Such a metal capacitor is preferable in that it does not increase the area of the semiconductor integrated circuit IC, but the capacitor is smaller than the gate capacitor and power supply noise cannot be sufficiently suppressed.
[0007]
Accordingly, the present invention provides a functional standard cell including a bypass capacitor that has a small residual inductance, does not increase the area, and provides a sufficient capacity in order to eliminate power supply noise of a high frequency component, and a semiconductor integrated circuit having the functional standard cell, It is another object of the present invention to provide a placement and routing method. In addition, the present invention provides a wiring delay standard cell that can easily eliminate a timing rule violation that occurs during layout design by arbitrarily adjusting the wiring capacity of the circuit wiring and delaying a signal propagation time by a desired time. A method of arranging and wiring this is provided.
[0015]
According to the present invention described in claim 1, comprising the steps of placing at least one wiring delay standard cell, wiring delay standard cell for the input and output signal terminals, is formed above the input and output signal terminals A three-terminal capacitor, the first and second intermediate wiring layers having a predetermined area, and a pair of ground wiring layers sandwiching the first and second intermediate wiring layers with an insulating layer interposed therebetween. And connecting the first and second intermediate wiring layers to the input and output signal terminals using the signal wiring layer, and connecting the first and second intermediate wiring layers, respectively. A method for arranging and wiring a semiconductor integrated circuit can be provided. Thus, by adding wiring delay using the wiring delay standard cell, it is possible to easily eliminate the timing rule violation that occurs during the layout design of the semiconductor integrated circuit.
[0016]
According to the second aspect of the present invention, it is possible to provide a placement and routing method further including a step of selecting a predetermined area of the first and second intermediate wiring layers. Thereby, the area of the intermediate wiring layer can be arbitrarily changed, the capacity of the circuit wiring can be arbitrarily selected, and the delay time of the propagation signal can be delayed by a desired time.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a semiconductor integrated circuit according to the present invention will be described below with reference to the accompanying drawings. In the description of the embodiments below, a term indicating a direction (for example, “upward”, “downward”, “x direction”, “y direction”, or “z direction”) is used as appropriate for easy understanding. However, this is for explanation and these terms do not limit the present invention.
[0018]
(Embodiment 1)
A first embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to FIGS. In FIG. 1, this semiconductor integrated circuit 1 is generally electrically connected to a standard cell region 2, a plurality of macro cells 3a, 3b, 3c, a power supply ring 4 and a ground ring 5 surrounding them, and rings 4, 5 respectively. And a power supply strap 6 and a grounding strap 7 extending in the y direction and connected to the. Further, a plurality of I / O cells 8 for receiving power supply from an external peripheral device (not shown) or transmitting / receiving control signals are formed at the peripheral edge of the semiconductor integrated circuit 1.
[0019]
The standard cell region 2 further includes a plurality of functional standard cells 10. As shown in FIG. 2, each functional standard cell 10 generally includes a power line 12 connected to the power ring 4 and the power strap 6, a ground line 14 connected to the ground ring 5 and the ground strap 7, and a power line. 12 and a functional circuit element 16 that receives power supply from the ground wiring 14. Further, the functional standard cell 10 having the inverter function illustrated in FIG. 2 has a P-type transistor region 22 formed on the semiconductor substrate 18 (the cross-sectional hatching is omitted for the sake of clarity) between the power supply wiring 12 and the ground wiring 14. And an N-type transistor region 24 and input and output signal terminals 26 and 28. In addition, an AND circuit, a NAND circuit, an OR circuit, a NOR circuit, or the like is prepared as the functional circuit element 16, and input and output signal terminals corresponding to functions are formed.
[0020]
Further, as shown in FIG. 3, the functional standard cell 10 has, for example, a multilayer wiring structure composed of a metal 1 layer (lowermost layer) M1 to a metal 6 layer (uppermost layer) M6. The wiring layer extending in the x direction shown in FIG. 2 is given priority to metal odd layers (for example, metal 1 layer, metal 3 layer, etc.), and the wiring layer extending in the y direction is preferential to metal even layers (for example, metal 2 layer, metal 4 layer, etc.). Used to configure. The metal 5 layer M5 located one layer below the uppermost layer is connected to the power supply ring 4 and the power supply strap 6. The uppermost metal 6 layer M6 and the metal 4 layer M4 that is two layers below the uppermost layer are connected to the ground ring 5 and the ground strap 7. At this time, whether 12 (M1) is connected to the power supply ring 4 and the power supply strap 6 is arbitrarily selected.
[0021]
Further, in the functional standard cell 10 shown in FIG. 3, the metal 5 layer M5 is formed of the metal 1 layer M1 through the power supply columnar conductive portion 30 composed of the metal 2 layer M2 to the metal 4 layer M4 and the via holes V1 to V4. The power supply wiring 12 is electrically connected. Similarly, the metal 4 layer M4 is connected to the ground wiring 14 via the ground columnar conductive portion 32 constituted by the metal 2 layer M2, the metal 3 layer M3, and the via holes V1 to V3. The via holes V1 to V4 are usually formed of the same metal as the metal layer, and an insulating layer 34 such as SiO ₂ is embedded between the metal layers (although the cross-sectional hatching is omitted for the sake of clarity).
[0022]
Further, the metal 4 layer M4 to the metal 6 layer M6 have substantially the same area as the functional standard cell 10 on the xy plane, as shown in FIGS. 4 (a) to 4 (c). Is formed. In the functional standard cell 10 shown in FIG. 3B thus configured, the metal 5 layer M5 to which the power supply voltage is supplied, the metal 4 layer M4 and the metal 6 layer M6 to be grounded are the three-terminal capacitor 36 of the present invention. Further, each functional circuit element 16 is supplied with power via the power and ground columnar conductive portions 30 and 32, the power wiring 12 and the ground wiring 14. The three-terminal capacitor 36 is known to have a smaller residual inductance than a general two-terminal capacitor, and by radiating from the functional standard cell 10 or the vicinity thereof by providing it as a bypass capacitor in the functional standard cell 10. It is possible to effectively eliminate the power supply noise of the generated high frequency component and reduce the power supply noise.
[0023]
The three-terminal capacitor 36 of the present invention can also be formed in the I / O cell 8 to which an external power supply voltage and ground voltage are supplied. As a result, it is possible to prevent power supply noise from entering the peripheral edge of the semiconductor integrated circuit 1.
[0024]
Preferably, all functional standard cells 10 formed in the standard cell region 2 have the three-terminal capacitor 36 of the present invention, and the grounded uppermost metal 6 layer is the standard on the xy plane. It is formed continuously so as to have substantially the same area as the cell region 2. At this time, both power supply noise radiated from the functional standard cell 10 to the outside and power supply noise entering the standard cell region 2 from an external peripheral device (not shown) are shielded (shielded). Thus, the ground metal 6 layer M6 formed on one surface suppresses power source noise (electromagnetic wave interference) radiated from the inside to the outside of the semiconductor integrated circuit 1 and from the outside to the inside as much as possible, and the semiconductor integrated having a high chip shield effect. Circuit 1 can be realized.
[0025]
Alternatively, the functional standard cell 10 having the three-terminal capacitor 36 may be embedded only in a region (an unused region) where a functional circuit element such as a filler cell (feed) is not formed. As a result, the three-terminal capacitor 36 can be disposed above or adjacent to the functional standard cell 10 to be protected from power supply noise. Therefore, the power supply noise can be efficiently controlled only in a selective region. Can be taken.
[0026]
Further, when it is considered that the influence of the migration effect of the metal layer is large, the slot shown in FIGS. 5A to 5C is formed from the metal 4 layer M4 to the metal 6 layer M6 constituting the three-terminal capacitor 36. It is still more preferable to provide 38.
[0027]
(Embodiment 2)
A second embodiment of the semiconductor integrated circuit according to the present invention will be described with reference to FIGS. Since the semiconductor integrated circuit 1 of the second embodiment is the same as that of the first embodiment except for the stacked structure of the functional standard cells 10, the description of the overlapping contents is omitted. 3A and FIG. 6, the functional standard cell 10 according to the second embodiment has a high dielectric layer 40 such as Ta ₂ O ₅ on the grounded metal 4 layer M4. On the body layer 40, a metal layer 42 different from the metal 4 layer M4 and the metal 5 layer M5 is provided. The metal layer 42 is connected via a via hole 44 to a metal 5 layer M5 to which a power supply voltage is supplied. As shown in FIG. 6, the functional standard cell 10 of the second embodiment configured as described above includes a capacitor formed between the metal 5 layer M5 connected to the power supply voltage and the metal 6 layer M6 grounded, and the power supply voltage. And an MIM (Metal-Insulator-Metal) capacitor formed between the metal layer 42 connected to the ground and the metal 4 layer M4 grounded. Such an MIM capacitor has the high dielectric layer 40 interposed between the metal layers and the shorter distance between the metal 4 layer M4 and the metal layer 42. It has a larger capacity than the capacitor formed between the metal 6 layers M6. That is, since the semiconductor integrated circuit 1 of the second embodiment includes the three-terminal capacitor 36 including a large-capacity MIM capacitor, the function of eliminating power supply noise is higher than that of the three-terminal capacitor 36 of the first embodiment.
[0028]
Several modified examples of the second embodiment will be described with reference to FIGS. The functional standard cell 10 shown in FIG. 7 has a three-terminal capacitor 36 including an MIM capacitor formed between the metal 5 layer M5 and the metal 6 layer M6. That is, a high dielectric layer 46 such as Ta ₂ O ₅ is laminated on the metal 5 layer M 5 connected to the power supply voltage, and another metal layer 48 is formed on the high dielectric layer 46. This metal layer 48 is connected via a via hole 50 to a metal 6 layer M6 to which a ground voltage is supplied. Thus, the functional standard cell 10 shown in FIG. 7 similarly includes the three-terminal capacitor 36 including the MIM capacitor having a high function of eliminating power supply noise.
[0029]
More preferably, as shown in FIG. 8, MIM capacitors may be stacked between the metal 4 layer M4 and the metal 5 layer M5 and between the metal 5 layer M5 and the metal 6 layer M6. The functional standard cell 10 having the MIM three-terminal capacitor 36 configured as described above has a higher function of eliminating power supply noise.
[0030]
(Embodiment 3)
A third embodiment of the semiconductor integrated circuit according to the present invention will be described with reference to FIGS. Since the semiconductor integrated circuit 1 of the third embodiment is the same as that of the second embodiment except for the stacked structure of the functional standard cells 10, the description of the overlapping contents is omitted. The functional standard cell 10 of Embodiment 3 includes a high dielectric layer 52 such as Ta ₂ O ₅ laminated on a grounded metal 4 layer M4, and a metal 4 formed on the high dielectric layer 52. The metal layer 54 is different from the layer M4 and the metal 5 layer M5. The metal 5 layer M5 is divided into three regions including a power source region 56 connected to a power source voltage, a grounded ground region 58, and a wiring region 60. The power supply region 56 and the wiring region 60 are connected to the metal layer 54 through via holes 62 and 64, respectively.
[0031]
As a result, the functional circuit element 16 of the functional standard cell 10 is connected to the power supply voltage via the power supply region 56, the metal layer 54, the wiring region 60, the via holes 62 and 64, and the power supply columnar conductive portion 30, and similarly It is grounded through the four layers M4 and the grounding columnar conductive portion 32. On the other hand, an MIM capacitor is formed between the grounded metal 4 layer M4 and the metal layer 54, and another capacitor is formed between the ground region 58 of the metal 5 layer M5 and the metal layer 54. In this manner, as in the second embodiment, the functional standard cell 10 having the three-terminal capacitor 36 including the MIM capacitor having a high function of eliminating power supply noise can be realized.
[0032]
(Embodiment 4)
A fourth embodiment of the semiconductor integrated circuit according to the present invention will be described with reference to FIGS. The semiconductor integrated circuit 1 of the fourth embodiment is the same as that of the first embodiment except that at least one wiring delay standard cell 70 is formed in addition to the plurality of functional standard cells 10 in the standard cell region 2. The wiring delay standard cell 70 will be described in detail below. Similar to the functional standard cell 10 of the first embodiment, the wiring delay standard cell 70 has a multilayer wiring structure including the metal 1 layer M1 to the metal 6 layer M6. In the wiring delay standard cell 70 shown in FIG. 11A, for example, input / output terminals 72 and 74 are formed on a pair of metal 1 layers M1. Further, as shown in FIG. 12 (a), the columnar conductive portions 76 and 78 formed by the metal 3 layer M3 and the metal 4 layer M4 and the via holes V2 to V4 connect the metal 2 layer M2 and the metal 5 layer M5. Yes. Thus, the metal 5 layer M5, the opposed metal 4 layer M4 and metal 6 layer M6 constitute a three-terminal capacitor 80 having an equivalent circuit as shown in FIG. Here, the metal 5 layer M5 disposed between the grounded metal 4 layer M4 and the metal 6 layer M6 (ground wiring layer) is referred to as an intermediate wiring layer 82. In this example, the metal 4 layer M4 and the metal 6 layer M6 are ground wiring layers, but this is not limited.
[0033]
By adding the thus configured three-terminal capacitor 80 to the circuit wiring layout for wiring each functional standard cell 10, the wiring capacity of the added circuit wiring can be increased. In general, when the wiring capacity of the circuit wiring increases, a signal propagating through the wiring between the functional standard cells 10 is delayed according to the wiring capacity. By actively utilizing this and intentionally delaying a signal propagating through a specific wiring by an arbitrary time, the timing shift generated in each wiring is adjusted in the wiring layout design, and the entire semiconductor integrated circuit 1 The timing rule violation can be resolved. At this time, by arbitrarily changing the area in the xy plane of the intermediate wiring layer 82 shown in FIG. 11B, the capacity of the circuit wiring is arbitrarily selected, and the delay time of the propagation signal is delayed by a desired time. Can do.
[0034]
Here, a method for placing and routing the semiconductor integrated circuit 1 using an automatic placement and routing tool will be described with reference to the flowchart shown in FIG. First, in step ST01, the automatic placement and routing tool extracts attribute information such as netlist information, standard cell and macrocell layout information, delay information, and power consumption information from the netlist, cell library, and control information memory, respectively. Also, placement constraint information and wiring constraint information that can be specified by the user are read.
[0035]
In step ST02, the automatic placement and routing tool arranges standard cells and macrocells at optimized positions based on the net list, and in step ST03, each functional standard is configured so that the semiconductor integrated circuit forms a desired logic circuit. The input / output terminals 26 and 28 of the cell 10 are wired.
[0036]
In step ST04, the automatic placement and routing tool determines whether or not a timing rule violation occurs in all wired circuit wirings. When the circuit wiring that does not satisfy the timing rule is confirmed (in the case of YES), the automatic placement and routing tool determines in step ST05 how much the signal transmission time should be delayed in the circuit wiring that has violated the timing rule. Calculate the signal delay time. Next, based on this signal delay time, the wiring capacitance value to be added to the circuit wiring is obtained, and the area of the intermediate wiring layer 82 of the placement delay standard cell 70 shown in FIGS. 11 and 12 is determined.
[0037]
However, as described above, when the placement delay standard cell 70 is used to delay a signal propagating a specific wiring by a desired time, the automatic placement and routing tool uses the input and input / output terminals of the placement delay standard cell 70. Since 72 and 74 are short-circuited via the metal 5 layer M5, these terminals are recognized as the same terminals, and these terminals cannot be incorporated into the circuit wiring layout.
[0038]
Therefore, in step ST05, the automatic placement and routing tool forms a temporary wiring delay standard cell 84 instead of the placement delay standard cell 70 (hereinafter referred to as “deterministic placement delay standard cell”). . On the other hand, a wiring delay standard cell to be added is added to the net list in a timely manner.
[0039]
In the provisional wiring delay standard cell 84 shown in FIG. 14B and FIG. 15, the metal 5 layer M5 is formed at the first and first points in the approximate center of the xy plane instead of forming the intermediate wiring layer 82. It is divided into two regions consisting of two intermediate regions 86 and 88. The first and second intermediate regions 86, 88 are electrically isolated slightly spaced apart.
[0040]
The automatic placement and routing tool returns to step ST02 and places the temporary wiring delay standard cell 84 at an appropriate position.
[0041]
In step ST03, the automatic placement and routing tool reroutes the circuit wiring including the provisional wiring delay standard cell 84 arranged in step ST02.
[0042]
In step ST05, steps ST02 to ST06 are repeated until no timing rule violation is confirmed (NO).
[0043]
In step ST07, all temporary placement delay standard cells 84 are replaced with definitive placement delay standard cells 70, thereby connecting the first and second intermediate regions 86 and 88, and placement and routing. Complete the process.
[0044]
As described above, by adding the wiring delay using the placement delay standard cell 70 having the three-terminal capacitor 80 of the present invention, it is possible to easily eliminate the timing rule violation that occurs during the layout design of the semiconductor integrated circuit. it can.
[0050]
According to the first aspect of the present invention, by using the wiring delay standard cell and adding the wiring delay, it is possible to easily eliminate the timing rule violation that occurs during the layout design of the semiconductor integrated circuit.
[0051]
According to the second aspect of the present invention, it is possible to arbitrarily change the area of the intermediate wiring layer, arbitrarily select the capacitance of the circuit wiring, and delay the delay time of the propagation signal by a desired time.
[Brief description of the drawings]
FIG. 1 is a plan view of a semiconductor integrated circuit according to a first embodiment of the present invention.
2A is a plan view of the functional standard cell according to the first embodiment when a wiring layer above the metal 1 layer is removed, and FIG. 2B is a functional standard according to the first embodiment. It is a top view of a cell.
3A is a cross-sectional view of the functional standard cell of the first embodiment when viewed from the line IIIA-IIIA in FIG. 2, and FIG. 3B is an equivalent circuit diagram thereof.
4 (a), 4 (b), and 4 (c) are plan views of a metal 4 layer, a metal 5 layer, and a metal 6 layer, respectively.
FIGS. 5 (a), 5 (b), and 5 (c) are plan views of a metal 4 layer and a metal 5 layer and a metal 6 layer having a slot for which migration countermeasures are taken, respectively. is there.
FIG. 6 is a cross-sectional view of the functional standard cell according to the second embodiment, which is the same cross-sectional view as FIG. 3 (a).
7 is a cross-sectional view of a functional standard cell according to a modification of the second embodiment, and is the same cross-sectional view as FIG. 3 (a).
8 is a cross-sectional view of a functional standard cell according to still another modification of the second embodiment, and is the same cross-sectional view as FIG. 3 (a).
FIG. 9A is a plan view of a functional standard cell according to the third embodiment, and FIG. 9B is a plan view showing a metal 4 layer and a metal layer.
FIG. 10 is a cross-sectional view of the functional standard cell as viewed from the line XX in FIG.
FIG. 11A is a plan view when a wiring layer above the metal 2 layer is removed from the definite wiring delay standard cell according to the fourth embodiment, and FIG. 12 is a plan view of a definite wiring delay standard cell according to mode 4. FIG.
12A is a cross-sectional view of a definite wiring delay standard cell viewed from the XII-XII line of FIG. 11B, and FIG. 12B is an equivalent circuit diagram thereof. .
FIG. 13 is a flowchart illustrating a method for arranging and wiring the wiring delay standard cell according to the fourth embodiment;
FIG. 14A is a plan view of the provisional wiring delay standard cell according to the fourth embodiment when a wiring layer above the metal 2 layer is removed, and FIG. 12 is a plan view of a provisional wiring delay standard cell according to mode 4. FIG.
FIG. 15 is a cross-sectional view of a provisional wiring delay standard cell viewed from line XV-XV in FIG.
FIG. 16 is an equivalent circuit diagram including a conventional bypass capacitor.
FIG. 17 is a plan view of a conventional semiconductor integrated circuit including a gate capacitance.
FIG. 18 is a cross-sectional view of a provisional wiring delay standard cell as viewed from line XVIII-XVIII in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Semiconductor integrated circuit 1, 2 ... Standard cell area | region, 3a, 3b, 3c ... Macro cell, 4 ... Power supply ring, 5 ... Grounding ring 5, 6 ... Power supply strap, 7 ... Grounding strap, 8 ... I / O cell, 10 ... Functional standard cell, 12 ... Power supply wiring, 14 ... Ground wiring, 16 ... Functional circuit element, 22 ... P-type transistor region, 24 ... N-type transistor region, 26 ... Input signal terminal, 28 ... Output signal terminal, M1 to M6 ... Metal layer, V1 to V6 ... Via hole, 30 ... Power supply columnar conductive portion, 32 ... Ground columnar conductive portion, 34 ... Insulating layer, 36 ... 3-terminal capacitor, 38 ... Slot, 40 ... High dielectric layer, 42,48, 54 ... metal layer, 44 ... via hole, 52 ... high dielectric layer, 56 ... power supply region, 58 ... ground region, 60 ... wiring region, 62,64 ... via hole, 70 ... wiring delay stander Docell, 72, 74 ... I / O terminal, 76, 78 ... Columnar conductive portion, 80 ... Three-terminal capacitor, 82 ... Intermediate wiring layer, 84 ... Temporary wiring delay standard cell, 86 ... First intermediate region, 88 ... second intermediate region.

Claims (2)

A method of placing and wiring a semiconductor integrated circuit,
  Placing at least one wiring delay standard cell;
  The wiring delay standard cell includes input and output signal terminals, and a three-terminal capacitor formed above the input and output signal terminals.
  The three-terminal capacitor has first and second intermediate wiring layers having a predetermined area, and a pair of ground wiring layers sandwiching the first and second intermediate wiring layers via an insulating layer,
  Using the signal wiring layer to connect the first and second intermediate wiring layers to the input and output signal terminals, respectively;
  And a step of connecting the first and second intermediate wiring layers to each other. The placement and routing method according to claim 1,
A placement and routing method, further comprising the step of selecting a predetermined area of the first and second intermediate wiring layers.

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