JP3919198B2 - Television and computer equipped with electro-optical device - Google Patents

Description

  The present invention relates to an active electro-optical device, and more particularly to an active liquid crystal electro-optical device, in which a clear gradation level can be set.

  The liquid crystal composition has different dielectric constants in the horizontal and vertical directions with respect to the molecular axis due to its material properties, so it can be easily aligned horizontally or vertically with respect to an external electric field. it can. The liquid crystal electro-optical device performs ON / OFF display by controlling the amount of transmitted light or the amount of dispersion using the anisotropy of the dielectric constant.

  FIG. 2 shows the electro-optical characteristics of the nematic liquid crystal. When the applied voltage is small Va (point A), the amount of transmitted light is almost 0%, in the case of Vb (point B), about 20%, in the case of Vc (point C), about 70%, Vd (point D). In this case, it becomes about 100%. In other words, if only the points A and D are used, black and white two-tone display can be performed, and if the rising portion of the electro-optical characteristics such as points B and C is used, intermediate gray-scale display can be performed.

  Conventionally, in the case of gradation display of a liquid crystal electro-optical device using a TFT, gradation display is performed by adjusting the voltage in an analog manner by changing the gate application voltage or the source-drain application voltage of the TFT.

  A description will be given of a gradation display method of a liquid crystal electro-optical device using TFT. An N-channel thin film transistor used in a conventional liquid crystal electro-optical device has voltage-current characteristics as shown in FIG. The voltage-current characteristics shown in FIG. 3 are the characteristics of an N-channel thin film transistor using amorphous silicon and the characteristics of an N-channel thin film transistor using polysilicon.

  By controlling the voltage applied to the gate electrode in an analog manner, the drain current can be controlled, and the magnitude of the electric field applied to the liquid crystal can be changed. As a result, gradation display is possible.

  However, for example, when a liquid crystal electro-optical device having a pixel number of 640 × 400 dots is assumed, it is very difficult to realistically manufacture all the characteristics of a total of 256,000 TFTs. In view of mass productivity and yield, 16 gradation display is considered the limit.

  In addition, a method of performing gradation display by setting the gate voltage to a constant value, controlling only ON / OFF, and controlling the source / drain voltage is also considered. The key is considered the limit. Analog gradation display control is greatly affected by TFT characteristics, and clear display requires difficulty.

  As another method, a gradation display method using a plurality of frames has been proposed. As shown in FIG. 12, for example, when gradation display is performed using 10 frames, the pixel A is 20% on average by transmitting 2 frames out of 10 frames and making the remaining 8 frames non-transparent. Can be displayed as transparent. Similarly, the pixel B can be displayed as 70% transmission, and the pixel C can be displayed as 50% transmission.

  However, when such a display is performed, the number of frames is substantially reduced, and therefore, flickering and display damage have occurred. In order to solve this, an increase in the frame frequency or the like has been devised, but this is a technology that has limitations because it is difficult to increase the power consumption accompanying the increase in the drive frequency or to increase the speed of the IC.

  Therefore, in order to clarify the applied voltage level, a reference voltage value that is repeated not at an analog value but at a constant period is input as a signal from the controller side, and the timing at which the reference signal is connected to the TFT is controlled by a digital value. Accordingly, the present invention is characterized in that a method of covering the characteristic variation of the TFT is taken by controlling the voltage applied to the TFT.

  That is, one of the signal lines used for arbitrary pixel drive selection for gradation display of an electro-optical device using a display drive method having a display timing related to the time F for writing one screen and the time t for writing to one pixel. A selection signal is applied to a reference signal having a voltage change with the period of time t and another signal line at an arbitrary timing within the time t, a voltage applied to the liquid crystal is determined, and the voltage is actually applied to the pixel. It is characterized in that gradation can be displayed without changing the time F by applying. In addition, this timing does not depend on the data transfer, but a high-speed clock is added to the driver IC itself mounted on the liquid crystal electro-optical device, and processing is performed in the signal processing portion, so that the data transfer speed of the conventional CMOS is achieved. It is characterized by enabling high-speed control that is not limited to several tens of MHz, which was the limit of the above.

FIG. 1 specifically shows a driving waveform of the electro-optical device according to the present invention. This is shown as an example in which this drive waveform is put in the 2 × 2 matrix shown in FIG. Here, a half wave of a sine wave is used as the reference signal waveform. Sine waves 309 and 310 are applied to V _DD1 303 and V _DD2 304 corresponding to the scanning line direction, and two-polarity (hereinafter referred to as “bipolar”) signals are applied to V _GG1 301 and V _GG2 302 corresponding to the information line direction. The part controlled by the digital value performs the timing of applying this bipolar signal. In other words, by changing the timing for selecting a signal whose voltage is changed as shown in 309 and 310, the amount of charge and the potential accumulated at the point A are determined, and the potential 313 of the counter electrode is arbitrarily taken. The magnitude of the electric field applied to the pixel and the liquid crystal is determined.

  The timing at which the bipolar signal is applied is not determined by the transfer speed of the information signal, and in the configuration according to the present invention, it is limited by the basic clock input to the driver IC directly connected to the liquid crystal electro-optical device. That is, when a liquid crystal electro-optical device with 640 × 400 dots is considered, the drive frequency is about 20 MHz from the limit of CMOS. To calculate the number of gradation display using this value, the drive frequency is the number of scanning lines. And the product of the number of frames, the bipolar pulse, and the gradation display number, it is sufficient to divide 20 MHz by (400 × 60 × 2). Therefore, the gradation display number can be displayed up to 416 gradations. . It goes without saying that up to 832 gradations are possible by dividing the display screen into two. Examples will be described below, and further detailed description will be added.

  The present invention is characterized in that digital gradation display is performed in contrast to the conventional analog gradation display. As an effect, for example, when a liquid crystal electro-optical device having a pixel number of 640 × 400 dots is assumed, it is very difficult to produce the characteristics of all the 256,000 TFTs without variation. In view of mass productivity and yield, the 16-grayscale display is considered to be the limit, but in order to clarify the applied voltage level, the reference voltage value is input as a signal instead of the analog value from the controller side. In addition, the present invention adopts a method for covering the characteristic variation of the TFT by controlling the voltage applied to the TFT by controlling the timing of connecting the reference signal to the TFT with a digital value. Therefore, clear digital gradation display is possible.

  In addition, by using two types of drive frequencies, clear digital gradation display is possible without changing the number of frames for screen rewriting. The occurrence of flicker associated with a decrease in the number of frames can be avoided.

  For example, when a normal analog gradation display is performed on a liquid crystal electro-optical device in which 256,000 TFTs of 640 × 400 dots are formed in a 300 mm square, there is about ± 10% variation in TFT characteristics. 16 gradation display was the limit. However, when digital gradation display according to the present invention is performed, it is difficult to be affected by variations in characteristics of TFT elements, and therefore, it is possible to display up to 256 gradations, and in color display, there are a wide variety of 16,777,216 colors. Display of various colors. When projecting software such as television images, for example, even the “rock” of the same color has a slightly different hue due to its fine depressions. When a display close to natural colors is to be displayed, difficulty is required with 16 gradations. The gradation display according to the present invention makes it possible to add these minute color tone changes.

  In this embodiment, a wall-mounted television is manufactured using a liquid crystal display device having a circuit configuration as shown in FIG. The TFT at that time was polycrystalline silicon using laser annealing.

  An arrangement configuration of actual electrodes and the like corresponding to this circuit configuration is shown in FIG. In order to simplify the explanation, only the portion corresponding to 2 × 2 (or less) is shown. The actual drive signal waveform is shown in FIG. In order to simplify the description, the description will be given with the signal waveform in the case of a 2 × 2 matrix configuration.

  First, a method for manufacturing a liquid crystal panel used in this embodiment will be described with reference to FIGS. In FIG. 7A, a silicon oxide film as a blocking layer 51 is formed on a glass 50 that can withstand a heat treatment of less expensive 700 ° C. or less, such as about 600 ° C., such as quartz glass, using a magnetron RF (high frequency) sputtering method. Fabricate to a thickness of ~ 3000 mm. The process conditions were an oxygen 100% atmosphere, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 cm / min.

A silicon film 52 was formed on the silicon film by plasma CVD. The film formation temperature was 250 ° C. to 350 ° C., and in this example, 320 ° C., and monosilane (SiH ₄ ) was used. Not only monosilane (SiH ₄ ) but also disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used. These were introduced into a PCVD apparatus at a pressure of 3 Pa, and a high frequency power of 13.56 MHz was applied to form a film. At this time, 0.02 to 0.10 W / cm ² is appropriate for the high-frequency power, and 0.055 W / cm ² was used in this example. The flow rate of monosilane (SiH ₄ ) was 20 SCCM, and the deposition rate at that time was about 120 liters / minute. Boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane in order to control the threshold voltage (Vth) of PTFT and NTFT to be approximately the same. . Further, not only this plasma CVD but also sputtering or low pressure CVD may be used for forming a silicon layer which becomes a channel region of the TFT, and the method will be briefly described below.

When the sputtering method is used, the back pressure before sputtering is set to 1 × 10 ⁻⁵ Pa or less, the target is single crystal silicon, and the atmosphere is mixed with 20 to 80% hydrogen in argon. For example, 20% argon and 80% hydrogen. The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputtering output was 400 to 800 W, and the pressure was 0.5 Pa.

In the case of forming by a reduced pressure vapor phase method, disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) is supplied to a CVD apparatus at 450 to 550 ° C., for example, 530 ° C., which is 100 to 200 ° C. lower than the crystallization temperature. A film was formed. The pressure in the reactor was 30 to 300 Pa. The film formation rate was 50 to 250 cm / min. Boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane in order to control the threshold voltage (Vth) of PTFT and NTFT to be approximately the same. .

The film formed by these methods preferably has oxygen of 5 × 10 ²¹ cm ⁻³ or less. In order to promote crystallization, it is desirable that the oxygen concentration be 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less. This concentration was selected because the current increases. If this oxygen concentration is high, crystallization is difficult and the laser annealing temperature must be increased or the laser annealing time must be increased. Hydrogen was 4 × 10 ²⁰ cm ⁻³ , and compared with silicon 4 × 10 ²² cm ⁻³ , it was 1 atomic%.

Further, in order to further promote crystallization with respect to the source and the drain, the oxygen concentration is set to 7 × 10 ¹⁹ cm ⁻³ or less, preferably 1 × 10 ¹⁹ cm ⁻³ or less, and the channel formation region of the TFT constituting the pixel is formed. In addition, oxygen may be added so as to be 5 × 10 ^{20 to} 5 × 10 ²¹ cm ⁻³ by ion implantation.

  By the above method, an amorphous silicon film was formed to a thickness of 500 to 5000 mm, in this example, 1000 mm.

Thereafter, as shown in FIG. 7B, a pattern was formed in which only the source / drain regions were opened using the photoresist 53 using the mask P1. A silicon film 54 to be an n-type active layer was formed thereon by plasma CVD. The film forming temperature was 250 ° C. to 350 ° C., and in this embodiment, 320 ° C., and monosilane (SiH ₄ ) and monosilane based phosphine (PH ₃ ) having a concentration of 3% were used. These were introduced into the PCVD apparatus at a pressure of 5 Pa, and a high frequency power of 13.56 MHz was applied to form a film. At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2.

The specific conductivity of the n-type silicon layer obtained by this method was about 2 × 10 ⁻¹ [Ωcm ⁻¹ ]. The film thickness was 50 mm. Thereafter, using a lift-off method, the resist 53 was removed, and source / drain regions 55 and 56 were formed.

A p-type active layer was formed using the same process. The introduced gas used here was monosilane (SiH ₄ ) and monosilane-based diborane (B ₂ H ₆ ) having a concentration of 5%. These were introduced into a PCVD apparatus at a pressure of 4 Pa, and a high frequency power of 13.56 MHz was applied to form a film. At this time, the high-frequency power is suitably 0.05~0.20W / cm ^2, in this embodiment using 0.120W / cm ^2. The specific conductivity of the p-type silicon layer obtained by this method was about 5 × 10 ⁻² [Ωcm ⁻¹ ]. The film thickness was 50 mm. Thereafter, source / drain regions 59 and 60 were formed by using a lift-off method in the same manner as the N-type region. Thereafter, the silicon film 52 was removed by etching using the mask P3 to form an N-channel thin film transistor island region 63 and a P-channel thin film transistor island region 64.

Thereafter, using a XeCl excimer laser, the source / drain / channel regions were laser-annealed, and at the same time, the active layer was laser-doped. The laser energy at this time has a threshold energy of 130 mJ / cm ² , and 220 mJ / cm ² is required to melt the entire film thickness. However, when energy of 220 mJ / cm ² or more is irradiated from the beginning, hydrogen contained in the film is suddenly released, so that the film is broken. For this reason, it is necessary to melt after first expelling hydrogen with low energy. After performing the flush hydrogen in the first 150 mJ / cm ² in the present embodiment was subjected to crystallization at 230 mJ / cm ^2.

By annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high order in a state after the film formation of silicon is particularly crystallized and tends to be in a crystalline state. However, since silicon is present between these regions, the silicon atoms pull each other. When measured by laser Raman spectroscopy, a peak shifted to a lower frequency side than the peak 522 cm ⁻¹ of single crystal silicon is observed. The apparent particle size is 50 to 500 mm when calculated from the full width at half maximum, but in reality, there are many regions with high crystallinity and a cluster structure, and the clusters are bonded to each other by silicon ( A film having an anchoring structure could be formed.

As a result, the coating film exhibits a state that it may be said that there is substantially no grain boundary (hereinafter referred to as GB). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which a so-called GB is clearly present. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² / VSec and electron mobility (μe) = 15 to 300 cm ² / VSec are obtained.

  On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000 mm, for example 1000 mm. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix sodium ions.

Thereafter, a silicon film in which phosphorus enters a concentration of 1 to 5 × 10 ²¹ cm ^{−3 on} the upper side or a multilayer of this silicon film and molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ thereon. A film was formed. This was patterned with a fourth photomask P4 to obtain FIG. A gate electrode 66 for NTFT and a gate electrode 67 for PTFT were formed. For example, the channel length was 7 μm, the gate electrode was formed with a thickness of 0.2 μm of phosphorus-silicon, and molybdenum was formed thereon with a thickness of 0.3 μm.

  In addition, when aluminum (Al) is used as a gate electrode material, the surface is anodized after patterning with a fourth photomask 69, so that the self-line method can be applied. Since the drain contact hole can be formed at a position closer to the gate, the characteristics of the TFT can be further improved by reducing the mobility and the threshold voltage.

  In this way, a C / TFT can be produced without applying temperature in all steps to 400 ° C. or higher. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and it can be said that this process is extremely suitable for the large-screen liquid crystal display device of the present invention.

  In FIG. 8A, an interlayer insulator 68 is formed as a silicon oxide film by the sputtering method described above. The silicon oxide film may be formed by LPCVD, photo CVD, or atmospheric pressure CVD. For example, the electrode window 79 is formed to a thickness of 0.2 to 0.6 μm, and then the electrode window 79 is formed using the fifth photomask P5. Thereafter, aluminum is formed to a thickness of 0.3 .mu.m on the entire surface by sputtering to produce leads 74 and contacts 73 and 75 using a sixth photomask P6, and then the surface is planarized with an organic resin. 77 For example, a translucent polyimide resin was applied and formed, and electrode drilling was performed again with the seventh photomask P7. Further, ITO (indium tin oxide) was formed to a thickness of 0.1 μm on all of these by sputtering, and a pixel electrode 71 was formed using an eighth photomask P8. This ITO was formed at room temperature to 150 ° C., and was achieved by oxygen at 200 to 400 ° C. or annealing in the atmosphere.

The TFT obtained has PTFT mobility of 40 (cm ² / Vs), Vth of −5.9 (V), NTFT mobility of 80 (cm ² / Vs), and Vth of 5 0.0 (V).

  One substrate for a liquid crystal electro-optical device manufactured according to the above method could be obtained.

  FIG. 6 shows an arrangement of electrodes and the like of this liquid crystal display device. An N-channel thin film transistor and a P-channel thin film transistor are provided at the intersection of the first signal line 3 and the second signal line 4. A matrix configuration using such a C / TFT was provided. The NTFT 13 is connected to the second signal line 4 through a contact at the input end of the drain 10, and the gate 9 is connected to the first signal line 3. The output terminal of the source 12 is connected to the electrode 17 of the pixel through a contact.

  On the other hand, the PTFT 22 has an input terminal of the drain 20 connected to the second signal line 4 via a contact, a gate 21 connected to the signal line 3, and an output terminal of the source 18 connected to the pixel electrode like the NTFT via a contact. 17 is connected. By repeating this structure left and right and up and down, a liquid crystal display device with large pixels of 640 × 480 and 1280 × 960 can be obtained. In this embodiment, it is 1920 × 400. In this way, a first substrate was obtained.

  A method for manufacturing the other substrate is shown in FIGS. A polyimide resin in which a black pigment is mixed with polyimide was formed on a glass substrate to a thickness of 1 μm by using a spin coating method, and a black stripe 81 was formed using a ninth photomask P9. Thereafter, a polyimide resin mixed with a red pigment was formed into a thickness of 1 μm by using a spin coating method, and a red filter 83 was manufactured using a tenth photomask P10. Similarly, the green filter 85 and the blue filter 86 were produced using the masks P11 and P12. During the production, each filter was baked in nitrogen at 350 ° C. for 60 minutes. Then, the leveling layer 89 was produced using transparent polyimide, also using the spin coat method.

  Thereafter, ITO (indium tin oxide) was formed to a thickness of 0.1 μm on all of these by sputtering, and a common electrode 90 was formed using a fifth photomask 91. This ITO was formed into a film at room temperature to 150 ° C., and was achieved by oxygen at 200 to 300 ° C. or annealing in the atmosphere to obtain a second substrate.

  A polyimide precursor was printed on the substrate using an offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. Thereafter, a known rubbing method was used to modify the polyimide surface, and at least initially, means for aligning liquid crystal molecules in a certain direction was provided.

  Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. A TAB-shaped drive IC and a PCB having a common signal and potential wiring were connected to leads on the substrate, and a polarizing plate was attached to the outside to obtain a transmissive liquid crystal electro-optical device.

  9 and 10 are schematic structural views of the electro-optical device according to this embodiment. The liquid crystal panel 220 obtained in the above process was installed in combination with the rear illumination device 221 in which three cold cathode tubes were arranged. Thereafter, a tuner 223 for receiving TV radio waves was connected to complete the electro-optical device. Compared to the conventional CRT type electro-optical device, the device has a planar shape and can be installed on a wall or the like.

  Next, a peripheral circuit of the liquid crystal electro-optical device for completing the present invention will be described with reference to FIG.

  The drive circuit 352 is connected to the information signal side wires 350 and 351 connected to the matrix circuit of the liquid crystal electro-optical device. The drive circuit 352 has two parts when divided by the drive frequency system. One is a data latch circuit system 353 similar to the conventional driving system, which is mainly composed of a basic clock CLK355 for sequentially transferring data 356, and 1-bit to 12-bit parallel processing is performed. The other one is a component according to the present invention, which comprises a clock 357, a flip-flop circuit 358, and a counter 360 corresponding to the division ratio necessary for gradation display. A counter 360 generates a bipolar pulse generation timing corresponding to the gradation display data sent from the data latch system 353. Further, it has been found that if a ROM table of Δt → sin θ conversion is used between the exit of the latch circuit and the data line 361, the gradation display data can be controlled more finely.

  The features of the present invention are just these portions, and by using two types of drive frequencies, clear digital gradation display is possible without changing the number of frames for screen rewriting. is there. The occurrence of flicker associated with a decrease in the number of frames can be avoided.

  On the other hand, the drive circuit 364 connected to the scanning-side signal lines 363 and 362 controls the sine wave transmitted from the sine wave oscillation circuit 365 by the flip-flop circuit 366 of the clock CLK 367 and adds a selection signal.

  In this way, gradation display is enabled by digitally controlling the timing at which the sine wave on the scanning line side is cut by the bipolar pulse on the information line side.

  For example, when a normal analog gradation display is performed on a liquid crystal electro-optical device in which 76,000 sets of 1920 × 400 dots TFTs are formed in a 300 mm square, there is about ± 10% variation in TFT characteristics. 16 gradation display was the limit. However, when digital gradation display according to the present invention is performed, it is difficult to be affected by variations in characteristics of TFT elements, and therefore, it is possible to display up to 64 gradations, and the color display has a variety of 262,144 colors and subtle colors. Display is realized.

  In this embodiment, a viewfinder for a video camera using a liquid crystal electro-optical device having a diagonal size of 1 inch is manufactured and the present invention is carried out.

  In this embodiment, the viewfinder is configured by forming an element using a high mobility TFT by a low temperature process with a configuration of 387 × 128 pixels. FIG. 14 shows the arrangement of the active elements on the substrate of the liquid crystal display device used in this embodiment, and FIG. 15 shows the manufacturing process showing the A-A ′ and B-B ′ sections in FIG. 14. In FIG. 15A, a silicon oxide film as a blocking layer 51 is formed on a glass 50 that can withstand heat treatment at an inexpensive temperature of 700 ° C. or lower, for example, about 600 ° C., using a magnetron RF (radio frequency) sputtering method. Prepare to thickness. The process conditions were an oxygen 100% atmosphere, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 cm / min.

A silicon film was formed thereon by LPCVD (low pressure vapor phase) method, sputtering method or plasma CVD method. In the case of forming by a reduced pressure vapor phase method, disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) is supplied to a CVD apparatus at 450 to 550 ° C., for example, 530 ° C., which is 100 to 200 ° C. lower than the crystallization temperature. A film was formed. The pressure in the reactor was 30 to 300 Pa. The film formation rate was 50 to 250 cm / min. Boron may be added during film formation at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ using diborane in order to control the threshold voltage (Vth) of PTFT and NTFT to be approximately the same. .

When the sputtering method is used, the back pressure before sputtering is set to 1 × 10 ⁻⁵ Pa or less, the target is single crystal silicon, and the atmosphere is mixed with 20 to 80% hydrogen in argon. For example, 20% argon and 80% hydrogen. The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputtering output was 400 to 800 W, and the pressure was 0.5 Pa.

When a silicon film is formed by plasma CVD, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD apparatus, and a high frequency power of 13.56 MHz was applied to form a film.

The film formed by these methods preferably has oxygen of 5 × 10 ²¹ cm ⁻³ or less. When this oxygen concentration is high, it is difficult to crystallize, and the thermal annealing temperature must be increased or the thermal annealing time must be increased. On the other hand, if the amount is too small, the leak current in the off state increases due to the backlight. Therefore, the range is 4 × 10 ¹⁹ to 4 × 10 ²¹ cm ⁻³ . Hydrogen was 4 × 10 ²⁰ cm ⁻³ , and compared with silicon 4 × 10 ²² cm ⁻³ , it was 1 atomic%.

  After the amorphous silicon film is formed to a thickness of 500 to 5000 mm, for example, 1500 mm by the above method, it is heated at a temperature of 450 to 700 ° C. for 12 to 70 hours in a non-oxide atmosphere, for example, a hydrogen atmosphere. It was held at a temperature of 600 ° C. below. Since an amorphous silicon oxide film is formed on the surface of the substrate under the silicon film, the specific nucleus does not exist in this heat treatment, and the whole is annealed uniformly. That is, it has an amorphous structure during film formation, and hydrogen is merely mixed.

By annealing, the silicon film shifts from an amorphous structure to a highly ordered state, and a part thereof exhibits a crystalline state. In particular, a region having a relatively high order in a state after the film formation of silicon is particularly crystallized and tends to be in a crystalline state. However, since silicon is present between these regions, the silicon atoms pull each other. When measured by laser Raman spectroscopy, a peak shifted to a lower frequency side than the peak 522 cm ⁻¹ of single crystal silicon is observed. The apparent grain size is calculated from the half-value width, which is 50 to 500 mm, like a microcrystal, but in reality, there are many regions with high crystallinity and a cluster structure. A film with a semi-amorphous structure in which silicon is bonded (anchored) can be formed.

As a result, the coating film exhibits a state that it may be said that there is substantially no grain boundary (hereinafter referred to as GB). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which a so-called GB is clearly present. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² / VSec and electron mobility (μe) = 15 to 300 cm ² / VSec are obtained.

On the other hand, when the film is polycrystallized by high-temperature annealing at 900 to 1200 ° C. instead of annealing at the medium temperature as described above, the segregation of impurities in the film occurs due to solid phase growth from the nucleus, resulting in GB. Has a large amount of impurities such as oxygen, carbon, nitrogen, and the mobility in the crystal is large, but it creates a barrier in the GB and inhibits the movement of carriers there. As a result, it is difficult to obtain a mobility of 10 cm ² / Vsec or more. That is, in this embodiment, a silicon semiconductor having a semi-amorphous or semi-crystal structure is used for the above reasons.

  In FIG. 15A, the silicon film is subjected to photoetching using the first photomask (1), and the NTFT region 13 (channel width 20 μm) is placed on the AA ′ cross section side of the drawing and the PTFT region. 22 was prepared on the BB ′ cross section side.

  On this, a silicon oxide film was formed as a gate insulating film to a thickness of 500 to 2000 mm, for example 1000 mm. This was performed under the same conditions as the production of the silicon oxide film as the blocking layer. During the film formation, a small amount of fluorine may be added to fix sodium ions.

Thereafter, a silicon film in which phosphorus enters a concentration of 1 to 5 × 10 ²¹ cm ^{−3 on} the upper side or a multilayer of this silicon film and molybdenum (Mo), tungsten (W), MoSi ₂ or WSi ₂ thereon. A film was formed. This was patterned with the second photomask (2) to obtain FIG. 15 (B). A gate electrode 9 for NTFT and a gate electrode 21 for PTFT were formed. In this example, the channel length for NTFT is 10 μm, the channel length for PTFT is 7 μm, a silicon nitride is formed as a gate electrode with a thickness of 0.2 μm, and molybdenum is formed thereon with a thickness of 0.3 μm. In FIG. 15C, boron is added to the source 18 drain 20 for PTFT by an ion implantation method at a dose of 1 to 5 × 10 ¹⁵ cm ⁻² . Next, as shown in FIG. 15D, a photoresist 61 was formed using a photomask (3). Phosphorus was added at a dose of 1 to 5 × 10 ¹⁵ cm ⁻² by ion implantation as a source 10 and drain 12 for NTFT.

  In addition, when aluminum (Al) is used as a gate electrode material, the self-line method can be applied by patterning the surface with a second photomask (2) and then anodizing the surface. Since the source / drain contact holes can be formed closer to the gate, the TFT characteristics can be further improved by reducing the mobility and the threshold voltage.

Next, heating annealing was performed again at 600 ° C. for 10 to 50 hours. The NTFT source 10 and drain 12 and PTFT source 18 and drain 20 were fabricated as P ⁺ and N ⁺ by activating impurities. Channel formation regions 19 and 11 are formed as semi-amorphous semiconductors under the gate electrodes 21 and 9.

  In this way, a C / TFT can be made without applying a temperature in all steps to 700 ° C. or higher even though it is a self-alignment method. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and this process is extremely suitable for the large-pixel liquid crystal display device of the present invention.

  In this embodiment, the thermal annealing was performed twice in FIGS. 15 (A) and 15 (D). However, the annealing of FIG. 15A may be omitted depending on the required characteristics, and both may be combined with the annealing of FIG. 15D to shorten the manufacturing time. In FIG. 15E, the interlayer insulator 65 is formed as a silicon oxide film by the sputtering method described above. The silicon oxide film may be formed by LPCVD, photo CVD, or atmospheric pressure CVD. For example, it formed in the thickness of 0.2-0.6 micrometer, and the window 66 for electrodes was formed after that using the photomask (4). Further, as shown in FIG. 15F, aluminum is formed on the entire surface by sputtering, and the lead 71 and the contact 72 are formed by using a photomask (5), and then the surface is planarized with an organic resin 69. For example, translucent polyimide resin was applied and formed, and electrode drilling was performed again with a photomask (6).

ITO (Indium Tin Oxide Film) was formed by a sputtering method so that the two TFTs had a complementary configuration and the output end was connected to the electrode of one pixel of the liquid crystal device as a transparent electrode. It was etched with a photomask (7) to form an electrode 17. This ITO was formed at room temperature to 150 ° C., and was achieved by oxygen at 200 to 400 ° C. or annealing in the atmosphere. In this manner, NTFT 13, PTFT 22, and transparent conductive film electrode 17 were fabricated on the same glass substrate 50. The TFT obtained has PTFT mobility of 20 (cm ² / Vs), Vth of −5.9 (V), NTFT mobility of 40 (cm ² / Vs), and Vth of 5 0.0 (V).

  One substrate for a liquid crystal device was produced according to the method as described above. FIG. 14 shows the arrangement of electrodes and the like of this liquid crystal display device. NTFT 13 and PTFT 22 are provided at the intersection of first signal line 3 and second signal line 4. A matrix configuration using such a C / TFT was provided. The NTFT 13 is connected to the second signal line 4 through a contact at the input end of the drain 10, and the gate 9 is connected to the signal line 3 in which a multilayer wiring is formed. The output terminal of the source 12 is connected to the electrode 17 of the pixel through a contact.

  On the other hand, the PTFT 22 has an input terminal of the drain 20 connected to the second signal line 4 via a contact, a gate 21 connected to the signal line 3, and an output terminal of the source 18 connected to the pixel electrode like the NTFT via a contact. 17 is connected. This embodiment is configured by repeating such a structure left and right and up and down.

  Next, as a second substrate, ITO (indium tin oxide film) was also formed by sputtering on a blue plate glass on which a 2000-nm-thick silicon oxide film was laminated by sputtering. This ITO was formed at room temperature to 150 ° C., and was achieved by oxygen at 200 to 400 ° C. or annealing in the atmosphere. Further, a color filter using the same method as in [Example 1] was formed on this substrate to obtain a second substrate.

  A polyimide precursor was printed on the substrate using an offset method, and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. Thereafter, a known rubbing method was used to modify the polyimide surface, and at least in the initial stage, means for aligning liquid crystal molecules in a certain direction was provided to form first and second substrates.

  Thereafter, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. Since the pitch of the leads on the substrate is as fine as 46 μm, the connection was made using the COG method. In this embodiment, a method is used in which gold bumps provided on an IC chip are connected with an epoxy-based silver palladium resin, and the IC chip and the substrate are filled and fixed with an epoxy-modified acrylic resin for the purpose of fixing and sealing. It was. Thereafter, a polarizing plate was attached to the outside to obtain a transmissive liquid crystal display device.

  FIG. 16 shows the drive waveforms used in this example. A ramp waveform was used instead of the sine wave used in Example 1. The ramp wave has an advantage in that the structure is simple and the conversion from the gradation data to Δt is easy.

  FIG. 17 shows a configuration diagram of the viewfinder according to the present embodiment. A liquid crystal electro-optical device 370 manufactured by the above method and a cold cathode tube 371 having planar light emission were used.

  For example, when normal analog gradation display is performed on a liquid crystal electro-optical device in which 49,152 pairs of TFTs of 384 × 128 dots are formed in a 50 mm square (36 multi-sided from a 300 mm square substrate), Since there is about ± 10% variation in characteristics, 16 gradation display is the limit. However, when digital gradation display according to the present invention is performed, it is difficult to be affected by variations in characteristics of TFT elements, and therefore, it is possible to display up to 128 gradations, and in color display, there are a wide variety of 2,097 and 152 colors. Color display is realized.

  In this embodiment, a projection type image display apparatus as shown in FIG.

  In this embodiment, the projection unit for the projection type image display device is assembled using three liquid crystal electro-optical devices 201. Each of them has a configuration of 640 × 480 dots, and 307,200 pixels were manufactured in a diagonal of 4 inches. The size per pixel was 127 μm square.

  As a configuration of the projection type image display device, the liquid crystal electro-optical device 201 is divided and installed for the three primary colors red, green, and blue, and the red filter 202, the green filter 203, the blue filter 204, and the reflection A plate 205, prism mirrors 206 and 207, a 150 W metal halide light source 208, and a focusing optical system 209 are included.

  The substrate of the liquid crystal electro-optical device used in the electro-optical device of this example was a substrate having a matrix circuit with a C / MOS structure using the same process as that manufactured in [Example 2].

  FIG. 19 shows an outline of the structure. A mixture of fumaric acid polymer resin and nematic liquid crystal dissolved in xylene as a common solvent at a ratio of 65:35 was formed on the substrate 210 to a thickness of 10 μm by using a die-cast method. Thereafter, the solvent was removed in a nitrogen atmosphere at 120 ° C. in 180 minutes to form a liquid crystal dispersion layer 211. In this case, it was found that the takt time can be shortened by reducing the pressure slightly below the atmospheric pressure.

  Thereafter, ITO (indium tin oxide film) was formed by sputtering to obtain the counter electrode 212. The ITO was formed at room temperature to 150 ° C. Thereafter, a translucent silicon resin was applied in a thickness of 30 μm using a printing method and baked at 100 ° C. for 30 minutes to obtain a liquid crystal electro-optical device.

  The functional configuration of the driving IC used in this example is shown in FIG. The configuration on the information electrode side is the same as in [Example 1]. The driving circuit 400 connected to the scanning-side wirings 406 and 407 controls the ramp wave transmitted from the ramp wave oscillation circuit 405 by the flip-flop circuits 403 and 404 of the clock CLK 408 and adds a selection signal.

  In this way, gradation display is enabled by digitally controlling the timing at which the scanning line side ramp wave is cut off by the information line side bipolar pulse.

  For example, when a normal analog gradation display is performed on a liquid crystal electro-optical device in which 307,200 TFTs of 640 × 480 dots are formed in a 300 mm square, there is about ± 10% variation in TFT characteristics. 16 gradation display was the limit. However, when digital gradation display according to the present invention is performed, it is difficult to be affected by variations in characteristics of TFT elements, and therefore, it is possible to display up to 256 gradations, and in color display, there are a wide variety of 16,777,216 colors. Display of various colors.

  When projecting software such as TV images, for example, even the “rock” of the same color has a slightly different hue due to the light that falls on the minute depressions. When a display close to natural colors is to be displayed, it is difficult to express with 16 gradations, which is not suitable for expressing these subtle depressions. The gradation display according to the present invention makes it possible to add these minute color tone changes.

  This liquid crystal electro-optic can be used not only for the front type projection television shown in FIG. 18, but also for the rear type projection television.

  In this embodiment, a portable computer electro-optical device is manufactured using a reflective liquid crystal display device as shown in FIG.

  As the first substrate used in this example, a substrate prepared in the same process as [Example 1] was used. A mixture of nematic liquid crystal mixed with 15% fumaric acid polymer resin and black pigment dissolved in xylene which is a common solvent at a ratio of 65:35 on the substrate 210 with a thickness of 10 μm using a die casting method. Then, the solvent was removed in a nitrogen atmosphere at 120 ° C. for 180 minutes to form a liquid crystal dispersion layer 211.

  Here, since a black pigment was used, a flat display, which was difficult with a dispersive liquid crystal display, was black when light was scattered (when no electric field was applied) and white when transmitted (when an electric field was applied). It is possible to display characters written on paper.

  Further, as a reverse structure, it is also possible to express white at the time of scattering and black at the time of transmission without mixing black pigment. However, in this case, it is necessary to make the back side shown below black. This can also be displayed like letters written on paper.

  Thereafter, ITO (indium tin oxide film) was formed by sputtering to obtain the counter electrode 212. The ITO was formed at room temperature to 150 ° C. Thereafter, using a printing method, a white silicone resin was applied to a thickness of 55 μm and baked at 100 ° C. for 90 minutes to obtain a liquid crystal electro-optical device.

2 shows a driving waveform according to the present invention. The electro-optical characteristics of nematic liquid crystal are shown. The current-voltage characteristics of a TFT made of polysilicon and amorphous silicon are shown. 2 shows a matrix configuration according to the present invention. 1 shows a matrix circuit according to an embodiment. Example 1 The plane structure of the element by an Example is shown. The process of TFT by an Example is shown. The process of TFT by an Example is shown. The structure of the liquid crystal display device (television) by an Example is shown. The structure of the liquid crystal display device (television) by an Example is shown. 1 shows a system configuration of a drive circuit according to an embodiment. The frame gradation display by a prior art example is shown. The process of the color filter by an Example is shown. The plane structure of the element by an Example is shown. (Example 2) The process of TFT by an Example is shown. 4 shows another driving waveform according to the present invention. The structure of the viewfinder by an Example is shown. The structure of the front type projection television by an Example is shown. (Example 3) 1 shows a liquid crystal electro-optical device according to an embodiment. 1 shows a system configuration of a drive circuit according to an embodiment. The structure of the portable personal computer by an Example is shown. (Example 4)

Claims (8)

A television including an electro-optical device and a tuner that receives television radio waves,
The electro-optical device includes:
A glass substrate;
A silicon oxide film on the glass substrate;
An active layer formed on the silicon oxide film and having a channel formation region, a source region, and a drain region;
A gate insulating film on the active layer;
A gate electrode on the gate insulating film;
An interlayer insulator on the gate electrode;
A first electrode formed on the interlayer insulator and connected to the drain region; and a second electrode connected to the source region;
A planarization film formed on the first electrode and the second electrode;
A pixel electrode made of a transparent conductive film formed on the planarization film and connected to the first electrode;
The drain electrode is connected to the drain region through a first contact hole formed in the interlayer insulator, and the pixel electrode is connected through the second contact hole formed in the planarization film. Connected to the first electrode;
The television set characterized in that the second contact hole does not overlap the first contact hole. A television including an electro-optical device and a tuner that receives television radio waves,
The electro-optical device includes:
A glass substrate;
A silicon oxide film on the glass substrate;
An active layer formed on the silicon oxide film and having a channel formation region, a source region, and a drain region;
A gate insulating film on the active layer;
A gate electrode on the gate insulating film;
An interlayer insulator on the gate electrode;
A first electrode formed on the interlayer insulator and connected to the drain region; and a second electrode connected to the source region;
A planarization film formed on the first electrode and the second electrode;
A pixel electrode made of a transparent conductive film formed on the planarization film and connected to the first electrode;
The drain electrode is connected to the drain region through a first contact hole formed in the interlayer insulator, and the pixel electrode is connected through the second contact hole formed in the planarization film. Connected to the first electrode;
The television set, wherein the second contact hole has a curved surface that does not overlap the first contact hole but extends from an upper surface of the planarization film to an inner surface of the second contact hole. A computer equipped with an electro-optical device,
The electro-optical device includes:
A glass substrate;
A silicon oxide film on the glass substrate;
An active layer formed on the silicon oxide film and having a channel formation region, a source region, and a drain region;
A gate insulating film on the active layer;
A gate electrode on the gate insulating film;
An interlayer insulator on the gate electrode;
A first electrode formed on the interlayer insulator and connected to the drain region; and a second electrode connected to the source region;
A planarization film formed on the first electrode and the second electrode;
A pixel electrode made of a transparent conductive film formed on the planarization film and connected to the first electrode;
The drain electrode is connected to the drain region through a first contact hole formed in the interlayer insulator, and the pixel electrode is connected through the second contact hole formed in the planarization film. Connected to the first electrode;
The computer according to claim 1, wherein the second contact hole does not overlap the first contact hole. A computer equipped with an electro-optical device,
The electro-optical device includes:
A glass substrate;
A silicon oxide film on the glass substrate;
An active layer formed on the silicon oxide film and having a channel formation region, a source region, and a drain region;
A gate insulating film on the active layer;
A gate electrode on the gate insulating film;
An interlayer insulator on the gate electrode;
A first electrode formed on the interlayer insulator and connected to the drain region; and a second electrode connected to the source region;
A planarization film formed on the first electrode and the second electrode;
A pixel electrode made of a transparent conductive film formed on the planarization film and connected to the first electrode;
The drain electrode is connected to the drain region through a first contact hole formed in the interlayer insulator, and the pixel electrode is connected through the second contact hole formed in the planarization film. Connected to the first electrode;
The computer according to claim 1, wherein the second contact hole has a curved surface that does not overlap the first contact hole but extends from an upper surface of the planarization film to an inner surface of the second contact hole.   3. The television according to claim 1, wherein the interlayer insulator is a silicon oxide film.   3. The television according to claim 1, wherein the planarizing film is an organic resin film. According to claim 3 or 4, the computer, wherein the interlayer insulator is a silicon oxide film. According to claim 3 or 4, the computer, wherein the planarization layer is an organic resin film.

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