JP3877095B2 - Semiconductor device - Google Patents

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JP3877095B2
JP3877095B2 JP26273997A JP26273997A JP3877095B2 JP 3877095 B2 JP3877095 B2 JP 3877095B2 JP 26273997 A JP26273997 A JP 26273997A JP 26273997 A JP26273997 A JP 26273997A JP 3877095 B2 JP3877095 B2 JP 3877095B2
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circuit pattern
conductor circuit
lead
semiconductor device
conductor
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JPH1187560A (en
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勝房 藤田
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Mitsui High Tech Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、絶縁性部材に導体回路を積層したインターポーザを構成部材とするＣＳＰ（チップ・スケール・パッケージ）型の半導体装置に係る。詳細には、集積回路素子の主面とその反対面にそれぞれのインターポーザを備えたＣＳＰ型の半導体装置の構造に関する。
【０００２】
【従来の技術】
情報処理機器の高速化、高機能化に伴い、半導体装置の作動に超高周波を用いるようになってきている。そのためポリイミド基板に微細な間隔で形成された導体回路パターンの複数のリード（電送路）を超高周波信号が電送される際に、隣接する前記リードに信号が漏れてしまうクロストーク現象を生じるという問題があった。
【０００３】
このような問題点を解決するために、絶縁性基板の一例であるポリイミドテープ基板に形成された導体回路パターンの反対面に、導電性の金属薄板からなる支持基板を固着し、この導体回路パターンの所定の前記リードと前記支持基板とを貫通孔を介して接続し、放熱及び接地機能を備えた半導体装置が提案されている（特願９−２２１６１参照）。
【０００４】
この方式の半導体装置は、表面に複数の電極パッドを設けた半導体素子の主面側に接合されており、絶縁性部材層の前記電極パッド面側には、複数のリードが配列された第１の導体回路パターン層を、他面側には、接地・放熱機能を備えた支持基板層を備え、さらに、前記リードの一端部には、前記集積回路素子の電極パッドに電気的に接続されるリードボンデイングパッドを、前記リードの他端部には、円形皿状にディプレスされた半導体素子搭載部の周辺にファン・アウト状に配置され、外部導通回路を形成する外部接続端子ランドを設けたインターポーザと、前記インターポーザの内部接続端子パッドと半導体素子の電極パッドとをリード・ボンディング（ワイヤレス・ボンデング方式）で接続された半導体素子と、前記半導体素子搭載部に封止樹脂を充填して前記半導体素子を封止する封止樹脂部と、第１の導体回路パターン層の一端部を被覆し、前記外部接続端子ランドに対応する複数のビア・ホールを設けたソルダ・レジスト層と、前記ビア・ホールを介して外部接続端子ランドに接続され、外部配線パターン側に突出した半田ボール叉はバンプから成る外部接続端子とを具備した構成とされるものである。
【０００５】
上記の半導体装置にあっては、導電性プレーン層を有するインターポーザを備えた構成としているので、半導体装置の放熱性、電気特性（寄生電流の拡散）の向上の要求には対応できるが、外部接続端子（半田ボールまたはバンプ）が集積回路素子搭載部の外周に配置されるファン・アウト状のエリア・アレイ構造であるため小型・軽量化に対応することができないという問題があった。
【０００６】
近来、前記の問題点を解決する為に、導体回路パターンが集積回路素子搭載領域範囲に引き回され外部接続端子がファン・イン状のエリア・アレイ構造のＣＳＰ（チップ・スケール・パッケージ）型の半導体装置が提案されている。
【０００７】
【発明が解決しようとする課題】
しかしながら、この種のＣＳＰ型の半導体装置では、外部接続端子（半田ボールまたはバンプ）が集積回路素子搭載部領域範囲に配置されるファン・イン状のエリア・アレイ構造であるため、半導体装置の小型・軽量化に対応することはできるが、外部接続端子ランド間に引き回すリードの本数が制限されるので、多端子化に対応することのできないという問題があった。
本発明は、上記の実情に鑑みてなされたもので、半導体装置の電気的特性を向上させると共に、半導体装置の小型・軽量化の要求に対応でき、且つ多端子化の要求にも対応することのできるＣＳＰ型の半導体装置を提供することにある。
【０００８】
【課題を解決するための手段】
本発明は上記の目的を達成する請求項１記載の半導体装置は、第１の絶縁性部材の表裏面に第１の導体回路パターン及び第１のリードを有するとともに該第１のリードのうちの所定のリードを除いて第１の外枠と分離した第２の導体回路パターンを備え、しかも、前記第１の絶縁性部材に設けられたスルーホールを介して第１及び第２の導体回路パターンの第１の導通部が形成され、さらに、その中央部に半導体素子搭載領域を設けた第１のインターポーザと、前記第１のインターポーザの半導体素子搭載領域に固着され、前記第２の導体回路パターンの各リードのリードボンディング端子とは、リードボンディングにより、それぞれ電気的に接続された半導体素子と、前記半導体素子の裏面に固着されており、第２の絶縁性部材の表裏に第２のリードを有するとともに該第２のリードのうちの所定のリードを除いて第２の外枠と分離した第３の導体回路パターン及び第３のリードを有するとともに該第３のリードのうちの所定のリードを除いて第３の外枠と分離した第４の導体回路パターンを備え、しかも、第２の絶縁性部材に設けられた貫通孔を介して第２導体回路パターンの接地回路パターンと第３の導体回路パターンの接地回路パターン及び第４の導体回路パターンの接地回路パターンとの間に電気的導通回路を形成する第２の導通部と第２の絶縁性部材に設けられたスルーホールを介して第３の導体回路パターンの各リードの第１の外部接続ランドと所定の外部接続端子との間に電気的導通回路を形成する第３の導通部と第２の絶縁性部材に設けられたスルーホールを介して第３及び第４の導体回路パターンの接地端子の第４の導通部とが形成された第２のインターポーザと、前記半導体素子、前記第２の導通部を封止する封止樹脂と、第４の導体回路パターンの各リードの第２の外部接続端子ランド及び第３の導通部、さらには、第４の導体回路パターンの外枠に設けた第４の接地端子を露出する開口部を備え、第４の導体回路パターンを被覆するカバーレジストと、前記カバーレジストの開口部を介して接続され、外部配線基板側に突出した外部接続端子とを具備して成る構成とされている。
【０００９】
請求項２記載の半導体装置は、請求項１記載の半導体装置にあっては、前記第１の導体回路パターンは、第２の導体パターンを覆う熱的、電氣的伝導性の良好な金属から成り、その表面に耐食性の金属めつき層を設け接地・放熱基板を設けた構成とされている。
【００１０】
請求項３記載の半導体装置は、請求項１記載の半導体装置にあっては、前記第１の導通部及び第４の導通部は、前記第２の導体回路パターンの第１の外枠、前記第３の導体回路パターンの第２の外枠、及び前記第４の導体回路パターンの第３の外枠それぞれの外枠の四隅に形成された接地端子に対応し、第１の導体回路パターンと外部接続端子との間に接地回路を形成する構成とされている。
【００１１】
請求項４記載の半導体装置は、請求項１記載の半導体装置にあっては、前記第３の導通部は、半導体素子搭載部領域範囲にファン・インのエリア・アレイ状に形成され、電源又は信号用のいずれか一方の前記外部接続端子と前記半導体素子との間に電源又は信号回路を形成する構成とされている。
【００１２】
請求項５記載の半導体装置は、請求項１記載の半導体装置にあっては、前記第２の導通部は、前記半導体素子搭載部領域に近接して形成され、前記半導体素子と第２の導電回路パターンとの間の電源及び信号用回路のいずれか一方を第３の導体回路パターンとの間に、他方を第４の導体回路パターンとの間に分岐して導通回路を形成する構成とされている。
【００１３】
請求項６記載の半導体装置は、請求項１〜５記載のいずれか１項記載の半導体装置にあっては、前記第２の導体回路パターンの第１の外枠、前記第３の導体回路パターンの第２の外枠及び前記第４の導体回路パターンの第３の外枠は、接地回路を形成する共通接地端子であるとされている。請求項７記載の半導体装置は、請求項１〜６記載のいずれか１項記載の半導体装置にあっては、前記第１、第２、第３及び第４の導体回路パターンは、金属薄板からプレス加工又はエッチング加工で形成された所要形状のインナー・リードフレームを用いた構成とされている。
【００１４】
【発明の実施の形態】
続いて、添付した図面に基づき本発明の実施の態様の一例について詳細に説明する。ここで、図１は本発明の一実施の態様に係る半導体装置の構成を示す断面図、図２は本発明の一実施の態様に係る半導体装置の外部接続端子側を示す平面図、図３は本発明の一実施の態様に係る第３の導体回路パターンを示す平面図、図４は本発明の実施の態様の一例に係る第２のインターポーザの構成を示す断面図、図５は本発明の実施の態様の一例に係る第４の導体回路パターンを示す平面図である。
【００１５】
図１及び２に示すように、本発明の一実施の形態に係る半導体装置１０は、半導体素子１１の表裏面に、第１及び第２の導体回路パターン１２、１３がそれぞれ形成された第１のインターポーザ１４と、第３及び第４の導体回路パターン１５、１６が形成された第２のインタポーザ１７とが、第１及び第２の絶縁性接着剤１８、１９の一例である液状エラストマ樹脂１８ａ、１９ａを介して固着されている。さらに、前記半導体素子１１と外部配線基板２０との電気的な導通回路を形成するファン・インのエリア・アレイ状に突出した構造の複数の外部接続端子２１の一例であるソルダ・ボール２１ａを有している。
【００１６】
図１に示すように、前記第１のインタポーザ１４は、第１の絶縁性部材２２の一例である第１のポリイミド樹脂テープ２２ａが使用され、その表側には導電性部材の一例である耐食性金属の一例である表面層にＮｉめっき層を有する銅箔材から成る第１の導体回路パターン１２が形成されている。そして第１のポリイミド樹脂テープ２２ａには、複数のスルー・ホールが形成され、第１の導体回路パターン１２の第１の接地端子２４と電気的導通回路を形成し、第１の導体回路パターン１２に接地・放熱の機能を付加する電気的な第１の導通部２３を有している。
【００１７】
一方、前記第１のポリイミド樹脂テープ２２ａの裏面側には、図１に示すように、中央の半導体素子搭載領域２５の周囲には第２の導体回路パターン１３が形成されている。そして、前記第２の導体回路パターン１３には、多数の第１のリード２６を有し、各リード２６の一端部には、前記半導体素子１１と電気的に接合するリードボンディング端子２７を、その他端部には、第２のインタポーザと電気的に接続する第１のリード接続端子２８を有している。さらに、その周縁には、所要数の第２の接地端子２９（本実施の態様では四隅に設けている）を設けている。そして各第１のリード２６の所定のリード２６ａを除いて分離した第１の外枠３０を備えている。しかも、前記第２の接地端子２９は前記第１の導通部２３に対応している。
【００１８】
このように第１のインターポーザ１４を構成することによって、第１のポリイミド樹脂テープ２２ａに設けた所要数のスルー・ホールを介して第１の導体回路パターン１２の第１の接地端子２４と第２の導体回路パターン１３の第２の接地端子２９との間に接地回路を形成している。そして、この接地回路によって第１の導体回路パターン１２を接地・放熱板として機能させことができると共に、前記第１の外枠３０を接地用の共用端子として用いることもできる。
【００１９】
なほ、この実施の形態では、第１の絶縁性部材２２としてポリイミド樹脂テープを使用したが、ポリイミド樹脂フィルムやその他の熱に強いシート又はテープであれば使用可能である。
【００２０】
図４に示すように、前記第２のインタポーザ１７は、第２の絶縁性部材３１の一例である第２のポリイミド樹脂テープ３１ａが使用され、その表裏面に、図３及び図５に示す、第３及び第４の導体回路パターン１５、１６を備えている。
【００２１】
図３に示すように、第３の導体回路パターン１５は、内側に向かって伸びる多数の第２のリード３３を有する。そして、前記各リード３３の一端部には、それぞれ第１の外部接続端子ランド３４を設け、その他端部には、それぞれ第２のリード接続端子３５を設けている。さらに、その周縁には、所要数の第３の接地端子３６（本実施の態様では回路パターンの四隅）を設けている。そして、前記各第２のリード３３の所定のリード３３ａを除いて分離した第２の外枠３７を備えている。しかも、前記第３の接地端子３６は導電性接着剤層Ａを介して前記第２の接地端子２９に接続するようにしている。
【００２２】
一方、図５に示すように、前記第４の導体回路パターン１６は、内側に向かって伸びる多数の第３のリード３８を有する。そして、前記各リード３８の一端部には、それぞれ第２の外部接続端子ランド３９を設け、その他端部には、第３のリード接続端子４０を設けている。さらに、その周縁には、所要数の第４の接地端子４１（本実施の態様では回路パターンの四隅）が設けられている。そして、前記各第３のリード３８の所定のリード３８ａを除いて前記リードが分離した第３の外枠４２を備えている。しかも、前記第４の接地端子４１は前記第３の接地端子３６に対応している。
【００２３】
図３及び図５に示すように、第２のポリイミド樹脂テープ３１ａの周囲には、前記第３のリード接続端子４０が露出した所定数の貫通孔（本実施の態様では斜線で示す４個の貫通孔）３２が形成されている。そして、この部分で前記各第１のリード接続端子２８と前記各第３の及び第４のリード接続端子３５、４０とがそれぞれ対応したリード接続端子が重なりあって、接合の一例である超音波接合によって電気的に接合された第２の導通部２３ａ（図１、図４参照）を有している。ここで、超音波接合に変えて導電性接着剤を用いても同様な結果を得ることができる。
【００２４】
さらに、第２のポリイミド樹脂テープ３１ａには、前記第３の導体回路パターン１５の第１の外部接続端子ランド３４に対応するスルー・ホールが形成され、この部分で外部接続端子２１の所定の端子（本実施の態様では信号のＩ／Ｏ端子）と電気的導通回路を形成する第３の導通部２３ｂを有している。
【００２５】
また、第２のポリイミド樹脂テープ３１ａには、前記第３及び第４の接地端子３６、４１に対応するスルー・ホールが形成され、この部分で前記第３の接地端子３６と第４の接地端子４１との間に電気的導通回路を形成する第４の導通部２３ｃを有している。
【００２６】
そして、前記第１の導通部２３及び前記第４の導通部２３ｃとこれに接続する第１、第２、第３、第４の接地端子と導電性接着剤とによって前記外部接続端子の所定の端子（本実施の態様では図２に示す外枠の四隅に形成された外部接続接地端子）と第１の導体回路パターン１２との間に電気的導通回路を形成して第１の導体回路パターン１２に接地的機能を付加している。
【００２７】
上記のように構成された第１のインターポーザ及び第２のインターポーザを構成部材とする半導体装置１０は、前記第１のインターポーザ１４の半導体素子搭載領域２５には、半導体素子１１が第１の絶縁性接着剤１８の一例である第１の液状エラストマ樹脂１８ａを用いて接合されると共に、前記半導体素子１１の各電極パッドと前記第１のリード２６のリードボンデング端子２７とはリード・ボンディングにより接続されている。さらに、半導体素子１１の裏面には、前記第２のインターポーザ１７が第２の絶縁性接着剤１９の一例である第２の液状エラストマ樹脂１９ａを用いて接合されると共に、前記各第１のリード接続端子２８と前記各第３の及び第４のリード接続端子３５、４０とがそれぞれ対応したリード接続端子に超音波接合によって電気的に接合（図１、図４参照）されている。そして、前記半導体素子、前記第１、第２及び第３のリード接続端子の第２の導通部２３ａを封止樹脂４３の一例である封止用エラストマ樹脂で樹脂封止され、さらに、図１、図４及び図５に示すように、前記第４の導体パターン１６を、前記第４の接地端子ランド４１、第２の外部接続端子ランド３９及び前記第３の導通部２３ｂを露出する開口部４４を設けた絶縁性のカバー・レジスト４５で被覆保護すると共に、該開口部４４を介して前記カバー・レジスト側に突出する外部接続端子２１を設けた図１に示すように、外周部に接地用の外部接続端子とファン・インのエリア・アレイ状の外部接続端子を備えた半導体装置が形成される。ここで、前記カバー・レジスト４５は、液状レジストをシルク印刷法又はフィルム・フォトレジスト露光法を用いて形成されたものであってもよい。
【００２８】
以上のような構成となっているので、半導体素子と外部接続端子の結合は、第２の導通部２３ａで第２の導体回路パターン及び第３の導体回路パターンに適切に分岐され、内側方向に回路の変更を行うことができる（図１、図２、図３、図４、図５参照）。そして、前記半導体素子１１と外部接続端子２１との間に各導通部を介し、適切な組合せの電気的導通回路を形成することができる。
【００２９】
前記実施の態様では、前記半導体素子搭載領域は第１の導体回路パターン側に突出するようにデイプレスして素子搭載キャビティを形成すると共に、前記第１のリードのリードボンディング端子が前記キャビティ側に突出するように再ディプレスした構成としているが（図１参照）、再ディプレスを形成しない構成とすることもできる。
【００３０】
さらに、第２のインタポーザは、第２の絶縁性部材の表裏面に第１及び第２の導体回路パターンを形成した構成としているが、絶縁性部材の片面に第１の導体回路パターンを形成し、他の絶縁性部材に第２の導体回路パターンを形成してそれぞれを絶縁性接着剤で接合した構成とすることもできる。この構成とすれば導体回路パターンの形成加工が容易になる。
【００３１】
さらに、前記第１、第２、第３及び第４の導体回路パターンを金属薄板からプレス加工又はエッチング加工で形成された所要形状のそれぞれのインナー・リードフレームを用いた構成としているので、導体回路パターンの形成加工が容易になり、半導体装置の製造コストの低減が可能となる。
【００３２】
さらに、前記第１のリード接続端子、第２及び第３のリード接続端子の第１の導通部を形成しているので、第２及び第３のリード接続端子を内側方向に延在したエリア・アレイ状の配置に形成することができる。これによって多端子化の対応がより容易になる。
【００３３】
【発明の効果】
請求項１、２記載の半導体装置は、半導体素子の信号のＩ／Ｏパッド、電源パッド及び接地パッドと外部接続端子との導通回路が、半導体素子搭載領域に隣接して設けた導通部で、第３及び第４の導体回路パターンに分岐し、外部接続端子ランドがファン・インのエリア・アレイ状に配置された第２のインターポーザを有する構成とされているので、半導体素子の外形サイズに近いパッケージサイズに小型化・軽量化することができると共に、半導体装置の多端子化に対応することができる。
【００３４】
請求項２記載の半導体装置は、請求項１記載の半導体装置にあっては、前記第１の導体回路パターンには、熱的、電氣的伝導性の良好な金属から成る接地・放熱の機能を有する構成としているので、半導体装置のクロストーク現象を防ぎ電気特性を向上させることができる。
【００３５】
請求項３記載の半導体装置は、請求項１記載の半導体装置にあっては、第２、第３、第４の導体回路の各外枠に第１の導体回路パターンと外部接続端子との間に接地回路を形成する接地端子を設けているので、第１又は第２の導体回路パターンのいずれか一方を接地回路又は／及び電源回路とし機能させることができ、Ｉ／Ｏ信号回路と電源回路とが分離され、半導体装置の電気特性をより向上させることができる。
【００３６】
請求項４記載の半導体装置は、請求項１記載の半導体装置にあっては、前記第３の導通部は、半導体素子搭載部領域範囲にファン・インのエリア・アレイ状に形成され、電源又は信号用のいずれか一方の前記外部接続端子と前記半導体素子との間に電源又は信号回路を形成する構成とされているので、半導体装置の小型化と多端子化とにさらに容易に対応することができるとともに電氣的特性をいっそう向上させることができる。
【００３７】
請求項５記載の半導体装置は、請求項１記載の半導体装置にあっては、前記第４の導通部は、前記半導体素子搭載部領域に近接して形成され、前記半導体素子と第２の導電回路パターンとの間の電源及び信号用回路のいずれか一方を第３の導体回路パターンとの間に、他方を第４の導体回路パターンとの間に回路を変換する分岐を形成する構成とされているので、外部接続端子間の間隔が短縮され、多端子化が容易に実現することができる。
【００３８】
請求項６記載の半導体装置は、請求項１〜４記載のいずれか１項記載の半導体装置にあっては、前記第２、第３及び第４の導体回路パターンの前記外枠は、接地回路を形成する共通接地端子である構成とされているので、第１、第２及び第３の導体回路パターンの外枠を接地共通回路とすることができ、半導体素子の回路設計の自由度を向上させることができる。
【００３９】
請求項７記載の半導体装置は、請求項１〜６記載のいずれか１項記載の半導体装置にあっては、前記第１、第２、第３及び第４の導体回路パターンは、金属薄板からプレス加工又はエッチング加工で形成された所要形状のインナー・リードフレームを用いた構成とされているので、導体回路パターンの形成が容易になり、製造コストを低減することができ、低価格の半導体装置の提供が可能となる。
【図面の簡単な説明】
【図１】本発明の実施の態様の一例に係る半導体装置の構成を示す断面図である。
【図２】本発明の実施の態様の一例に係る半導体装置の外部接続端子側を示す平面図である。
【図３】本発明の実施の態様の一例に係る半導体装置の第３の導体回路パターンを示す平面図である。
【図４】本発明の実施の態様の一例に係る半導体装置の第２のインターポーザの構成を示す断面図である。
【図５】本発明の実施の態様の一例に係る半導体装置の第４の導体回路パターンを示す平面図である。
【符号の説明】
１０ 半導体装置
１１ 半導体素子
１２ 第１の導体回路パターン
１３ 第２の導体回路パターン
１４ 第１のインターポーザ
１５ 第３の導体回路パターン
１６ 第４の導体回路パターン
１７ 第２のインタポーザ
１８ 第１の絶縁性接着剤
１８ａ 液状エラストマ樹脂
１９ 第２の絶縁性接着剤
１９ａ 液状エラストマ樹脂
２０ 外部配線基板
２１ 外部接続端子
２１ａ ソルダ・ボール
２２ 第１の絶縁性部材
２２ａ 第１のポリイミド樹脂テープ
２３ 第１の導通部
２３ａ 第２の導通部
２３ｂ 第３の導通部
２３ｃ 第４の導通部
２４ 第１の接地端子
２５ 半導体素子搭載領域
２６ 第１のリード
２６ａ リード
２７ リードボンディング端子
２８ 第１のリード接続端子
２９ 第２の接地端子
３０ 第１の外枠
３１ 第２の絶縁性部材
３１ａ 第２のポリイミド樹脂テープ
３２ 貫通孔
３３ 第２のリード
３３ａ リード
３４ 第１の外部接続端子ランド
３５ 第２のリード接続端子
３６ 第３の接地端子
３７ 第２の外枠
３８ 第３のリード
３８ａ リード
３９ 第２の外部接続端子ランド
４０ 第３のリード接続端子
４１ 第４の接地端子
４２ 第３の外枠
４３ 封止樹脂
４４ 開口部
４５ カバー・レジスト[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a CSP (chip scale package) type semiconductor device having an interposer in which a conductor circuit is laminated on an insulating member as a constituent member. Specifically, the present invention relates to a structure of a CSP type semiconductor device provided with an interposer on the main surface of an integrated circuit element and on the opposite surface thereof.
[0002]
[Prior art]
With the increase in speed and functionality of information processing equipment, ultra-high frequencies have been used for the operation of semiconductor devices. Therefore, when a high frequency signal is transmitted through a plurality of leads (electric transmission paths) of a conductor circuit pattern formed on a polyimide substrate at fine intervals, a crosstalk phenomenon occurs in which a signal leaks to the adjacent leads. was there.
[0003]
In order to solve such problems, a support substrate made of a conductive metal thin plate is fixed to the opposite surface of the conductor circuit pattern formed on a polyimide tape substrate which is an example of an insulating substrate, and this conductor circuit pattern is fixed. A semiconductor device has been proposed in which the predetermined lead and the support substrate are connected through a through hole and provided with a heat dissipation and grounding function (see Japanese Patent Application No. 9-22161).
[0004]
This type of semiconductor device is bonded to the main surface side of a semiconductor element provided with a plurality of electrode pads on the surface, and a plurality of leads are arranged on the electrode pad surface side of the insulating member layer. The conductive circuit pattern layer is provided with a support substrate layer having a grounding / heat dissipating function on the other surface side, and one end of the lead is electrically connected to the electrode pad of the integrated circuit element. A lead bonding pad is provided at the other end of the lead in the form of a fan-out around the semiconductor element mounting portion depressed in a circular dish shape, and an external connection terminal land forming an external conduction circuit is provided. An interposer, a semiconductor element in which an internal connection terminal pad of the interposer and an electrode pad of the semiconductor element are connected by lead bonding (wireless bonding method); A plurality of via holes corresponding to the external connection terminal lands, covering a sealing resin portion for sealing the semiconductor element by filling a sealing resin in the portion, and covering one end portion of the first conductor circuit pattern layer The solder resist layer provided and the external connection terminal land connected to the external connection terminal land through the via hole, and the external connection terminal made of a solder ball or bump projecting to the external wiring pattern side are provided. is there.
[0005]
The semiconductor device described above has an interposer having a conductive plane layer, so that it can meet the demand for improvement in heat dissipation and electrical characteristics (diffusion of parasitic current) of the semiconductor device, but external connection Since the terminals (solder balls or bumps) have a fan-out area array structure arranged on the outer periphery of the integrated circuit element mounting portion, there is a problem that it is impossible to cope with a reduction in size and weight.
[0006]
Recently, in order to solve the above-mentioned problem, a CSP (chip scale package) type in which the conductor circuit pattern is routed to the integrated circuit element mounting region range and the external connection terminal is a fan-in area array structure. Semiconductor devices have been proposed.
[0007]
[Problems to be solved by the invention]
However, since this type of CSP type semiconductor device has a fan-in area array structure in which external connection terminals (solder balls or bumps) are arranged in the integrated circuit element mounting region region range, the size of the semiconductor device is small. Although it is possible to cope with weight reduction, the number of leads routed between the external connection terminal lands is limited, and there is a problem that it is not possible to cope with the increase in the number of terminals.
The present invention has been made in view of the above circumstances, and can improve the electrical characteristics of a semiconductor device, meet the demand for miniaturization and weight reduction of a semiconductor device, and also meet the demand for multiple terminals. An object of the present invention is to provide a CSP type semiconductor device that can be used.
[0008]
[Means for Solving the Problems]
The semiconductor device according to claim 1, wherein the present invention achieves the above object, wherein the first conductive circuit pattern and the first lead are provided on the front and back surfaces of the first insulating member, and the first lead is provided. A second conductor circuit pattern separated from the first outer frame except for a predetermined lead is provided, and the first and second conductor circuit patterns are provided through through holes provided in the first insulating member. A first interposer provided with a semiconductor element mounting region at the center thereof, and fixed to the semiconductor element mounting region of the first interposer, and the second conductor circuit pattern. the lead bonding terminal of each lead, the lead bonding, the semiconductor element are electrically connected, it is fixed to the back surface of the semiconductor device, the front and back of the second insulating member Given of the third conductive circuit pattern, and the third of the third lead and having a lead separated from the second outer frame except for the predetermined lead of the second lead and having a lead comprising a except for the lead fourth conductor circuit pattern separated a third outer frame, moreover, the ground circuit pattern of the second conductor circuit pattern through a through hole formed in the second insulating member first 3 of the second conductive portion and a through hole provided in the second insulating member to form an electrical connection circuit between the ground circuit pattern of ground circuit pattern and the fourth conductor circuit pattern of the conductor circuit patterns And a third conductive portion that forms an electrical conductive circuit between the first external connection land of each lead of the third conductor circuit pattern and a predetermined external connection terminal, and the second insulating member. Through through holes A second interposer in which a fourth conductive portion of the ground terminal of the third and fourth conductor circuit patterns is formed, the semiconductor element, a sealing resin for sealing the second conductive portion, A second external connection terminal land and a third conduction part of each lead of the four conductor circuit patterns, and further an opening for exposing the fourth ground terminal provided on the outer frame of the fourth conductor circuit pattern. The cover resist covering the fourth conductor circuit pattern and the external connection terminal connected to the cover resist through the opening of the cover resist and projecting toward the external wiring board are provided.
[0009]
The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the first conductor circuit pattern is made of a metal having good thermal and electrical conductivity covering the second conductor pattern. The surface is provided with a corrosion-resistant metal plating layer and a grounding / heat dissipating substrate.
[0010]
The semiconductor device according to claim 3, wherein, in the semiconductor device according to claim 1, wherein the first conductive portion and the fourth conductive portion, a first outer frame of the second conductor circuit pattern, the the second outer frame of the third conductive circuit pattern, and corresponds to the fourth third ground terminals formed at four corners of the outer frame each of the outer frame of the conductor circuit patterns, a first conductor circuit pattern A ground circuit is formed between the external connection terminals.
[0011]
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the third conductive portion is formed in a fan-in area array shape in the semiconductor element mounting portion region range, A power supply or a signal circuit is formed between any one of the external connection terminals for signals and the semiconductor element.
[0012]
According to a fifth aspect of the present invention, in the semiconductor device according to the first aspect, the second conductive portion is formed close to the semiconductor element mounting portion region, and the semiconductor element and the second conductive portion are formed. One of the power supply circuit and the signal circuit between the circuit pattern and the third conductor circuit pattern is branched between the other and the fourth conductor circuit pattern, and a conduction circuit is formed. ing.
[0013]
The semiconductor device according to claim 6, in the semiconductor device according to any one of claims 1 to 5, wherein the first outer frame of the second conductor circuit pattern, the third conductive circuit patterns the second outer frame and third outer frame of the fourth conductor circuit pattern is to be common ground terminal to form a ground circuit. A semiconductor device according to a seventh aspect is the semiconductor device according to any one of the first to sixth aspects, wherein the first, second, third and fourth conductor circuit patterns are made of a thin metal plate. The inner lead frame having a required shape formed by pressing or etching is used.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Next, an example of an embodiment of the present invention will be described in detail based on the attached drawings. Here, FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view illustrating an external connection terminal side of the semiconductor device according to an embodiment of the present invention, and FIG. FIG. 4 is a plan view showing a third conductor circuit pattern according to an embodiment of the present invention, FIG. 4 is a cross-sectional view showing the configuration of a second interposer according to an example of the embodiment of the present invention, and FIG. It is a top view which shows the 4th conductor circuit pattern which concerns on an example of embodiment of this.
[0015]
As shown in FIGS. 1 and 2, a semiconductor device 10 according to an embodiment of the present invention includes a first device in which first and second conductor circuit patterns 12 and 13 are formed on the front and back surfaces of a semiconductor element 11, respectively. The interposer 14 and the second interposer 17 on which the third and fourth conductor circuit patterns 15 and 16 are formed are a liquid elastomer resin 18a that is an example of the first and second insulating adhesives 18 and 19. , 19a. Furthermore, a solder ball 21a, which is an example of a plurality of external connection terminals 21 having a structure protruding in the form of a fan-in area array that forms an electrical conduction circuit between the semiconductor element 11 and the external wiring board 20, is provided. is doing.
[0016]
As shown in FIG. 1, the first interposer 14 uses a first polyimide resin tape 22a which is an example of a first insulating member 22, and a corrosion-resistant metal which is an example of a conductive member on the front side. A first conductor circuit pattern 12 made of a copper foil material having a Ni plating layer is formed on the surface layer as an example. A plurality of through holes are formed in the first polyimide resin tape 22a to form an electrical conduction circuit with the first ground terminal 24 of the first conductor circuit pattern 12, and the first conductor circuit pattern 12 is formed. 1 has an electrical first conductive portion 23 for adding a function of grounding and heat dissipation.
[0017]
On the other hand, on the back side of the first polyimide resin tape 22a, as shown in FIG. 1, a second conductor circuit pattern 13 is formed around a central semiconductor element mounting region 25. The second conductor circuit pattern 13 has a large number of first leads 26, and one end portion of each lead 26 is provided with a lead bonding terminal 27 that is electrically connected to the semiconductor element 11, and the like. The end portion has a first lead connection terminal 28 that is electrically connected to the second interposer. Further, the required number of second ground terminals 29 (provided at the four corners in this embodiment) are provided on the periphery. A first outer frame 30 separated from each other except for a predetermined lead 26a of each first lead 26 is provided. Moreover, the second ground terminal 29 corresponds to the first conduction portion 23.
[0018]
By constructing the first interposer 14 in this way, the first ground terminal 24 and the second conductor 24 of the first conductor circuit pattern 12 are passed through the required number of through holes provided in the first polyimide resin tape 22a. A ground circuit is formed between the conductor circuit pattern 13 and the second ground terminal 29. The ground circuit can cause the first conductor circuit pattern 12 to function as a ground / heat sink, and the first outer frame 30 can be used as a common terminal for grounding.
[0019]
In this embodiment, a polyimide resin tape is used as the first insulating member 22. However, any polyimide resin film or other heat-resistant sheet or tape can be used.
[0020]
As shown in FIG. 4, the second interposer 17 uses a second polyimide resin tape 31 a which is an example of the second insulating member 31, and the front and back surfaces thereof are shown in FIGS. 3 and 5. Third and fourth conductor circuit patterns 15 and 16 are provided.
[0021]
As shown in FIG. 3, the third conductor circuit pattern 15 has a large number of second leads 33 extending inward. A first external connection terminal land 34 is provided at one end of each lead 33, and a second lead connection terminal 35 is provided at the other end. Further, the required number of third ground terminals 36 (four corners of the circuit pattern in this embodiment) are provided on the periphery. A second outer frame 37 separated from the second lead 33 except for a predetermined lead 33a is provided. In addition, the third ground terminal 36 is connected to the second ground terminal 29 through the conductive adhesive layer A.
[0022]
On the other hand, as shown in FIG. 5, the fourth conductor circuit pattern 16 has a large number of third leads 38 extending inward. A second external connection terminal land 39 is provided at one end of each lead 38, and a third lead connection terminal 40 is provided at the other end. Further, a required number of fourth ground terminals 41 (four corners of the circuit pattern in this embodiment) are provided on the periphery. A third outer frame 42 in which the leads are separated except for a predetermined lead 38a of each third lead 38 is provided. Moreover, the fourth ground terminal 41 corresponds to the third ground terminal 36.
[0023]
As shown in FIGS. 3 and 5, around the second polyimide resin tape 31a, a predetermined number of through-holes in which the third lead connection terminals 40 are exposed (in the present embodiment, four slanted lines are shown). A through-hole) 32 is formed. In this portion, the lead connection terminals corresponding to the first lead connection terminals 28 and the third and fourth lead connection terminals 35 and 40 overlap with each other, and an ultrasonic wave is an example of bonding. It has the 2nd conduction | electrical_connection part 23a (refer FIG. 1, FIG. 4) electrically joined by joining. Here, the same result can be obtained even when a conductive adhesive is used instead of ultrasonic bonding.
[0024]
Further, a through hole corresponding to the first external connection terminal land 34 of the third conductor circuit pattern 15 is formed in the second polyimide resin tape 31a, and a predetermined terminal of the external connection terminal 21 is formed in this portion. (In this embodiment, a signal I / O terminal) and a third conduction portion 23b that forms an electrical conduction circuit.
[0025]
Further, through holes corresponding to the third and fourth ground terminals 36 and 41 are formed in the second polyimide resin tape 31a, and the third ground terminal 36 and the fourth ground terminal are formed in this portion. 41 has a fourth conduction portion 23c that forms an electrical conduction circuit.
[0026]
Then, the first conductive portion 23 and the fourth conductive portion 23c, the first, second, third, and fourth ground terminals connected to the first conductive portion 23 and the fourth conductive portion 23c, and a conductive adhesive are used to determine a predetermined value of the external connection terminal. The first conductor circuit pattern is formed by forming an electrical conduction circuit between the terminal (in this embodiment, external connection ground terminals formed at the four corners of the outer frame shown in FIG. 2) and the first conductor circuit pattern 12. 12 is added with a grounding function.
[0027]
In the semiconductor device 10 including the first interposer and the second interposer configured as described above, the semiconductor element 11 has a first insulating property in the semiconductor element mounting region 25 of the first interposer 14. The first liquid elastomer resin 18a, which is an example of the adhesive 18, is used for bonding, and the electrode pads of the semiconductor element 11 and the lead bonding terminals 27 of the first leads 26 are connected by lead bonding. Has been. Further, the second interposer 17 is bonded to the back surface of the semiconductor element 11 by using a second liquid elastomer resin 19a which is an example of a second insulating adhesive 19, and each of the first leads. The connection terminal 28 and the third and fourth lead connection terminals 35 and 40 are electrically joined to the corresponding lead connection terminals by ultrasonic bonding (see FIGS. 1 and 4). Then, the second conductive portion 23a of the semiconductor element and the first, second, and third lead connection terminals is resin-sealed with a sealing elastomer resin that is an example of a sealing resin 43, and further, FIG. 4 and FIG. 5, the fourth conductor pattern 16 has an opening that exposes the fourth ground terminal land 41, the second external connection terminal land 39, and the third conductive portion 23b. 1 is provided with an external cover terminal 21 projecting to the cover / resist side through the opening 44, as shown in FIG. Thus, a semiconductor device having external connection terminals for a fan and an external connection terminal in the form of a fan-in area array is formed. Here, the cover resist 45 may be a liquid resist formed using a silk printing method or a film photoresist exposure method.
[0028]
Since it is configured as described above, the coupling between the semiconductor element and the external connection terminal is appropriately branched into the second conductor circuit pattern and the third conductor circuit pattern at the second conductive portion 23a, and inwardly. The circuit can be changed (see FIGS. 1, 2, 3, 4, and 5). An appropriate combination of electrical conduction circuits can be formed between the semiconductor element 11 and the external connection terminal 21 via each conduction portion.
[0029]
In the embodiment, the semiconductor element mounting region is pressed so as to protrude toward the first conductor circuit pattern side to form an element mounting cavity, and the lead bonding terminal of the first lead is on the cavity side. Although it is configured to be re-depressed so as to protrude (see FIG. 1), a configuration in which re-depressing is not formed may be employed.
[0030]
Further, the second interposer has a configuration in which the first and second conductor circuit patterns are formed on the front and back surfaces of the second insulating member, but the first conductor circuit pattern is formed on one surface of the insulating member. The second conductor circuit pattern may be formed on another insulating member, and each may be joined with an insulating adhesive. With this configuration, the conductor circuit pattern can be easily formed.
[0031]
Furthermore, since the first, second, third and fourth conductor circuit patterns are formed by using respective inner lead frames of a required shape formed by pressing or etching from a metal thin plate, the conductor circuit Pattern formation processing is facilitated, and the manufacturing cost of the semiconductor device can be reduced.
[0032]
Further, since the first conductive portion of the first lead connection terminal, the second lead connection terminal, and the third lead connection terminal is formed, the area extending from the second and third lead connection terminals in the inward direction. It can be formed in an array arrangement. This makes it easier to handle multiple terminals.
[0033]
【The invention's effect】
The semiconductor device according to claim 1 or 2 is a conduction part in which a conduction circuit between the I / O pad of the signal of the semiconductor element, the power supply pad and the ground pad, and the external connection terminal is provided adjacent to the semiconductor element mounting region. Branching to the third and fourth conductor circuit patterns, and the external connection terminal lands having a second interposer arranged in a fan-in area array, close to the outer size of the semiconductor element The package size can be reduced in size and weight, and the number of terminals of the semiconductor device can be increased.
[0034]
The semiconductor device according to claim 2 is the semiconductor device according to claim 1, wherein the first conductor circuit pattern has a function of grounding / dissipating heat made of a metal having good thermal and electrical conductivity. Thus, the crosstalk phenomenon of the semiconductor device can be prevented and the electrical characteristics can be improved.
[0035]
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, between the first conductor circuit pattern and the external connection terminal in each outer frame of the second, third, and fourth conductor circuits. Since a grounding terminal for forming a grounding circuit is provided in the first and second conductor circuit patterns, either the first or second conductor circuit pattern can function as a grounding circuit or / and a power supply circuit. And the electrical characteristics of the semiconductor device can be further improved.
[0036]
According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the third conductive portion is formed in a fan-in area array shape in the semiconductor element mounting portion region range, Since a power supply or a signal circuit is formed between any one of the external connection terminals for signals and the semiconductor element, it is possible to more easily cope with downsizing and multi-terminal of the semiconductor device. In addition, the electrical characteristics can be further improved.
[0037]
The semiconductor device according to claim 5 is the semiconductor device according to claim 1, wherein the fourth conductive portion is formed in the vicinity of the semiconductor element mounting portion region, and the semiconductor element and the second conductive portion are formed. A branch for converting the circuit between one of the power source and the signal circuit between the circuit pattern and the third conductor circuit pattern and the other between the circuit circuit pattern and the fourth conductor circuit pattern is formed. Therefore, the interval between the external connection terminals can be shortened, and a multi-terminal can be easily realized.
[0038]
A semiconductor device according to a sixth aspect is the semiconductor device according to any one of the first to fourth aspects, wherein the outer frame of the second, third, and fourth conductor circuit patterns is a ground circuit. Therefore, the outer frame of the first, second and third conductor circuit patterns can be used as a common ground circuit, and the degree of freedom in circuit design of the semiconductor element is improved. Can be made.
[0039]
A semiconductor device according to a seventh aspect is the semiconductor device according to any one of the first to sixth aspects, wherein the first, second, third and fourth conductor circuit patterns are made of a thin metal plate. Low-cost semiconductor device with a configuration using an inner lead frame of a required shape formed by press working or etching, making it easy to form a conductor circuit pattern, reducing manufacturing costs Can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to an example of an embodiment of the present invention.
FIG. 2 is a plan view showing an external connection terminal side of a semiconductor device according to an example of an embodiment of the present invention.
FIG. 3 is a plan view showing a third conductor circuit pattern of a semiconductor device according to an example of an embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating a configuration of a second interposer of a semiconductor device according to an example of an embodiment of the present invention.
FIG. 5 is a plan view showing a fourth conductor circuit pattern of a semiconductor device according to an example of an embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor element 12 1st conductor circuit pattern 13 2nd conductor circuit pattern 14 1st interposer 15 3rd conductor circuit pattern 16 4th conductor circuit pattern 17 2nd interposer 18 1st insulation Adhesive 18a Liquid elastomer resin 19 Second insulating adhesive 19a Liquid elastomer resin 20 External wiring board 21 External connection terminal 21a Solder ball 22 First insulating member 22a First polyimide resin tape 23 First conducting portion 23a Second conductive portion 23b Third conductive portion 23c Fourth conductive portion 24 First ground terminal 25 Semiconductor element mounting region 26 First lead 26a Lead 27 Lead bonding terminal 28 First lead connection terminal 29 Second Ground terminal 30 First outer frame 31 Second insulating member 31a Second polyimide resin tape 32 Through-hole 33 Second lead 33a Lead 34 First external connection terminal land 35 Second lead connection terminal 36 Third ground terminal 37 Second outer frame 38 Third lead 38a Lead 39 Second external connection Terminal land 40 Third lead connection terminal 41 Fourth ground terminal 42 Third outer frame 43 Sealing resin 44 Opening 45 Cover resist

Claims (7)

第１の絶縁性部材の表裏面に第１の導体回路パターン及び第１のリードを有するとともに該第１のリードのうちの所定のリードを除いて第１の外枠と分離した第２の導体回路パターンを備え、しかも、前記第１の絶縁性部材に設けられたスルーホールを介して第１及び第２の導体回路パターンの第１の導通部が形成され、さらに、その中央部に半導体素子搭載領域を設けた第１のインターポーザと、前記第１のインターポーザの半導体素子搭載領域に固着され、前記第２の導体回路パターンの各リードのリードボンディング端子とは、リードボンディングにより、それぞれ電気的に接続された半導体素子と、前記半導体素子の裏面に固着されており、第２の絶縁性部材の表裏に第２のリードを有するとともに該第２のリードのうちの所定のリードを除いて第２の外枠と分離した第３の導体回路パターン及び第３のリードを有するとともに該第３のリードのうちの所定のリードを除いて第３の外枠と分離した第４の導体回路パターンを備え、しかも、第２の絶縁性部材に設けられた貫通孔を介して第２導体回路パターンの接地回路パターンと第３の導体回路パターンの接地回路パターン及び第４の導体回路パターンの接地回路パターンとの間に電気的導通回路を形成する第２の導通部と第２の絶縁性部材に設けられたスルーホールを介して第３の導体回路パターンの各リードの第１の外部接続ランドと所定の外部接続端子との間に電気的導通回路を形成する第３の導通部と第２の絶縁性部材に設けられたスルーホールを介して第３及び第４の導体回路パターンの接地端子の第４の導通部とが形成された第２のインターポーザと、前記半導体素子、前記第２の導通部を封止する封止樹脂と、第４の導体回路パターンの各リードの第２の外部接続端子ランド及び第３の導通部、さらには、第４の導体回路パターンの外枠に設けた第４の接地端子を露出する開口部を備え、第４の導体回路パターンを被覆するカバーレジストと、前記カバーレジストの開口部を介して接続され、外部配線基板側に突出した外部接続端子とを具備して成ることを特徴とする半導体装置。A second conductor having a first conductor circuit pattern and a first lead on the front and back surfaces of the first insulating member and separated from the first outer frame except for a predetermined lead of the first lead. A first conductive portion of the first and second conductor circuit patterns is formed through a through hole provided in the first insulating member, and further includes a semiconductor element at the center thereof A first interposer provided with a mounting area and a lead bonding terminal of each lead of the second conductor circuit pattern are electrically connected to each other by lead bonding, and are fixed to the semiconductor element mounting area of the first interposer. and connected semiconductor devices, wherein is fixed to the back surface of the semiconductor element, a predetermined re of the second lead and having a second lead on the front and back of the second insulating member The separated from the third outer frame except for the predetermined lead of the third lead and having a third conductor circuit pattern and the third lead separate from the second outer frame except for de 4 And a ground circuit pattern of the second conductor circuit pattern, a ground circuit pattern of the third conductor circuit pattern, and a fourth conductor circuit through a through hole provided in the second insulating member. The first of each lead of the third conductor circuit pattern through a second conduction portion that forms an electrical conduction circuit between the pattern and the ground circuit pattern, and a through hole provided in the second insulating member Third and fourth conductor circuit patterns via a third conduction portion that forms an electrical conduction circuit between the external connection land and a predetermined external connection terminal, and through holes provided in the second insulating member 4th conduction of the ground terminal of A second interposer in which the semiconductor element and the second conductive portion are sealed, a second external connection terminal land of each lead of the fourth conductor circuit pattern, and a third A cover resist for covering the fourth conductor circuit pattern, and an opening for the cover resist, further comprising an opening for exposing the fourth ground terminal provided on the outer frame of the fourth conductor circuit pattern. A semiconductor device comprising: an external connection terminal connected through a portion and protruding toward the external wiring board. 前記第１の導体回路パターンは、第２の導体パターンを覆う熱的、電氣的伝導性の良好な金属から成り、その表面に耐食性の金属めつき層を設け接地・放熱基板を設けた構成としたことを特徴とする請求項１記載の半導体装置。    The first conductor circuit pattern is made of a metal having good thermal and electrical conductivity covering the second conductor pattern, and has a structure in which a corrosion-resistant metal plating layer is provided on the surface thereof and a grounding / heat dissipating board is provided. The semiconductor device according to claim 1. 前記第１の導通部及び第４の導通部は、前記第２の導体回路パターンの第１の外枠、前記第３の導体回路パターンの第２の外枠、及び前記第４の導体回路パターンの第３の外枠それぞれの外枠の四隅に形成された接地端子に対応し、第１の導体回路パターンと外部接続端子との間に接地回路を形成する構成としたことを特徴とする請求項１記載の半導体装置。Said first conductive portion and the fourth conductive portion, said first outer frame of the second conductor circuit pattern, the second outer frame of the third conductive circuit pattern, and the fourth conductive circuit pattern The ground circuit is formed between the first conductor circuit pattern and the external connection terminal corresponding to the ground terminals formed at the four corners of each of the third outer frames. Item 14. A semiconductor device according to Item 1. 前記第３の導通部は、半導体素子搭載部領域範囲にファン・インのエリア・アレイ状に形成され、電源又は信号用のいずれか一方の前記外部接続端子と前記半導体素子との間に電源又は信号回路を形成することを特徴とする請求項１記載の半導体装置。    The third conductive portion is formed in a fan-in area array shape in a semiconductor element mounting portion region range, and a power source or a power source or a signal is connected between the external connection terminal for signals and the semiconductor element. 2. The semiconductor device according to claim 1, wherein a signal circuit is formed. 前記第２の導通部は、前記半導体素子搭載部領域に近接して形成され、前記半導体素子と第２の導電回路パターンとの間の電源及び信号用回路のいずれか一方を第３の導体回路パターンとの間に、他方を第４の導体回路パターンとの間に分岐して導通回路を形成することを特徴とする請求項１記載の半導体装置。    The second conductive portion is formed in the vicinity of the semiconductor element mounting portion region, and either a power source or a signal circuit between the semiconductor element and the second conductive circuit pattern is used as a third conductor circuit. 2. The semiconductor device according to claim 1, wherein a conductive circuit is formed by branching between the other and the fourth conductor circuit pattern. 前記第２の導体回路パターンの第１の外枠、前記第３の導体回路パターンの第２の外枠及び前記第４の導体回路パターンの第３の外枠は、接地回路を形成する共通接地端子であることを特徴とする請求項１から５記載のいずれか１項に記載の半導体装置。Said first outer frame of the second conductor circuit pattern, a third outer frame of the second outer frame and said fourth conductor circuit pattern of the third conductive circuit patterns, a common ground to form a ground circuit 6. The semiconductor device according to claim 1, wherein the semiconductor device is a terminal. 前記第１、第２、第３及び第４の導体回路パターンは、金属薄板からプレス加工又はエッチング加工で形成された所要形状のインナー・リードフレームであることを特徴とする請求項１〜６記載のいずれか１項に記載の半導体装置。    7. The first, second, third and fourth conductor circuit patterns are inner lead frames having a required shape formed by pressing or etching from a thin metal plate. The semiconductor device according to any one of the above.
JP26273997A 1997-09-09 1997-09-09 Semiconductor device Expired - Fee Related JP3877095B2 (en)

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US6351393B1 (en) 1999-07-02 2002-02-26 International Business Machines Corporation Electronic package for electronic components and method of making same
US6373717B1 (en) 1999-07-02 2002-04-16 International Business Machines Corporation Electronic package with high density interconnect layer
JP3371867B2 (en) * 1999-10-05 2003-01-27 日本電気株式会社 Semiconductor device
JP2002118204A (en) * 1999-11-17 2002-04-19 Sumitomo Bakelite Co Ltd Semiconductor device, substrate for mounting semiconductor and method for manufacturing the same
KR100708044B1 (en) * 2001-07-28 2007-04-16 앰코 테크놀로지 코리아 주식회사 Multi-layer circuit tape and its manufacturing method and semiconductor package using it
CA2455024A1 (en) 2003-01-30 2004-07-30 Endicott Interconnect Technologies, Inc. Stacked chip electronic package having laminate carrier and method of making same
US7023707B2 (en) 2003-01-30 2006-04-04 Endicott Interconnect Technologies, Inc. Information handling system
US7035113B2 (en) 2003-01-30 2006-04-25 Endicott Interconnect Technologies, Inc. Multi-chip electronic package having laminate carrier and method of making same
JP2005317861A (en) 2004-04-30 2005-11-10 Toshiba Corp Semiconductor device and method of manufacturing the same
US7332818B2 (en) 2005-05-12 2008-02-19 Endicott Interconnect Technologies, Inc. Multi-chip electronic package with reduced line skew and circuitized substrate for use therein

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