JP3866681B2 - Semiconductor device - Google Patents

Description

【００３６】
ここで、拡散電位によって形成される空乏層は埋め込み層の間に存在し、電流経路を狭め抵抗値を上げるので、より厳密な導電面積率を求めるために、この空乏層面積を考慮して求める。拡散電位Ｖ_biは、
Ｖ_bi＝ｋＴ ｌｎ（ｎ_n0ｐ_p0／ｎ_i）
ここで、
ｋ： ボルツマン係数
Ｔ： 絶対温度
ｎ_n0： ｎ型層の多数キャリア密度
ｐ_p0： ｐ型層の多数キャリア密度
ｎ_i ： 真性キャリア密度
となる。
【００３７】
拡散電位によって作成される１次元の空乏層幅は、ｐ⁺ とｎ^- 層のジャンクションなので空乏層はｎ^- 層のみに伸びると近似することができるので、
ｗ_bi＝√｛２εＶ_bi／（ｑＮ_n）｝
ここで、
Ｎ_n ：ｎ^- 層のネット不純物濃度
である。
【００３８】
拡散電位による空乏層の表面積は、電導面積を減らし、その値は、埋め込み形状の周辺長に１次元の空乏層幅をかけたものと仮定した場合の形状別の空乏層面積を以下に示す。
【００３９】
【表２】

【００４０】
形状によって空乏層面積が異なる。また、拡散電位を決める多数キャリア密度と真性キャリア密度は、バンドギャップエネルギーによって変化するので、バンドギャップエネルギーが異なる材料もまた空乏層面積に影響を及ぼす。材料別のバンドギャップエネルギーと比誘電率は、
【表３】

である。
【００４１】
材料からくるバンドギャップエネルギーとｎ^- 層の不純物濃度によって空乏層面積に影響を及ぼすので、（表１）に示す導電面積率に補正をかけて計算するのはより正確な値を得られる。
【００４２】
（表１）に示す公式を用いて、埋め込み層間隔ｗ＝０．５，１，５μｍのときの横軸に寸法率（間隔／幅）、縦軸に導電面積率を、それぞれ図３（ａ）〜（ｃ）に示す。いずれも４Ｈ−ＳｉＣの場合であり、（ａ）は埋め込み幅ｗが０．５μｍ、（ｂ）はｗが１μｍ、（ｃ）はｗが５μｍである。構造条件は、４Ｈ−ＳｉＣを用いた場合であり、埋め込み層１層で上のｎ^- 層と下のｎ- 層は共に不純物濃度が２×１０¹⁶ｃｍ^-3で厚さ５μｍである。
【００４３】
何れの場合においても、丸形状が最も導電面積率が高く、次に四角と六角形が同じ値を示し、ストライプが最も低い値となった。寸法率が小さいところでは導電面積率が０になっているのは、埋め込み層間隔が、拡散長より小さくなる領域で、埋め込み層間が空乏層で埋まってしまい、電流が流れるパスがなくなることを意味する。
【００４４】
横軸に寸法率（ｓ／ｗ）、縦軸に理想値を基準に正規化した耐圧、オン抵抗をそれぞれ図４（ａ）（ｂ）に示す。寸法率が増加すると耐圧は減少し、減少するとオン抵抗は上昇する。なお、オン抵抗に関して、ｓ＝０．６μｍの場合は極めて高いオン抵抗を示したために、図４（ｂ）には記していない。
【００４５】
また、正規化した耐圧とオン抵抗の関係を図４（ｃ）に示す。耐圧とオン抵抗が共に良好な値を示すのが最適な構造となり、以下に上位３つの具体値を示す。この条件は、エピタキシャル層の不純物濃度を２×１０¹⁶ｃｍ^-3、単位エピタキシャル層厚を５μｍ、埋め込み１層の構造である。
【００４６】
【表４】

【００４７】
各埋め込み層と表面パターンとの整合性について、ストライプではなく、四角，丸，六角の孤立形状を適用すると、位置合わせがずれても問題ないので整合性は取れる。また、孤立形状であればチップのダイシングで埋め込み層に接触しても電気的には他の埋め込み層とは孤立しているため、リーク発生と耐圧劣化の問題は解決できる。そのため、連続形状のように埋め込み層とチップ端の間隔を大きくとる必要は無くチップ面積少、コスト低下につながる。また、位置合わせ不要のため、位置合わせマークの作成と特別なプロセスの必要性が無くなり、コストを低下できる。
【００４８】
また、孤立形状の埋め込み層を適用すると、ダイシング位置を考慮する必要が無くなることで、チップ面積を無視してウエハー全面に埋め込み層を作ることができる。そのため、埋め込み層ありのウエハーを大量生産することができ、コストが大きく低下する可能性があり、従来技術のコストより低くできる可能性がある。
【００４９】
このように本実施形態によれば、埋め込み層を孤立の円形とすることにより、導電面積率を大きくしてオン抵抗を小さくすることができる。より具体的には、埋め込み層の形状として導電面積率が最も高くなる丸形状に関し、図４（ａ）から、１≦ｓ／ｗ≦２では、ｓが３μｍ以下で十分大きな正規化耐圧（Ｖｂｒ＞０．７５）が得られた。さらに、２＜ｓ／ｗ≦３では、ｓが２μｍ以下で十分大きな正規化耐圧（Ｖｂｒ＞０．７５）が得られた。また、図４（ｂ）から、ｓ／ｗが１以上であれば、ｓが１μｍ以上でＲon≦２の低いオン抵抗が得られた。従って、円形の埋め込み層の幅ｗ及び間隔ｓの望ましい範囲は、１≦ｓ／ｗ≦２，１≦ｓ≦３、又は２＜ｓ／ｗ≦３，１≦ｓ≦２である。
【００５０】
（第２の実施形態）
今まで述べた孤立形状は、埋め込み層を孤立形状で作成し、他の領域はｎ^- 層になっている。ここで、ｐ⁺ 埋め込み層とｎ^- 層形状を反転させた場合の構造を提案する。この場合の形状について、図５（ａ）〜（ｄ）に示す。（ａ）は四角メッシュ、（ｂ）は四角交互、（ｃ）は丸交互、（ｄ）は六角形交互の形状の場合である。拡散電位による空乏層を考慮にいれない場合、導電面積率は下記の（表５）のようになり、その寸法率依存は図６のようになる。拡散電位による空乏層の面積を（表６）に、その導電面積率の解析式を（表７）に示す。
【００５１】
【表５】

【００５２】
【表６】

【００５３】
【表７】

【００５４】
また、埋め込み層間隔に対する導電面積率対寸法率を、図７（ａ）〜（ｃ）にそれぞれ示す。（ａ）はビルトイン電位を考慮した場合でｗ＝０．５μｍの電導面積率の寸法依存、（ｂ）はｗ＝１μｍの電導面積率の寸法依存性、（ｃ）はｗ＝５μｍの電導面積率の寸法依存性である。
【００５５】
この場合、ストライプが最も導電面積率が高く、次に四角（メッシュと交互は同じ）、次に六角形が高く、最も低いのは丸であった。ストライプの伝導面積率が最も高く抵抗が最も低くなることが期待され、従ってｐ⁺ 埋め込み層とｎ^- 層形状を反転させた構造においては、ストライプ形状とすればよい。
【００５６】
動特性改善構造のための埋め込み層コンタクト領域を含んだ構造の丸、六角形の場合の上面図を図８（ａ）〜（ｄ）に示す。図８で（ａ）はメッシュ構造のコンタクト領域を持ちその四角の中に四角を交互に並べる伝導層を持つ埋め込み層の構造、（ｂ）はメッシュ構造のコンタクト領域を持ちその四角の中にメッシュ形状の埋め込み層を持つ構造、（ｃ）はメッシュ構造のコンタクト領域を持ちその四角の中に丸が交互に並ぶ伝導層を持つ埋め込み層の構造、（ｄ）はメッシュ構造のコンタクト領域を持ちその四角の中に六角形が交互に並ぶ伝導層を持つ埋め込み層の構造である。図中２１は埋め込み層コンタクト領域、２２はｐ⁺ 層、２３はｎ^- 層を示している。
【００５７】
この形状は、埋め込み層形状以外に、ＳＩＴ（Static Induction Transistor）のゲート領域とソース領域（伝導領域）にも適用できる。埋め込み層との対応は、埋め込み層は導電領域ではないので、ＳＩＴのゲートに対応し、埋め込み層の間隔形状（ｎ^- 形状）は導電領域なのでＳＩＴのソース形状（導電形状）に対応する。
【００５８】
図９に大略的なＳＩＴの断面形状を示す。図中の３１はｎ⁺ 型基板、３２はｎ^- 層、３３はゲート、３４はソースを示している。図１０にその上面図を示す。図１０の（ａ）はストライプの場合、（ｂ）は四角メッシュの場合、（ｃ）は四角交互の場合、（ｄ）は丸交互の場合、（ｅ）は六角形交互の場合である。この場合、ゲートがストライプ形状の導電面積率が最も高いので、抵抗が最も小さくなる。
【００５９】
ゲートは、ショットキーコンタクトを持つニッケル等の金属で形成されている。ソース電圧を０Ｖ、ドレイン電圧をソース電圧よりも高くする。ゲート電圧がしきい値以下の時、ソース領域を挟んで存在する２つのゲートからｎ−層に伸びた空乏層は、ソース領域でつながり、ソースとドレインを空乏層で遮ることで、ソースとドレイン間の電流経路を断ち、デバイス状態はオフ状態になる。ゲート電圧がしきい値以上の場合、ソースを挟んだ２つのゲートから伸びた空乏層の伸びは後退をし、２つの空乏層は離れる。これにより、ソースとドレイン間がｎ^- を通してつながることで、電流が流れ、オン状態となる。
【００６０】
ここで、ゲートをショットキーコンタクト金属ではなく、ｐ⁺ 層で形成すれば、ＪＦＥＴになる。動作原理はＳＩＴと同じである。
【００６１】
（第３の実施形態）
動特性においてオフからオンになるときに電流が増加せずオン抵抗が急増する問題の解決方法として、埋め込み層に電圧印加を行う。半導体素子は前記図１に示すような構造とし、埋め込み層は孤立長方形とした。
【００６２】
具体的方法として、図１１（ａ）に示すように、カソードとアノード間に２つの抵抗Ｒ１とＲ２を直列に接続し、２つの抵抗の接続ノードから埋め込み層に電圧を供給する。図中の４２はｎ^- 層、４３はショットキーコンタクト、４５はｐ⁺ 埋め込み層である。供給する電圧値は、埋め込み層の理想電圧値になるようにＲ１とＲ２の比率を決める。その関係式は、
Ｖｕ＝１／（１＋Ｒ１／Ｒ２）×Ｖａ
Ｖｕ：埋め込み層への印加電位
Ｖａ：アノード電圧
となる。
【００６３】
また、Ｒ１＋Ｒ２が低すぎれば、カソードとアノード間にリーク電流が流れ、オフ時の消費電力が増加するので十分高い抵抗値の設定が必要である。この抵抗によるリーク電流値Ｉｒは、
Ｉｒ＝Ｖａ／（Ｒ１＋Ｒ２）
となる。
【００６４】
さらに、Ｒ１＋Ｒ２が高すぎると、オフ時に、抵抗を通して埋め込み層に注入される電荷量が、ｎ^- 層の多数キャリアが埋め込み層に注入する量より低くなり、埋め込み層の電位が十分に理想電位に近くならないので、オフからオンへの特性が改善されない可能性が出てくる。故に、埋め込み層の電位が十分に理想電位に近づくように抵抗値を選択する必要がある。オフ時の埋め込み層の理想電位は、その層の上部で支えられる電圧の合計になる。上部から下に向かって、埋め込み層で分割されるｍ番目のｎ^- 層の不純物濃度と厚さと支えられる電圧をそれぞれ、Ｎ_m，ｔ_m，Ｖ_m で表す。このときｍは１からｎ^- 層の分割数までとなる。埋め込み層の総数をＭとすると、
Ｖ_m ＝ｑＮ ｔ_m ²／（２ε）
ここで、
ｑ：単一電子の電荷
ε：誘電率
となり、上からｍ番目の埋め込み層の理想電位Ｖｕ_ｍは、
【数１】

となる。
【００６５】
シミュレーションによる比較結果を図１２に示す。図１１（ａ）の構成からＲ１，Ｒ２を除去した構成を用いて従来構造の動特性を調査した。図１２は、従来構造と図１１（ａ）に示す動特性改善構造のトランジェント特性を示す。オフからオンに移行した後の出力電圧Ｖｏｕｔの値が、従来では１００Ｖ以上になり改善構造では０Ｖ近辺になり、改善構造で動特性が大きく改善されていることが分かる。
【００６６】
従来構造では、オフからオンへの遷移特性で、Ｖｏｕｔの電圧が一旦異常に高くなってゆっくりと低下している。これは、オン抵抗が一時的に大きく増加していることによる。これに対し、本実施形態構造について図１１（ａ）の回路構成でシミュレーションを行った結果、オン状態のＶｏｕｔは安定して低く正常な動特性を示していることから、提案構造で確実に改善されていることが証明された。
【００６７】
図１１（ｂ）は、図１１（ａ）の構成からＲ１を削除したものであり、埋め込み層とカソード間を抵抗Ｒ２を通してつないで埋め込み層への電位印加を行う構造を示す。オフ状態の時、リーク電流がカソード→Ｒ２→埋め込み層→埋め込み層上部のｎ^- 層→アノードに流れるため、Ｒ２の抵抗は許容されるリーク値に収めるために高くする。また、Ｒ２の抵抗値が高すぎると、スイッチング特性に問題が出るので、許容されるスイッチング特性を満たすように設定する。図１１（ｃ）は、埋め込み層とその上部のｎ^- 層を電気的に接続することで、埋め込み層に電位を与える構造である。
【００６８】
図１１（ａ）〜（ｃ）の何れの構成においても、埋め込み層はフローティングではなくなり所定の電位が印加されることになり、従ってオフ状態からオン状態へのスイッチング速度を高め、動特性の向上をはかることができる。
【００６９】
抵抗印加方式の具体的なデバイス構造について、図１３及び図１４を参照して説明する。
【００７０】
図１３は、デバイスを作成するアクティブ領域の端に斜めの側面を作り、その側面に抵抗層としてｐ型ポリシリコン又はｐ層を作成して埋め込み層に電圧を印加する例である。図中５１はｎ⁺ 型基板、５２はｎ^- 層、５５はｐ⁺ 層、５７は抵抗層、５８はメタルコンタクトである。抵抗層５７としてのｐ型ポリシリコン又はｐ層は、ｐ⁺ 埋め込み層５５とは電気的に接続され、ｎ^- 層５２には物理的に接触しているが電気的に接続されないのでｎ^- 層５２とは絶縁され埋め込み層５２に電圧を印加できる。下部において、メタルコンタクトを作成しｎ⁺ を介してカソード電圧が印加される。垂直な構造はエッチングで作成される。抵抗層５７は、ｐ型ポリシリコンの場合はＬＰＣＶＤによって、ｐ層の場合はイオン注入で作成される。抵抗層５７の上部をアノード電圧にバイアスすれば図１１（ａ）の印加方式になり、上部のアノードバイアスをなくせば図１１（ｂ）の印加方式になる。
【００７１】
本実施形態のように、勾配があるとポリシリコンを付け易い、又はｐ層をイオン注入で作成し易いという利点がある。勾配構造もエッチングで作成することができる。
【００７２】
図１４は、デバイスを作成するアクティブ領域の中にトレンチ構造を作成し、その上にショットキーコンタクト５９を蒸着で付けて、ショットキーダイオードを作成した構造である。下部において、メタルコンタクト５８を作成しｎ⁺ 層５１を介してカソード電圧が印加される。トレンチ構造はエッチングで作成される。抵抗層５７は、ｐ型ポリシリコンの場合はＬＰＣＶＤによって、ｐ層の場合はイオン注入で作成される。抵抗層５７の上部をアノード電圧にバイアスすれば図１１（ａ）の印加方式になり、上部のアノードバイアスをしなければ図１１（ｂ）の印加方式になる。
【００７３】
埋め込み層に電位を印加する抵抗層の作成は、アクセプタをイオン注入することでｐ^- 層を作成できる。しかし、この層はカソードとアノード電極間を繋げることでリーク電流になるので、高抵抗が望まれる。イオン注入で抵抗層を作成するとｎ^- 層を反転させるために、ｎ^- 層と同じレベルの不純物濃度以上が入ることになる。もし、それ以上の抵抗値が必要な場合は、イオン注入では作成が困難になる。
【００７４】
この代替方法として、ｐ型の高抵抗ポリシリコンを抵抗層に使う。ポリシリコンの不純物濃度はｎ^- 層とは無関係に決定できるので任意の抵抗を実現できる。また、ｐ型を使うことでｎ^- 層とは逆バイアスになるのでｎ^- 層からポリシリコンへの電流は流れなく、埋め込み層とは同じｐ型なので電気的に接続でき、都合がよい。
【００７５】
（第４の実施形態）
他の動特性改善構造として、埋め込み層の電位をその上のｎ^- 層と同電位にするためにその間を電気的にショートする構造を提案する。具体的な改善構造例として、埋め込み層の端にメサを作成し、埋め込み層とその上の部分にショートするためのメタル層を形成する構造を、図１５に示す。
【００７６】
もし、埋め込み層と下側のｎ^- 層とショートした場合、下のｎ^- 層→埋め込み層→上のｎ^- 層→ゲートに微小電流が流れ、逆バイアス印加時のリーク電流になりゆえに消費電力損失になるので好ましくない。よって、埋め込み層と上の層をショートする構造とすることが提案される。
【００７７】
本実施形態においても、埋め込み層をフローティングではなくし、埋め込み層に所定の電位を与えることができるため、先の第３の実施形態と同様の効果が得られる。なお、この図では、終端メサ壁面での埋め込み層とその上部との接続構造で、接続材料にフィールドプレート機能を持たせた構造としている。
【００７８】
図１６は、埋め込み層への電位印加を、トレンチ構造において行うもので、図１１（ｃ）の実施形態である。図中の６１はｎ⁺ 型基板、５２はｎ^- 層、６５はｐ⁺ 層、６７は導電物質、６８は絶縁性物質、６９はショットキーコンタクトである。トレンチ構造内の導電性物質６７は例えば金属やポリシリコン等で形成されており、絶縁性物質６８は例えば酸化膜で形成されている。導電性物質６７は、埋め込み層６５と埋め込み層６５上のｎ^- 層にまたがる場所に位置することで、埋め込み層とその上のｎ^- 層を電気的に接続する。
図１５と同じ原理で横型のＭＯＳＦＥＴに適用した例を、図１７に示す。図中の７１は基板、７２はｎ^- 層、７３はｐ層、７４はソース、７５はドレイン、７６はゲート、７７はメタル層を示している。図１６及び図１７の構造においても図１５と同様の効果が得られる。
【００７９】
図１５と同じ原理で横型のＭＯＳＦＥＴに適用した例を、図１７に示す。図中の７１は基板、７２はｎ^- 層、７３はｐ層、７４はソース、７５はドレイン、７６はゲート、７７はメタル層を示している。図１６及び図１７の構造においても図１５と同様の効果が得られる。
【００８０】
（第５の実施形態）
動特性改善構造として前記図１３，図１４に示した埋め込み層の端での電位印加構造の、上面図を例として図１８（ａ）〜（ｆ）に示す。図１８（ａ）はストライプ形状の埋め込み層において、それと交差する方向に、全ての埋め込み層を跨いで、ある間隔をおいて平行に繰り返す埋め込み層コンタクト領域が位置する構造である。図１８（ｂ）は、埋め込み層コンタクト構造が任意の数の埋め込み層を跨いで位置する構造である。図１８（ｃ）は、埋め込み層１本毎にコンタクト領域を位置させた例である。
【００８１】
埋め込み層に欠陥起因の電流リークが存在する場合、図１８（ａ）はその埋め込み層１本が全て不良となってしまうのに対し、図１８（ｂ）はそれより不良となる埋め込み層の長さが限られるので、歩留まりの低下を減少できる効力がある。図１８（ｃ）はさらにその効力がある。
【００８２】
図１８（ｄ）は、図１８（ｃ）の埋め込み層コンタクト領域を交互に位置させることによって、コンタクト同士の隔離を大きく取ることができるのでプロセスが容易になる効果がある。図１８（ｅ）は、ストライプ形状の埋め込み層の場合の埋め込み層コンタクト領域を升目状にしたものである。図１８（ｆ）は図１８（ｅ）のコンタクト領域を長方形状にした例である。
【００８３】
（変形例）
なお、本発明は上記実施形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施形態に開示されている複数の構成要素の適宜な組み合わせにより、種々の発明を形成できる。
【００８４】
例えば、実施形態に示される全構成要素から幾つかの構成要素を削除してもよい。さらに、異なる実施形態にわたる構成要素を適宜組み合わせてもよい。また、ｐ⁺ 埋め込み層やｎ^- 層は、様々な素子との組み合わせが可能である。例えば、ダイオードではショットキーダイオード、ＰｉＮダイオードである。表面にＭＯＳＦＥＴ構造を作成すると、ＤＭＯＳＦＥＴ，ＡＣＣＵＦＥＴ，ＵＭＯＳＦＥＴ，ＶＭＯＳＦＥＴ，ＩＧＢＴであり、その他にＳＩＴ，ＢＪＴ，ＪＦＥＴも作成可能である。
【００８５】
【発明の効果】
以上詳述したように本発明によれば、埋め込み層に対して所定の電位を印加可能な構成としているので、オフ状態からオン状態へのスイッチング速度を向上させて動特性の改善をはかることができる。
【図面の簡単な説明】
【図１】埋め込み層を有する半導体装置の基本構造を示す断面図。
【図２】第１の実施形態に係わる半導体装置を説明するためのもので、埋め込み層の各種形状および配置を示す平面図。
【図３】４Ｈ−ＳｉＣの場合のビルトインポテンシャルによる空乏層面積を考慮した導電面積率対寸法率（間隔／幅）を示す図。
【図４】正規化耐圧及び正規化オン抵抗対寸法率（間隔／幅）との関係を示す図。
【図５】メッシュ構造のコンタクト領域を持ちその四角の中に四角，丸，六角形のを構造に並べる伝導層を持つ埋め込み層の構造を示す図。
【図６】ビルトイン電位を無視した場合の電導面積率の寸法率依存性を示す図。
【図７】ビルトイン電位を考慮した場合の電導面積率の寸法率依存性を示す図。
【図８】 メッシュ構造のコンタクト領域を持ちその四角の中に四角，丸，六角形を並べる伝導層を持つ埋め込み層の構造を示す図。
【図９】ＳＩＴ断面構造を示す図。
【図１０】ＳＩＴゲート構造上面図。
【図１１】動特性改善提案の構造を示す図。
【図１２】従来構造と動特性改善提案構造のトランジェント特性を示す図。
【図１３】チップ端の勾配に抵抗をつける構造を示す図。
【図１４】アクティブ領域の中にトレンチ構造で抵抗を付ける構造をショットキーダイオードに適用した構造を示す図。
【図１５】動特性改善構造の例（横型ＭＯＳＦＥＴ）を示す図。
【図１６】動特性改善構造の例（縦型ダイオード）を示す図。
【図１７】 動特性改善構造の例（横型ＭＯＳＦＥＴ）を示す図。
【図１８】埋め込み層と各種形状のコンタクト領域との関係を示す図。
【符号の説明】
１１，３１…ｎ⁺ 型基板
１２，２３…ｎ^- 型ドリフト層
１３…ショットキーコンタクト（アノード）
１４…カソード
１５，２２，４５…ｐ⁺ 型埋め込み層
２１…埋め込み層コンタクト領域
３２…ｎ^- 層
３３…ゲート
３４…ソース
４２…ｎ^- 層
４３…ショットキーコンタクト
４６…導電体[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor device, and more particularly to a semiconductor device in which a buried layer is provided in a drift layer.
[0002]
[Prior art]
In recent years, a structure in which a buried layer is provided in a drift layer between a first electrode and a second electrode has been adopted in a semiconductor device for electric power in order to further improve the withstand voltage (for example, patent document). 1 and 2).
[0003]
A typical structure of the buried layer will be described with reference to the example of the Schottky diode shown in FIG. n on the n-type substrate 11^-A type drift layer 12 is formed, an anode 13 by Schottky connection is formed on a part of the drift layer 12, and a cathode 14 is formed on the lower surface of the substrate 11. In the drift layer 12, p⁺A plurality of buried layers 15 of the mold are formed.
[0004]
  If the Schottky contact is provided on the anode side, in the ON state, electrons injected from the cathode 14 are n between the buried layers 15.^-It flows through the layer 12 and out to the anode 13. OffOhThe anode voltage from 0V(To negative bias side)When gradually increasing, the depletion layer first extends from the anode 13, and when the depletion layer reaches the first layer (counting 1, 2, 3,... From the anode side), the electric field distribution in the depletion layer is almost fixed. When the cathode voltage is further increased, the depletion layer starts to extend downward from the first buried layer. When this depletion layer reaches the second buried layer, the electric field distribution formed between the first layer and the second layer is substantially fixed, and the increase in the anode voltage further increases below the next buried layer. The anode voltage can be increased until a depletion layer is created below the bottom buried layer. That is, the breakdown voltage can be improved.
[0005]
However, this type of apparatus has the following problems. That is, n with a buried layer^-In the epitaxial structure, the on-resistance and breakdown voltage vary depending on the surface shape of the buried layer. In general, when the area of the buried layer is increased in a plane perpendicular to the direction of current flow, the breakdown voltage increases, but it is considered that the on-resistance increases accordingly. However, there is no description as to how the surface shape of the buried layer affects the on-resistance and the breakdown voltage, and therefore the optimum shape of the buried layer is not known.
[0006]
In addition, in order to determine the shape of the buried layer, it is necessary to consider the existence of a depletion layer due to a diffusion potential, but how this affects is not reported. Therefore, the optimum shape of the buried layer when this is taken into account is also unknown.
[0007]
On the other hand, when it is formed in a continuous shape, when an epitaxial layer is grown on the buried layer, the pattern swallowed below cannot be accurately recognized. For this reason, it is not easy to align the embedded layer and the upper layer. The only way to align was to etch the edges of each layer so that the alignment marks appeared on the surface.
[0008]
Further, it has been found that when the dynamic characteristic makes a transition from the off state to the on state, the current does not flow normally and the on-resistance temporarily increases rapidly. This is because the potential of the buried layer is n^-This is because it decreases due to minority carrier injection from the layer, the depletion layer width increases, and the buried layer is pinched off by the depletion layer, making it difficult for current to flow. As shown in FIG. 12, in the conventional structure, the on-voltage does not become close to 0V but shows an abnormally high value when it changes from off to on. This is a characteristic that is almost impossible to put into practical use.
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-330496
[0010]
[Patent Document 2]
JP 2000-101082 A
[0011]
[Problems to be solved by the invention]
Thus, although a structure in which a buried layer is provided in the drift layer has been proposed in the past, it has not yet been recognized what shape the buried layer should be. In particular, when a SiC material is used as the semiconductor element forming material, there is almost no literature on the shape and dimensions of the buried layer, and it has not been possible to satisfy both on-resistance and breakdown voltage.
[0012]
  In addition, this type of device having a buried layer has a structure in which the buried layer is electrically floating.a fewBy injecting carriers, the potential difference between the buried layer and the drift layer around it increases, and the width of the depletion layer extending from the buried layer to the drift layer increases. For this reason, there is a problem that the current value is lowered by narrowing the width of current conduction between the buried layers. In addition, when a depletion layer extending from an adjacent buried layer is connected, there is a problem that current does not flow. The switching characteristics of the device from off to onturnThere is a problem that the ON speed is lowered or does not turn ON.
[0014]
  The present invention has been made in consideration of the above circumstances, and its purpose is:Embedded layerButApply potential so as not to float electricallyTo doAnother object of the present invention is to provide a semiconductor device capable of improving the switching speed from the off state to the on state and reducing the on-resistance.
[0015]
[Means for Solving the Problems]
(Constitution)
In order to solve the above problems, the present invention adopts the following configuration.
[0017]
  That is, the present invention is a semiconductor device in which silicon carbide (SiC) is used as a constituent material and a buried layer having a conductivity type different from that of the drift layer is inserted in the drift layer between the first electrode and the second electrode. AndThe buried layer is disposed so as to divide the drift layer vertically; andThe buried layer is formed so as to have a plurality of openings that partially connect the drift layer between the front and back of the buried layer, and has any one of the following configurations (a) to (c): Features.
  (A) A voltage is applied to the buried layer by resistance division.
  (B) A voltage is applied to the buried layer through a resistor connected to the cathode as the second electrode.
  (C) A part of the drift layer on the anode side as the first electrode adjacent to the buried layer and the buried layer is electrically short-circuited.
[0018]
  Here, preferred embodiments of the present invention include the following.
  (1) The drift layer is n^-Type and buried layer is p⁺Be type.
  (2) In the rectifier structure, the first electrode isAnode with Schottky junctionAnd the second electrode isCathodeBe.
  (3) In the rectifying element, a resistance of the number of buried layers + 1 is connected in series between two electrodes, and a voltage is divided to apply a potential to the buried layer.
  (4) In the rectifying element, the same number of resistors as the number of buried layers are connected to the uppermost buried layer.CathodeConnect a resistor in series between the two and apply a potential divided by resistance to the buried layer.
[0019]
(5) The switching element has a switching structure on the surface, the first electrode is a source, and the second electrode is a drain.
(6) In switching elements, apply a potential by resistance division between the source and drain.
(7) In a switching element, apply a potential through a resistor between the drain and the buried layer.
(8) Have a structure that applies a potential to the buried layer.
(9) p⁺N around the buried layer^-Apply the same potential to the buried layer as the layer.
[0020]
  (10) Create a resistor at the edge or inside of the active area.
  (11) The structure for attaching the resistance is vertical or inclined.
  (12) The resistor is made of a p-type semiconductor.
  (13) P-type resistorIn polysiliconTo create.
  (14) Buried layer and n on it^-Electrically connect the layers.
  (15) Edge of buried layerInforming a resistance layer with a p-type ion implantation layer;
  (16) High resistance p-type polysilicon is formed at the end of the buried layer.
[0021]
(17) At the end of the buried layer, the buried layer and n above it^-Form a contact layer across the layers.
[0022]
  (18) A stripe-shaped buried layer contact region intersecting with the stripe-shaped buried layer is formed.
  (19) Form buried layer contact regions alternately having a length that intersects with the stripe-shaped buried layer.
  (20) A buried layer contact region is formed for each stripe-shaped buried layer.
  (21) The buried layer contact regions are located alternately.
  (22) Striped buried layerIsHave a contact pattern for the buried layer of the mesh.
  (23) Striped embedded layerIsHave a rectangular buried layer contact shape.
[0023]
(24) In the case of a rectifying element, the potential applied to the mth buried layer counted from the anode side is V_im, The total number of buried layers is M, and the potential difference between the anode and the cathode is V_ac, The anode potential is V_aV_m= V_a+ {M × V_ac/ (M + 1)} to apply a potential to the buried layer.
[0024]
(26) n^-Layer thickness 5μm, n^-Impurity concentration 2 × 10¹⁶cm^-3The buried layer structure has a buried layer width of 0.58 μm and a buried layer interval of 1.4 μm.
(27) n^-Layer thickness 5μm, n^-Impurity concentration 2 × 10¹⁶cm^-3The buried layer structure has a buried layer width of 0.6 μm and a buried layer interval of 1.6 μm.
(28) n^-Layer thickness 5μm, n^-Impurity concentration 2 × 10¹⁶cm^-3The buried layer structure has a buried layer width of 1 μm and a buried layer interval of 2 μm.
[0025]
(29) The region that is not a buried layer has a quadrangular mesh structure.
(30) It has a structure in which regions that are not buried layers are alternately arranged in a square shape.
(31) It has a structure in which regions that are not buried layers are alternately arranged in a round shape.
(32) The region which is not a buried layer has a structure shape in which hexagons are alternately arranged in hexagons.
(33) The buried layer contact region has a bowl shape.
[0026]
(34) The source has a stripe shape in the SIT structure.
(35) The SIT structure has a structure in which the sources are arranged in a square and mesh shape.
(36) The SIT structure has a structure in which the sources are arranged alternately in a square shape.
(37) The SIT structure has a structure in which the sources are arranged in a round shape alternately.
(38) The SIT structure has a structure in which the sources are alternately arranged in a hexagonal shape.
[0028]
  According to the present invention, the buried layer is formed, for example, in a mesh shape so as to have a plurality of openings that partially connect the drift layer between the front and back sides,By applying a voltage to the buried layer by resistance division, applying a voltage through a resistor connected to the cathode, or electrically short-circuiting the buried layer and a part of the drift layer on the anode side adjacent to the buried layer, In contrast, the embedded layer is not floating, and a predetermined potential is applied, which increases the switching speed from the off state to the on state, and improves the problem of dynamic characteristics.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Before describing embodiments of the invention, the basic concept of the present invention will be described.
[0030]
In order to guarantee a breakdown voltage, it is necessary to narrow the buried layer interval s, and to reduce the on-resistance, it is necessary to increase the ratio of the buried layer interval s to the width w as much as possible. Various surface shapes of the buried layer are conceivable, but no current contributing to the on-resistance flows in the buried layer, and current flows in a region other than the buried layer. Therefore, n between the buried layer and the buried layer^-The on-resistance of the layer will be higher than where there is no buried layer. Therefore, increasing the conductive area ratio (= surface area other than the embedded layer / surface area of the embedded layer) as much as possible within the range in which the voltage is ensured leads to a reduction in on-resistance, but it is unclear which surface shape is the best.
[0031]
Stripes, squares, circles, hexagons, etc. can be considered as the embedded shape, and mesh, alternating, etc. can be considered as the arrangement of the individual shapes. In the present invention, which shape is the optimal shape with the lowest resistance value, the conductive area ratio Derived by seeking. Further, since the depletion layer formed by the diffusion potential affects the conductivity, an optimum shape with the highest conductive area ratio is found in consideration of this depletion layer.
[0032]
  In addition, as described above, this type of device having a buried layer has a structure in which the buried layer is electrically floating, so that the on-speed of the device decreases from the off state to the on state in the switching characteristics. Or, there is a problem that the characteristics are not turned on. Therefore, in the present invention, the dynamic characteristics are improved by applying a potential so that the buried layer does not float electrically. For this purpose, a method and a structure for applying an external potential to a buried layer are provided. further,turnProvided is a buried layer shape effective for reducing on-resistance.
[0033]
The details of the present invention will be described below with reference to the illustrated embodiments.
[0034]
(First embodiment)
As the surface shape of the buried layer, as shown in FIG. 2, a stripe (a), a square mesh (b), a square alternate (c), a circle (d), and a hexagon (e) are examined. The minimum interval of the buried layer pattern is s, and the minimum width is w. Using s and w as parameters, an analytical expression for the conductive area ratio of each shape was obtained. It was found that the analytical expression for each shape is determined by the ratio of s and w.
[0035]
[Table 1]

[0036]
Here, since the depletion layer formed by the diffusion potential exists between the buried layers, the current path is narrowed and the resistance value is increased. Therefore, in order to obtain a more precise conductive area ratio, this depletion layer area is taken into consideration. . Diffusion potential V_biIs
V_bi= KT ln (n_n0p_p0/ N_i)
here,
k: Boltzmann coefficient
T: Absolute temperature
n_n0: Majority carrier density of n-type layer
p_p0: Majority carrier density in p-type layer
n_i: Intrinsic carrier density
It becomes.
[0037]
The one-dimensional depletion layer width created by the diffusion potential is p⁺And n^-Since the junction is a layer, the depletion layer is n^-Since it can be approximated to extend only to the layer,
w_bi= √ {2εV_bi/ (QN_n)}
here,
N_n: N^-Net impurity concentration of the layer
It is.
[0038]
The surface area of the depletion layer due to the diffusion potential reduces the conductive area, and the value shows the depletion layer area by shape assuming that the peripheral length of the embedded shape is multiplied by the one-dimensional depletion layer width.
[0039]
[Table 2]

[0040]
The depletion layer area varies depending on the shape. In addition, since the majority carrier density and intrinsic carrier density that determine the diffusion potential change depending on the band gap energy, materials having different band gap energy also affect the depletion layer area. The band gap energy and relative dielectric constant of each material are
[Table 3]

It is.
[0041]
Band gap energy from material and n^-Since the depletion layer area is affected by the impurity concentration of the layer, it is possible to obtain a more accurate value by calculating and correcting the conductive area ratio shown in (Table 1).
[0042]
Using the formula shown in Table 1, the horizontal axis represents the dimension ratio (interval / width) and the vertical axis represents the conductive area ratio when the embedded layer interval w = 0.5, 1, 5 μm, and FIG. ) To (c). Both are cases of 4H-SiC, (a) has a buried width w of 0.5 μm, (b) has w of 1 μm, and (c) has w of 5 μm. The structural condition is the case where 4H—SiC is used, and the upper n layer is formed by one buried layer.^-Both the n-layer and the underlying n- layer have an impurity concentration of 2 × 10¹⁶cm^-3The thickness is 5 μm.
[0043]
In any case, the round shape has the highest conductive area ratio, the square and the hexagon have the same value, and the stripe has the lowest value. When the dimension ratio is small, the conductive area ratio is 0, which means that the buried layer interval is smaller than the diffusion length, and the buried layer is filled with a depletion layer, and there is no path for current flow. To do.
[0044]
4 (a) and 4 (b) show the dimension ratio (s / w) on the horizontal axis and the breakdown voltage and on-resistance normalized on the basis of the ideal value on the vertical axis, respectively. When the size ratio increases, the breakdown voltage decreases, and when it decreases, the on-resistance increases. Regarding the on-resistance, when s = 0.6 μm, an extremely high on-resistance was shown, so that it is not shown in FIG.
[0045]
FIG. 4C shows the relationship between the normalized breakdown voltage and on-resistance. The optimum structure is that both the breakdown voltage and the on-resistance show good values, and the following three specific values are shown. This condition is that the impurity concentration of the epitaxial layer is 2 × 10.¹⁶cm^-3The unit epitaxial layer thickness is 5 μm and the structure is one buried layer.
[0046]
[Table 4]

[0047]
As for the consistency between each buried layer and the surface pattern, if a rectangular, round, or hexagonal isolated shape is used instead of a stripe, there is no problem even if the alignment is shifted, so that consistency can be obtained. In addition, if it is in an isolated shape, even if it comes into contact with the buried layer by chip dicing, it is electrically isolated from other buried layers, so that the problems of leakage and breakdown voltage degradation can be solved. Therefore, there is no need to increase the distance between the buried layer and the chip end as in the continuous shape, leading to a reduction in chip area and cost. In addition, since alignment is not necessary, the necessity of creating alignment marks and special processes is eliminated, and the cost can be reduced.
[0048]
Further, when an isolated buried layer is applied, it is not necessary to consider the dicing position, so that the buried layer can be formed on the entire surface of the wafer ignoring the chip area. Therefore, a wafer with a buried layer can be mass-produced, and the cost may be greatly reduced, which may be lower than the cost of the prior art.
[0049]
As described above, according to the present embodiment, by making the buried layer an isolated circle, the conductive area ratio can be increased and the on-resistance can be decreased. More specifically, regarding the round shape having the highest conductive area ratio as the shape of the buried layer, from FIG. 4A, when 1 ≦ s / w ≦ 2, s is 3 μm or less and a sufficiently large normalized breakdown voltage (Vbr > 0.75) was obtained. Further, when 2 <s / w ≦ 3, a sufficiently large normalized breakdown voltage (Vbr> 0.75) was obtained when s was 2 μm or less. Further, from FIG. 4B, when s / w was 1 or more, a low on-resistance of Ron ≦ 2 was obtained when s was 1 μm or more. Accordingly, a desirable range of the width w and the interval s of the circular buried layer is 1 ≦ s / w ≦ 2, 1 ≦ s ≦ 3, or 2 <s / w ≦ 3, 1 ≦ s ≦ 2.
[0050]
(Second Embodiment)
In the isolated shape described so far, the buried layer is formed in an isolated shape, and other regions are n^-It is layered. Where p⁺Buried layer and n^-We propose a structure in which the layer shape is reversed. The shape in this case is shown in FIGS. (A) is a quadrilateral mesh, (b) is a quadrangle alternate, (c) is a circle alternate, and (d) is a hexagonal alternate shape. When the depletion layer due to the diffusion potential is not taken into consideration, the conductive area ratio is as shown in (Table 5) below, and the dependence on the dimensional ratio is as shown in FIG. The area of the depletion layer due to the diffusion potential is shown in (Table 6), and the analytical expression of the conductive area ratio is shown in (Table 7).
[0051]
[Table 5]

[0052]
[Table 6]

[0053]
[Table 7]

[0054]
Moreover, the conductive area ratio versus the dimensional ratio with respect to the buried layer interval are shown in FIGS. (A) is the dimension dependence of the conductive area ratio of w = 0.5 μm, considering the built-in potential, (b) is the dimension dependence of the conductive area ratio of w = 1 μm, and (c) is the conductive area of w = 5 μm. It is the dimension dependence of the rate.
[0055]
In this case, the stripe had the highest conductive area ratio, the next square (alternately with the mesh), the next hexagon, and the lowest circle. It is expected that the conductive area ratio of the stripe is the highest and the resistance is the lowest, so p⁺Buried layer and n^-In a structure in which the layer shape is inverted, a stripe shape may be used.
[0056]
  8A to 8D are top views in the case of a circle or hexagon having a structure including a buried layer contact region for a dynamic characteristic improving structure. In FIG. 8, (a) has a contact area with a mesh structure, and a square is placed in the square.AlternatelyStructure of buried layer having conductive layers arranged side by side, (b) has a mesh-structured contact region and mesh-shaped buried layer in the square, and (c) has a mesh-structured contact region in the square. (D) shows a buried layer structure having a mesh-structured contact region and a conductive layer in which hexagons are alternately arranged in a square. In the figure, 21 is a buried layer contact region, 22 is p⁺Layer, 23 is n^-Shows the layer.
[0057]
This shape can be applied to the gate region and source region (conduction region) of SIT (Static Induction Transistor) in addition to the shape of the buried layer. The correspondence with the buried layer corresponds to the gate of SIT because the buried layer is not a conductive region, and the gap shape of the buried layer (n^-Since (shape) is a conductive region, it corresponds to the source shape (conductive shape) of SIT.
[0058]
FIG. 9 shows a schematic cross-sectional shape of the SIT. 31 in the figure is n⁺Mold substrate, 32 is n^-A layer 33 is a gate, and 34 is a source. The top view is shown in FIG. 10A shows a case of stripes, FIG. 10B shows a case of a square mesh, FIG. 10C shows a case of alternating squares, FIG. 10D shows a case of alternating circles, and FIG. 10E shows a case of alternating hexagons. In this case, since the gate has the highest conductive area ratio in a stripe shape, the resistance becomes the smallest.
[0059]
The gate is formed of a metal such as nickel having a Schottky contact. The source voltage is set to 0 V, and the drain voltage is set higher than the source voltage. When the gate voltage is lower than the threshold value, the depletion layer extending from the two gates sandwiching the source region to the n− layer is connected at the source region, and the source and drain are blocked by the depletion layer, thereby The current path is cut off, and the device state is turned off. When the gate voltage is equal to or higher than the threshold value, the depletion layer extending from the two gates sandwiching the source recedes and the two depletion layers are separated. As a result, there is n between the source and drain.^-By connecting through, an electric current flows and it turns on.
[0060]
Here, the gate is not a Schottky contact metal, but p⁺If formed of layers, it becomes a JFET. The operating principle is the same as SIT.
[0061]
(Third embodiment)
As a solution to the problem that the on-resistance rapidly increases without increasing the current when the dynamic characteristics are switched from OFF to ON, a voltage is applied to the buried layer. The semiconductor element has a structure as shown in FIG. 1, and the buried layer has an isolated rectangular shape.
[0062]
As a specific method, as shown in FIG. 11A, two resistors R1 and R2 are connected in series between a cathode and an anode, and a voltage is supplied to a buried layer from a connection node of the two resistors. 42 in the figure is n^-Layer, 43 is Schottky contact, 45 is p⁺It is a buried layer. The ratio of R1 and R2 is determined so that the supplied voltage value becomes the ideal voltage value of the buried layer. The relational expression is
Vu = 1 / (1 + R1 / R2) × Va
Vu: potential applied to the buried layer
Va: anode voltage
It becomes.
[0063]
Further, if R1 + R2 is too low, a leak current flows between the cathode and the anode, and power consumption at the time of off increases, so that a sufficiently high resistance value needs to be set. The leakage current value Ir due to this resistance is
Ir = Va / (R1 + R2)
It becomes.
[0064]
  Furthermore, if R1 + R2 is too high, the resistance will be reduced when off.throughThe amount of charge injected into the buried layer is n^-Since the majority carriers of the layer are lower than the amount injected into the buried layer, and the potential of the buried layer is not sufficiently close to the ideal potential, there is a possibility that the characteristics from off to on will not be improved. Therefore, it is necessary to select the resistance value so that the potential of the buried layer is sufficiently close to the ideal potential. The ideal potential of the buried layer when off is the sum of the voltages supported on the top of the layer. Mth n divided by the buried layer from top to bottom^-The voltage supported by the impurity concentration and thickness of the layer, respectively, N_m, T_m, V_mRepresented by Here, m is 1 to n^-Up to the number of divisions in the layer. If the total number of buried layers is M,
  V_m= QN t_m ²/ (2ε)
here,
  q: Single electron charge
  ε: dielectric constant
And the ideal potential Vu of the mth buried layer from the top_mIs
[Expression 1]

It becomes.
[0065]
The comparison result by simulation is shown in FIG. The dynamic characteristics of the conventional structure were investigated using a configuration in which R1 and R2 were removed from the configuration of FIG. FIG. 12 shows the transient characteristics of the conventional structure and the dynamic characteristic improving structure shown in FIG. It can be seen that the value of the output voltage Vout after the transition from OFF to ON is 100 V or more in the related art and is around 0 V in the improved structure, and the dynamic characteristics are greatly improved in the improved structure.
[0066]
In the conventional structure, the voltage of Vout once becomes abnormally high and slowly decreases due to the transition characteristic from off to on. This is because the on-resistance temporarily increases greatly. On the other hand, as a result of simulating the structure of the present embodiment with the circuit configuration of FIG. 11A, the Vout in the ON state is stable and low and shows normal dynamic characteristics, so the proposed structure reliably improves the structure. Proved to be.
[0067]
FIG. 11B shows a structure in which R1 is omitted from the configuration of FIG. 11A, and a potential is applied to the buried layer by connecting the buried layer and the cathode through a resistor R2. In the off state, the leakage current is cathode → R2 → buried layer → n above the buried layer.^-Since the current flows from the layer to the anode, the resistance of R2 is increased to keep the allowable leak value. Also, if the resistance value of R2 is too high, there will be a problem with the switching characteristics, so the setting is made so as to satisfy the allowable switching characteristics. FIG. 11 (c) shows the buried layer and n above it.^-This is a structure in which a potential is applied to the buried layer by electrically connecting the layers.
[0068]
In any of the configurations of FIGS. 11A to 11C, the buried layer is not floating, and a predetermined potential is applied. Therefore, the switching speed from the off state to the on state is increased, and the dynamic characteristics are improved. Can be measured.
[0069]
A specific device structure of the resistance application method will be described with reference to FIGS.
[0070]
  FIG. 13 shows an example in which an oblique side surface is formed at the end of an active region for forming a device, p-type polysilicon or p layer is formed as a resistance layer on the side surface, and a voltage is applied to the buried layer. 51 in the figure is n⁺Mold substrate, 52 is n^-Layer, 55 is p⁺Reference numeral 57 denotes a resistance layer, and reference numeral 58 denotes a metal contact. The p-type polysilicon or p layer as the resistance layer 57 is p⁺The buried layer 55 is electrically connected and n^-Layer 52 is in physical contact but not electrically connected, so n^-A voltage can be applied to the buried layer 52 by being insulated from the layer 52. At the bottom, make a metal contact⁺ThroughCathodeA voltage is applied. Vertical structures are created by etching.The resistance layer 57 isIn the case of p-type polysilicon, it is formed by LPCVD, and in the case of a p-layer, it is formed by ion implantation. The top of the resistance layer 57To anode voltageIf bias is applied, the application method of FIG.anodeIf the bias is eliminated, the application method shown in FIG.
[0071]
As in this embodiment, when there is a gradient, there is an advantage that polysilicon can be easily attached or a p layer can be easily formed by ion implantation. Gradient structures can also be created by etching.
[0072]
  FIG. 14 shows a structure in which a trench structure is formed in an active region for forming a device, and a Schottky contact 59 is deposited thereon to form a Schottky diode. In the lower part, a metal contact 58 is made and n⁺A cathode voltage is applied through layer 51. The trench structure is created by etching.The resistance layer 57 isIn the case of p-type polysilicon, it is formed by LPCVD, and in the case of a p-layer, it is formed by ion implantation. The top of the resistance layer 57To anode voltageIf bias is applied, the application method of FIG.anodeIf no bias is applied, the application method shown in FIG.
[0073]
The resistance layer for applying a potential to the buried layer is formed by ion implantation of an acceptor.^-You can create a layer. However, since this layer becomes a leakage current by connecting the cathode and the anode electrode, a high resistance is desired. When a resistance layer is formed by ion implantation, n^-N to invert the layer^-The impurity concentration at the same level as that of the layer is entered. If a resistance value higher than that is required, it becomes difficult to produce by ion implantation.
[0074]
As an alternative to this, p-type high resistance polysilicon is used for the resistance layer. The impurity concentration of polysilicon is n^-Any resistance can be realized because it can be determined independently of the layer. Also, by using p-type, n^-N is reverse biased with the layer^-Current from the layer to the polysilicon does not flow, and since the buried layer is the same p-type, it can be electrically connected, which is convenient.
[0075]
(Fourth embodiment)
As another dynamic characteristic improving structure, the potential of the buried layer is changed to n above it.^-A structure is proposed in which the same potential as the layers is electrically shorted. As a specific example of improved structure, FIG. 15 shows a structure in which a mesa is formed at the end of the buried layer and a metal layer for forming a short circuit is formed on the buried layer and a portion above the buried layer.
[0076]
If the buried layer and the lower n^-When shorted with layer, n below^-Layer → buried layer → n on^-Since a minute current flows from the layer to the gate and becomes a leakage current when a reverse bias is applied, power consumption is lost, which is not preferable. Therefore, it is proposed to have a structure in which the buried layer and the upper layer are short-circuited.
[0077]
Also in the present embodiment, since the buried layer is not floating and a predetermined potential can be applied to the buried layer, the same effect as in the third embodiment can be obtained. In this figure, the connection material is provided with a field plate function in the connection structure between the buried layer on the terminal mesa wall and the upper part thereof.
[0078]
  FIG. 16 shows the embodiment of FIG. 11C in which the potential application to the buried layer is performed in the trench structure. 61 in the figure is n⁺Mold substrate, 52 is n^-Layer, 65 is p⁺Layer, 67 is conductive material, 68 isInsulationReference numeral 69 denotes a Schottky contact. The conductive material 67 in the trench structure is made of, for example, metal or polysilicon, and the insulating material 68 is made of, for example, an oxide film. The conductive material 67 includes the buried layer 65 and the n on the buried layer 65.^-Located in a location that straddles the layer, the buried layer and n above it^-Electrically connect the layers.
  FIG. 17 shows an example in which the same principle as that of FIG. 15 is applied to a lateral MOSFET. In the figure, 71 is a substrate, 72 is n^-73, p layer, 74 source, 75 drain, 76 gate, and 77 metal layer. In the structure of FIGS. 16 and 17, the same effect as in FIG. 15 can be obtained.
[0079]
FIG. 17 shows an example in which the same principle as that of FIG. 15 is applied to a lateral MOSFET. In the figure, 71 is a substrate, 72 is n^-73, p layer, 74 source, 75 drain, 76 gate, and 77 metal layer. In the structure of FIGS. 16 and 17, the same effect as in FIG. 15 can be obtained.
[0080]
  (Fifth embodiment)
  FIGS. 18A to 18F show top views of the potential application structure at the end of the buried layer shown in FIGS. 13 and 14 as the dynamic characteristic improving structure. FIG. 18 (a) shows a stripe-shaped buried layer in a direction intersecting with it, straddling all the buried layers and parallel to each other at a certain interval.repeatIn this structure, the buried layer contact region is located. FIG. 18B shows a structure in which the buried layer contact structure is located across any number of buried layers. FIG. 18C shows an example in which a contact region is positioned for each buried layer.
[0081]
When there is a current leak due to a defect in the buried layer, FIG. 18A shows that all of the buried layer becomes defective, whereas FIG. 18B shows the length of the buried layer that becomes defective. Therefore, there is an effect that the decrease in yield can be reduced. FIG. 18 (c) is more effective.
[0082]
FIG. 18D has an effect of facilitating the process because the contact between the buried layer contact regions shown in FIG. FIG. 18 (e) shows a buried layer contact region having a grid shape in the case of a stripe-shaped buried layer. FIG. 18F shows an example in which the contact region of FIG.
[0083]
(Modification)
Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment.
[0084]
  For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined. P⁺Buried layer and n^-The layer can be combined with various elements. For example, a diode is a Schottky diode,PiNIt is a diode. When a MOSFET structure is created on the surface, DMOSFET, ACCUFET, UMOSFET, VMOSFET, and IGBT can be created, and SIT, BJT, and JFET can also be created.
[0085]
【The invention's effect】
  As detailed above, according to the present invention,Since a predetermined potential can be applied to the buried layer, the dynamic characteristics can be improved by improving the switching speed from the off state to the on state.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a basic structure of a semiconductor device having a buried layer.
FIG. 2 is a plan view for explaining the semiconductor device according to the first embodiment and showing various shapes and arrangements of buried layers.
FIG. 3 is a diagram showing a conductive area ratio versus a dimension ratio (interval / width) in consideration of a depletion layer area due to a built-in potential in the case of 4H—SiC.
FIG. 4 is a diagram showing the relationship between normalized withstand voltage and normalized on-resistance versus size ratio (interval / width).
FIG. 5 is a diagram showing a structure of a buried layer having a contact region having a mesh structure and having a conductive layer in which squares, circles, and hexagons are arranged in the square.
FIG. 6 is a diagram showing the dimensional ratio dependence of the conductive area ratio when the built-in potential is ignored.
FIG. 7 is a diagram showing a dimensional ratio dependency of a conductive area ratio in consideration of a built-in potential.
[Figure 8] Has a mesh-structured contact area with squares, circles, and hexagons inside the squaresTheThe figure which shows the structure of the embedding layer which has the conductive layer to arrange.
FIG. 9 is a diagram showing a SIT cross-sectional structure.
FIG. 10 is a top view of a SIT gate structure.
FIG. 11 is a diagram showing a structure of a dynamic characteristic improvement proposal.
FIG. 12 is a diagram showing transient characteristics of a conventional structure and a dynamic characteristic improvement proposed structure.
FIG. 13 is a diagram showing a structure for applying resistance to the gradient at the tip end.
FIG. 14 is a diagram showing a structure in which a structure in which resistance is added in a trench structure in an active region is applied to a Schottky diode.
FIG. 15 is a diagram showing an example of a dynamic characteristic improving structure (lateral MOSFET).
FIG. 16 is a diagram showing an example of a dynamic characteristic improving structure (vertical diode).
FIG. 17The figure which shows the example (lateral MOSFET) of a dynamic characteristic improvement structure.
FIG. 18 is a diagram showing the relationship between a buried layer and contact regions of various shapes.
[Explanation of symbols]
11, 31 ... n⁺Mold substrate
12, 23 ... n^-Type drift layer
13 ... Schottky contact (anode)
14 ... Cathode
15, 22, 45 ... p⁺Mold embedding layer
21: buried layer contact region
32 ... n^-layer
33 ... Gate
34 ... Source
42 ... n^-layer
43 ... Schottky contact
46. Conductor

Claims (9)

A semiconductor device comprising silicon carbide (SiC) as a constituent material, and a buried layer having a conductivity type different from that of the drift layer inserted in a drift layer between the first electrode and the second electrode,
The buried layer is arranged so as to divide the drift layer vertically , and the buried layer is formed with a plurality of openings that partially connect the drift layer between the front and back of the buried layer,
In order to apply a voltage by resistance division to the buried layer, a first resistor is provided between the buried layer and the first electrode, and a second resistor is provided between the buried layer and the second electrode. A semiconductor device including a resistor. A semiconductor device comprising silicon carbide (SiC) as a constituent material, and a buried layer having a conductivity type different from that of the drift layer inserted in a drift layer between the first electrode and the second electrode,
The buried layer is arranged so as to divide the drift layer vertically , and the buried layer is formed with a plurality of openings that partially connect the drift layer between the front and back of the buried layer,
A semiconductor device comprising a resistor for electrically connecting the buried layer and the second electrode in order to apply a predetermined voltage to the buried layer. A semiconductor device comprising silicon carbide (SiC) as a constituent material, and a buried layer having a conductivity type different from that of the drift layer inserted in a drift layer between the first electrode and the second electrode,
The buried layer is arranged so as to divide the drift layer vertically , and the buried layer is formed with a plurality of openings that partially connect the drift layer between the front and back of the buried layer,
In order to apply a predetermined voltage to the buried layer, an electrode for electrically short-circuiting the buried layer and a part of the drift layer on the first electrode side adjacent to the buried layer is provided. Semiconductor device.   The semiconductor device according to claim 1, wherein the buried layer is formed in a mesh shape.   The semiconductor device according to claim 1, wherein the openings are arranged in a matrix at a constant pitch or in a staggered pattern in an in-plane direction of the buried layer.   6. The semiconductor device according to claim 1, wherein the pattern of the opening is a quadrangle, a circle, or a hexagon.   3. The semiconductor device according to claim 1, wherein the resistor is a semiconductor layer having the same conductivity type as that of the buried layer provided on a side surface of the drift layer and the buried layer.   The semiconductor device according to claim 1, wherein the first electrode is an anode by Schottky junction, and the second electrode is a cathode.   The semiconductor device according to claim 1, wherein the first electrode is a source of a MOS type switching element, and the second electrode is a drain.

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