JP3857400B2 - 自己変更コードの競合を検出するマイクロプロセッサ及びこのマイクロプロセッサを動作させる方法 - Google Patents

自己変更コードの競合を検出するマイクロプロセッサ及びこのマイクロプロセッサを動作させる方法 Download PDF

Info

Publication number
JP3857400B2
JP3857400B2 JP32372397A JP32372397A JP3857400B2 JP 3857400 B2 JP3857400 B2 JP 3857400B2 JP 32372397 A JP32372397 A JP 32372397A JP 32372397 A JP32372397 A JP 32372397A JP 3857400 B2 JP3857400 B2 JP 3857400B2
Authority
JP
Japan
Prior art keywords
address
fetch
write
fetch address
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32372397A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10187440A (ja
JPH10187440A5 (cg-RX-API-DMAC7.html
Inventor
イー．シュタイス ドナルド
ディー．アンダーソン ティモシー
アガルワラ サンジブ
Original Assignee
テキサス インスツルメンツ インコーポレイテツド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by テキサス インスツルメンツ インコーポレイテツド filed Critical テキサス インスツルメンツ インコーポレイテツド
Publication of JPH10187440A publication Critical patent/JPH10187440A/ja
Publication of JPH10187440A5 publication Critical patent/JPH10187440A5/ja
Application granted granted Critical
Publication of JP3857400B2 publication Critical patent/JP3857400B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
JP32372397A 1996-10-21 1997-10-20 自己変更コードの競合を検出するマイクロプロセッサ及びこのマイクロプロセッサを動作させる方法 Expired - Fee Related JP3857400B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2929996P 1996-10-21 1996-10-21
US029299 1996-10-21

Publications (3)

Publication Number Publication Date
JPH10187440A JPH10187440A (ja) 1998-07-21
JPH10187440A5 JPH10187440A5 (cg-RX-API-DMAC7.html) 2005-06-30
JP3857400B2 true JP3857400B2 (ja) 2006-12-13

Family

ID=21848318

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32372397A Expired - Fee Related JP3857400B2 (ja) 1996-10-21 1997-10-20 自己変更コードの競合を検出するマイクロプロセッサ及びこのマイクロプロセッサを動作させる方法

Country Status (2)

Country Link
US (1) US6009516A (cg-RX-API-DMAC7.html)
JP (1) JP3857400B2 (cg-RX-API-DMAC7.html)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6405307B1 (en) * 1998-06-02 2002-06-11 Intel Corporation Apparatus and method for detecting and handling self-modifying code conflicts in an instruction fetch pipeline
JP3739607B2 (ja) * 1999-08-24 2006-01-25 富士通株式会社 情報処理装置
US6363336B1 (en) * 1999-10-13 2002-03-26 Transmeta Corporation Fine grain translation discrimination
US7065096B2 (en) * 2000-06-23 2006-06-20 Mips Technologies, Inc. Method for allocating memory space for limited packet head and/or tail growth
US7082552B2 (en) 2000-02-08 2006-07-25 Mips Tech Inc Functional validation of a packet management unit
US7155516B2 (en) 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7165257B2 (en) * 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US7139901B2 (en) * 2000-02-08 2006-11-21 Mips Technologies, Inc. Extended instruction set for packet processing applications
US7058065B2 (en) * 2000-02-08 2006-06-06 Mips Tech Inc Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
US7649901B2 (en) 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US7058064B2 (en) 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US7502876B1 (en) 2000-06-23 2009-03-10 Mips Technologies, Inc. Background memory manager that determines if data structures fits in memory with memory state transactions map
US7076630B2 (en) * 2000-02-08 2006-07-11 Mips Tech Inc Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management
US20010052053A1 (en) * 2000-02-08 2001-12-13 Mario Nemirovsky Stream processing unit for a multi-streaming processor
US7042887B2 (en) 2000-02-08 2006-05-09 Mips Technologies, Inc. Method and apparatus for non-speculative pre-fetch operation in data packet processing
US7032226B1 (en) 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US6938148B2 (en) * 2000-12-15 2005-08-30 International Business Machines Corporation Managing load and store operations using a storage management unit with data flow architecture
US20030093775A1 (en) * 2001-11-14 2003-05-15 Ronald Hilton Processing of self-modifying code under emulation
US7868894B2 (en) * 2006-11-28 2011-01-11 International Business Machines Corporation Operand multiplexor control modifier instruction in a fine grain multithreaded vector microprocessor
US8250336B2 (en) * 2008-02-25 2012-08-21 International Business Machines Corporation Method, system and computer program product for storing external device result data
US8103850B2 (en) * 2009-05-05 2012-01-24 International Business Machines Corporation Dynamic translation in the presence of intermixed code and data
CN102141905B (zh) * 2010-01-29 2015-02-25 上海芯豪微电子有限公司 一种处理器体系结构
US20110320784A1 (en) * 2010-06-24 2011-12-29 International Business Machines Corporation Verification of processor architectures allowing for self modifying code
WO2014016651A1 (en) * 2012-07-27 2014-01-30 Freescale Semiconductor, Inc. Circuitry for a computing system, LSU arrangement and memory arrangement as well as computing system
US9229745B2 (en) 2012-09-12 2016-01-05 International Business Machines Corporation Identifying load-hit-store conflicts
US9436624B2 (en) * 2013-07-26 2016-09-06 Freescale Semiconductor, Inc. Circuitry for a computing system, LSU arrangement and memory arrangement as well as computing system
US9477516B1 (en) 2015-03-19 2016-10-25 Google Inc. Concurrent in-memory data publication and storage system
CN106933537B (zh) * 2016-04-20 2019-03-08 上海兆芯集成电路有限公司 侦测自修正程序码的处理器与方法
US9798669B1 (en) * 2016-04-20 2017-10-24 Via Alliance Semiconductor Co., Ltd. System and method of determining memory ownership on cache line basis for detecting self-modifying code
CN106933538B (zh) * 2016-04-20 2019-03-01 上海兆芯集成电路有限公司 侦测自修正程序码的处理器与方法
CN106919367B (zh) * 2016-04-20 2019-05-07 上海兆芯集成电路有限公司 侦测自修正程序码的处理器与方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728690A (en) * 1971-08-26 1973-04-17 Honeywell Inf Systems Branch facility diagnostics
JPS5245232A (en) * 1975-10-08 1977-04-09 Hitachi Ltd Micro program modification circuit
US4573119A (en) * 1983-07-11 1986-02-25 Westheimer Thomas O Computer software protection system
WO1985000453A1 (en) * 1983-07-11 1985-01-31 Prime Computer, Inc. Data processing system
US5255369A (en) * 1984-03-10 1993-10-19 Encore Computer U.S., Inc. Multiprocessor system with reflective memory data transfer device
DE3802025C1 (cg-RX-API-DMAC7.html) * 1988-01-25 1989-07-20 Otto 7750 Konstanz De Mueller
US5125083A (en) * 1989-02-03 1992-06-23 Digital Equipment Corporation Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system
JP2682264B2 (ja) * 1991-05-21 1997-11-26 日本電気株式会社 プログラムカウンタ装置
GB2258069B (en) * 1991-07-25 1995-03-29 Intel Corp High speed computer graphics bus
JP2771374B2 (ja) * 1991-12-27 1998-07-02 茨城日本電気株式会社 プロセッサのページ越処理方式
US5692167A (en) * 1992-07-31 1997-11-25 Intel Corporation Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor
US5434987A (en) * 1993-09-21 1995-07-18 Intel Corporation Method and apparatus for preventing incorrect fetching of an instruction of a self-modifying code sequence with dependency on a bufered store
US5636374A (en) * 1994-01-04 1997-06-03 Intel Corporation Method and apparatus for performing operations based upon the addresses of microinstructions
US5564028A (en) * 1994-01-11 1996-10-08 Texas Instruments Incorporated Pipelined data processing including instruction trace
US5568631A (en) * 1994-05-05 1996-10-22 International Business Machines Corporation Multiprocessor system with a shared control store accessed with predicted addresses
US5640526A (en) * 1994-12-21 1997-06-17 International Business Machines Corporation Superscaler instruction pipeline having boundary indentification logic for variable length instructions
JPH08263424A (ja) * 1995-03-20 1996-10-11 Fujitsu Ltd コンピュータ装置
US5826073A (en) * 1995-10-06 1998-10-20 Advanced Micro Devices, Inc. Self-modifying code handling system
US5742791A (en) * 1996-02-14 1998-04-21 Advanced Micro Devices, Inc. Apparatus for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor

Also Published As

Publication number Publication date
JPH10187440A (ja) 1998-07-21
US6009516A (en) 1999-12-28

Similar Documents

Publication Publication Date Title
JP3857400B2 (ja) 自己変更コードの競合を検出するマイクロプロセッサ及びこのマイクロプロセッサを動作させる方法
JP3907809B2 (ja) 複合分岐予測およびキャッシュ先取りをするマイクロプロセッサ
US5913049A (en) Multi-stream complex instruction set microprocessor
US6430674B1 (en) Processor executing plural instruction sets (ISA's) with ability to have plural ISA's in different pipeline stages at same time
US6021485A (en) Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
JP2846406B2 (ja) 分岐処理方法及び分岐処理装置
JP2846407B2 (ja) 例外処理方法及び例外処理装置
US7065632B1 (en) Method and apparatus for speculatively forwarding storehit data in a hierarchical manner
US6481251B1 (en) Store queue number assignment and tracking
US6321326B1 (en) Prefetch instruction specifying destination functional unit and read/write access mode
EP3171264B1 (en) System and method of speculative parallel execution of cache line unaligned load instructions
JPH0526219B2 (cg-RX-API-DMAC7.html)
EP1244962A1 (en) Scheduler capable of issuing and reissuing dependency chains
KR100309309B1 (ko) 단일클록사이클동안슈퍼스칼라프로세서에서복수의저장인스트럭션완료를용이하게하는방법및시스템
JPH10111800A (ja) 分岐解決方法、プロセッサ、及びシステム
US7571283B2 (en) Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatch
US8549235B2 (en) Method for detecting address match in a deeply pipelined processor design
US6266767B1 (en) Apparatus and method for facilitating out-of-order execution of load instructions
KR20010077997A (ko) 단일 사이클 파이프라인 기능 정지를 발생하기 위한파이프라인 프로세서 시스템 및 방법
US20100031011A1 (en) Method and apparatus for optimized method of bht banking and multiple updates
US6289428B1 (en) Superscaler processor and method for efficiently recovering from misaligned data addresses
KR20000005685A (ko) 분산인스트럭션완료로직
US6675287B1 (en) Method and apparatus for store forwarding using a response buffer data path in a write-allocate-configurable microprocessor
US5895497A (en) Microprocessor with pipelining, memory size evaluation, micro-op code and tags
JPH0418648A (ja) キャッシュを有するデータ処理装置及びそのデータアクセス方法

Legal Events

Date Code Title Description
A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041020

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041020

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060210

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060214

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20060515

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20060518

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060814

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060908

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060914

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100922

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110922

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120922

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130922

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees