JP3856619B2 - Semiconductor device, liquid crystal display device, manufacturing method of semiconductor device, and manufacturing method of liquid crystal display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, a manufacturing method thereof, a liquid crystal display device, and a manufacturing method thereof, and more specifically, a semiconductor device including a thin film field effect transistor and a capacitor region adjacent to the thin film field effect transistor, and a manufacturing method thereof. And a liquid crystal display device and a manufacturing method thereof.
[0002]
[Prior art]
Conventionally, a liquid crystal display device using a thin film field effect transistor is known as one of liquid crystal display devices. FIG. 53 is a schematic plan view showing a conventional liquid crystal display device, and shows a display pixel region of the liquid crystal display device. FIG. 54 is a schematic cross-sectional view showing a conventional liquid crystal display device, which shows a cross section taken along line 500-500 in FIG. 53 and a drive circuit region of the liquid crystal display device shown in FIG. A conventional liquid crystal display device will be described with reference to FIGS.
[0003]
53 and 54, the liquid crystal display device includes a display pixel region and a drive circuit region. In the display pixel region, a base film 102 composed of a two-layer film of a silicon nitride film and a silicon oxide film is formed on the glass substrate 101. A thin film field effect transistor for pixel 136 and a capacitor 137 are formed on the base film.
[0004]
On the base film 102, n ⁺ Type impurity regions 103a, 103b, 103h, n type impurity regions 104a to 104d and n ^- A semiconductor film in which type impurity regions 105a to 105e, channel regions 106a and 106b, and a capacitor electrode 109 are formed is formed. On this semiconductor film, an insulating film 107 that functions as a gate insulating film of the pixel thin film field effect transistor 136 and a dielectric film of the capacitor 137 is formed. On the insulating film 107, the gate electrode 108a of the pixel thin film field effect transistor 136 is formed in a region located on the channel regions 106a and 106b. A capacitor electrode 108 b as an upper electrode of the capacitor 137 is formed in a region located on the capacitor electrode 109 on the insulating film 107. Thus, n as the source / drain region ⁺ Type impurity regions 103a, 103b, 103h, n type impurity regions 104a to 104d and n ^- The pixel thin film field effect transistor 136 is composed of the type impurity regions 105a to 105d, the channel regions 106a and 106b, the insulating film 107 as a gate insulating film, and the gate electrode 108a. The capacitor 137 includes a capacitor electrode 109 as a lower electrode, an insulating film 107 as a dielectric film, and a capacitor electrode 108b as an upper electrode.
[0005]
An interlayer insulating film 110 is formed on the gate electrode 108a and the capacitor electrode 108b. N of interlayer insulating film 110 ⁺ Contact holes 111a and 111b are formed in regions located on the type impurity regions 103a and 103h. Metal interconnections 112a and 112b are formed so as to extend from the inside of contact holes 111a and 111b to the upper surface of interlayer insulating film 110. A passivation film (not shown) is formed on the metal wirings 112a and 112b, and a planarization film 113 is formed on the passivation film. A contact hole 114 is formed in the planarizing film 113 and the passivation film. A pixel electrode 115 electrically connected to the metal wiring 112b is formed so as to extend from the inside of the contact hole 114 to the upper surface of the planarization film 113. An alignment film 116 a is formed on the pixel electrode 115.
[0006]
An upper glass substrate 117 is disposed so as to face the substrate 101 on which the pixel thin film field effect transistor 136 and the capacitor 137 are formed. A color filter 118 is disposed on the surface of the upper glass substrate 117 facing the glass substrate 101. A counter electrode 119 is formed on the surface of the color filter 118 facing the glass substrate 101. An alignment film 116 b is formed on the surface of the counter electrode 119 facing the glass substrate 101. A liquid crystal 120 is injected and sealed in a region sandwiched between the alignment film 116a and the alignment film 116b.
[0007]
In the drive circuit region of the liquid crystal display device, a base film 102 composed of a two-layer film of a silicon nitride film and a silicon oxide film is formed on the glass substrate 101 as in the display pixel region. A p-type thin film field effect transistor 138 and an n type thin film field effect transistor 139 constituting a drive circuit are formed on the base film 102.
[0008]
A semiconductor film including p-type impurity regions 127 a and 127 b which are source / drain regions of the p-type thin film field effect transistor 138 and a channel region 106 d is formed on the base film 102. On this semiconductor film, an insulating film 107 is formed which becomes a gate insulating film of a p-type thin film field effect transistor. A gate electrode 108 c is formed in a region located on the channel region 106 d on the insulating film 107. The gate electrode 108c, the insulating film 107 as a gate insulating film, the p-type impurity regions 127a and 127b, and the channel region 106d constitute a p-type thin film field effect transistor 138. Further, on the base film 102, n which is a source / drain region of the n-type thin film field effect transistor 139 is formed. ⁺ Type impurity regions 103e, 103f and n type impurity regions 104e, 104f and n ^- A semiconductor film including the type impurity regions 105f and 105g and the channel region 106c is formed. An insulating film 107 to be a gate insulating film of the n-type thin film field effect transistor 139 is formed on the semiconductor film. On the insulating film 107, a gate electrode 108d is formed in a region located on the channel region 106c. The gate electrode 108d, the insulating film 107, the channel region 106c, and n ⁺ Type impurity regions 103e, 103f and n type impurity regions 104e, 104f and n ^- An n-type thin film field effect transistor 139 is composed of the type impurity regions 105f and 105g. An interlayer insulating film 110 is formed on the gate electrodes 108c and 108d. Interlayer insulating film 110 and insulating film 107 include p-type impurity regions 127a, 127b and n ⁺ Contact holes 111d to 111g are formed in regions located above the type impurity regions 103e and 103f, respectively. Metal interconnection 112c is formed to extend from the inside of contact hole 111d to the upper surface of interlayer insulating film 110. Metal wiring 112d is formed to extend from the inside of contact holes 111e and 111f to the upper surface of interlayer insulating film 110. Metal wiring 112e is formed to extend from the inside of contact hole 111g to the upper surface of interlayer insulating film 110. A passivation film is formed on the metal wirings 112c to 112e, and a planarization film 113 is formed on the passivation film. An upper glass substrate 117 is disposed so as to face the glass substrate 101, and a liquid crystal 120 is injected and sealed between the upper glass substrate 117 and the glass substrate 101.
[0009]
Next, a manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54 will be described with reference to FIGS. 55 to 62 are schematic plan views for explaining the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54, and FIGS. 63 to 72 show the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. It is a cross-sectional schematic diagram for demonstrating. The schematic plan views shown in FIGS. 55 to 62 are schematic plan views of the region 200 in FIG. Further, the display pixel region in the schematic cross-sectional views shown in FIGS. 63 to 72 corresponds to the cross-sectional schematic diagram in the line segment 500-500 in FIG.
[0010]
First, in the display pixel region and the drive circuit region, a base film 102 (see FIG. 63) composed of a two-layer film of a silicon oxide film and a silicon nitride film is formed on a glass substrate 101 (see FIG. 63). An amorphous silicon film 122 is formed on the base film 102 using a CVD (Chemical Vapor Deposition) method. Then, as shown in FIG. 63, laser annealing is performed by irradiating the amorphous silicon film 122 with laser light. In this way, the amorphous silicon film 122 is turned into polysilicon.
[0011]
Next, as shown in FIG. 55, the source / drain regions and channel regions 106a and 106b (see FIG. 54) of the pixel thin film field effect transistor 136 and the capacitor electrode 109 (see FIG. 54) should be formed in the display pixel region. In order to form the polysilicon film 125a (see FIG. 64), a resist film 123 is formed on the polysilicon film obtained by converting the amorphous silicon film 122 into polysilicon. By using this resist film 123 as a mask, the polysilicon film is partially removed to form a polysilicon film 125a. At the same time, in the driving circuit region of the liquid crystal display device, a polysilicon film 125b (see FIG. 5) to become the p-type impurity regions 127a and 127b and the channel region 106d of the p-type thin film field effect transistor 138 on the polysilicon film. 64) and a polysilicon film to be the source / drain regions of the n-type thin film field effect transistor 139 and the channel region 106c are formed by the same method.
[0012]
Next, an insulating film 107 (see FIG. 64) is formed on the polysilicon films 125a to 125c. As shown in FIGS. 56 and 64, resist films 124a to 124c having a predetermined pattern are formed on the insulating film 107 using a photoengraving technique. The resist film 124a is formed on a region where the gate electrode 108a of the pixel thin film field effect transistor 136 is to be formed. The resist film 124b is formed so as to cover a region where the p-type thin film field effect transistor 138 is to be formed in the drive circuit region. The resist film 124c is formed on a region where the gate electrode 108d of the n-type thin film field effect transistor 139 is to be formed. Then, as shown in FIG. 64, n-type conductive impurities are implanted into a predetermined region of the polysilicon film by using the resist films 124a to 124c as masks. ⁺ Type impurity regions 103a, 103b, 103e to 103g and channel regions 106a to 106c are formed. Thereafter, the resist films 124a to 124c are removed.
[0013]
Next, a conductor film (not shown) to be the gate electrodes 108 a, 108 c, 108 d and the capacitor electrode 108 b is formed on the insulating film 107. As shown in FIG. 57, in the display pixel region, a resist film 142 is formed on the conductive film so as to cover the region where the pixel thin film field effect transistor 136 and the capacitor 137 are to be formed using a photoengraving technique. To do. At this time, in the drive circuit region, another resist film is formed on the region where the gate electrode 108c of the p-type thin film field effect transistor 138 is to be formed, and the n-type thin film field effect transistor 139 is to be formed at the same time. Another resist film is formed so as to cover the region. The conductive film is partially removed by etching using the resist film 142 as a mask, so that the conductive film extending over the region where the pixel thin film field effect transistor 136 and the capacitor 137 are to be formed as shown in FIG. The body membrane 126a can be obtained. The planar shape of the conductor film 126a is substantially the same as the planar shape of the resist film 142 shown in FIG. In this etching step, a conductor film 126b (see FIG. 65) is formed so as to cover a region where the n-type thin film field effect transistor 139 is to be formed in the drive circuit region. In this etching step, the gate electrode 108c (see FIG. 65) of the p-type thin film field effect transistor 138 is formed.
[0014]
Next, as shown in FIG. 66, p-type impurity regions 127a and 127b are formed by implanting boron (B) ions into the polysilicon film using the conductor films 126a and 126b and the gate electrode 108c as a mask. In this boron ion implantation process, the conductor films 126a and 126b act as masks, so that the polysilicon film 125a to be the source / drain region and the channel region of the capacitor electrode 109 and the pixel thin film field effect transistor 136 is not formed. Boron ions are not implanted.
[0015]
Next, as shown in FIGS. 67 and 58, resist films 129a to 129d are formed on the conductor films 126a and 126b and the gate electrode 108c by using a photolithography technique. At this time, the resist film 129a is formed on the region where the gate electrode 108a of the thin film field effect transistor 136 for pixels is to be formed. The resist film 129b is formed on the region where the capacitor electrode 108b of the capacitor 137 is to be formed. The resist film 129d is formed on a region where the gate electrode 108d of the n-type thin film field effect transistor 139 is to be formed. The resist film 129c is formed to cover the p-type thin film field effect transistor 138. Next, the conductive films 126a and 126b are partially removed using the resist films 129a to 129d as a mask, thereby forming gate electrodes 108a and 108d and a capacitor electrode 108b (see FIG. 68).
[0016]
Then, as shown in FIG. 68, by implanting phosphorus (P) ions into a predetermined region of the polysilicon film, n-type impurity regions 104a to 104f and n ⁺ A type impurity region 103h is formed. Here, the widths of the resist films 129a and 192d are formed to be smaller than the widths of the resist films 124a and 124c in FIG. Therefore, in the step shown in FIG. 68, phosphorus ions can be implanted into a region where phosphorus ions are not implanted by the phosphorous ion implantation step shown in FIG. 64 (region adjacent to the gate electrodes 108a and 108d). In this manner, the regions into which phosphorus ions are implanted for the first time in the process shown in FIG. 68 are n-type impurity regions 104a to 104f. Further, in the above-described etching process, the etching is performed so that the side surfaces of the gate electrodes 108a and 108d are set back from the positions of the side surfaces of the resist films 129a and 129d. This can be easily performed by adjusting the etching conditions such as wet etching in the etching process and overetching the conductor films 126a and 126b. Then, after the phosphorus ion implantation step shown in FIG. 68, the resist films 129a to 129d are removed.
[0017]
Next, as shown in FIG. 69, low-concentration phosphorus ions are implanted into a predetermined region of the polysilicon film using the gate electrodes 108a and 108d and the capacitor electrode 108b as a mask. Here, as described above, since the widths of the gate electrodes 108a and 108d are smaller than the widths of the resist films 129a and 129d, a region in which phosphorus ions are implanted is generated for the first time in the phosphorus ion implantation step shown in FIG. . In the step shown in FIG. 69, the region where low concentration phosphorus ions are first implanted is n. ^- The type impurity regions 105a to 105g are formed.
[0018]
Next, as shown in FIG. 70, an interlayer insulating film 110 is formed on the gate electrodes 108a, 108c, 108d and the capacitor electrode 108b.
[0019]
Next, as shown in FIG. 59, a resist film 130 having a predetermined pattern is formed on the interlayer insulating film 110 by using a photolithography technique. In the resist film 130, openings 131a and 131b are formed in regions where contact holes 111a and 111b (see FIG. 71) are to be formed, respectively. By using this resist film 130 as a mask, interlayer insulating film 110 and insulating film 107 are partially removed by etching to form contact holes 111a and 111b (see FIG. 71). Similarly, openings are formed in the resist film 130 in regions where contact holes 111d to 111g are to be formed in the drive circuit region. For this reason, the contact holes 111d to 111g are formed in the drive circuit region by the etching process for forming the contact holes 111a and 111b described above. Thereafter, the resist film 130 is removed.
[0020]
Next, a metal film (not shown) is formed on the interlayer insulating film 110. This metal film is formed so as to extend from the upper surface of the interlayer insulating film 110 to the inside of the contact holes 111a, 111b, 111d to 111g. On this metal film, as shown in FIG. 60, resist films 132a and 132b having a predetermined pattern are formed on regions where metal wirings 112a to 112e are to be formed using a photoengraving technique. Referring to FIG. 60, resist film 132a is formed on a region where metal interconnection 112a is to be formed. The resist film 132b is formed on the region where the metal wiring 112b is to be formed. Using the resist films 132a and 132b as a mask, the metal film is partially removed by etching, thereby forming metal wirings 112a and 112b. In the drive circuit region, metal wirings 112c to 112e are formed by the same process. Thereafter, the resist films 132a and 132b are removed. In this way, a structure as shown in FIG. 71 is obtained.
[0021]
Next, a passivation film (not shown) is formed on the metal wirings 112a to 112e. A planarizing film 113 (see FIG. 72) is formed on the passivation film. A resist film 133 (see FIG. 61) having a predetermined pattern is formed on the planarizing film 113 using a photolithography technique.
[0022]
Referring to FIG. 61, opening 134 is formed in resist film 133 in the region where contact hole 114 (see FIG. 72) of planarization film 113 is to be formed. By using this resist film 133 as a mask, the planarizing film 113 and the passivation film are partially removed by etching, thereby forming a contact hole 114. Thereafter, the resist film 133 is removed.
[0023]
Next, a transparent conductor film (not shown) to be a transparent electrode is formed so as to extend from the upper surface of the planarizing film 113 to the inside of the contact hole 114. A resist film 135 is formed on the transparent conductor film using a photoengraving technique as shown in FIG. The resist film 135 is formed on a region where the pixel electrode 115 is to be formed. The transparent conductive film is partially removed using the resist film 135 as a mask to obtain the pixel electrode 115 (see FIG. 72). Thereafter, the resist film 135 is removed. In this way, a structure as shown in FIG. 72 is obtained.
[0024]
Thereafter, an alignment film 116a is formed on the pixel electrode 115, and an upper glass substrate 117 (see FIG. 54) including the color filter 118, the counter electrode 119, and the alignment film 116b is prepared. The upper glass substrate 117 is arranged so as to face the glass substrate 101, and the liquid crystal 120 is injected and sealed between the upper glass substrate 117 and the glass substrate 101, whereby the liquid crystal display shown in FIGS. A device can be obtained.
[0025]
[Problems to be solved by the invention]
The conventional liquid crystal display device as described above has the following problems. That is, in the boron implantation process shown in FIG. 66, the conductor film 126a is used as a protective film for preventing unnecessary boron ions from being implanted into the polysilicon film 125a. Then, as shown in FIGS. 58 and 67, the conductor film 126a is separated into the gate electrode 108a and the capacitor electrode 108b by etching using the resist films 129a and 129b as masks. In this case, the step of etching the portion of the conductor film 126a located between the gate electrode 108a and the capacitor electrode 108b is only the above-described etching step. In this etching process, there is a pattern defect in the resist films 129a and 129b due to foreign matters adhering to the substrate surface or foreign matters in the resist, specifically, foreign matters exist between the resist film 129a and the resist film 129b. As a result, pattern defects such as the separation of the resist films 129a and 129b may occur. When such defects in the resist films 129a and 129b occur, a part of the conductor film 126a remains after etching between the gate electrode 108a and the capacitor electrode 108b. As a result, the gate electrode 108a and the capacitor electrode 108b Sometimes short-circuited. The occurrence of such a short circuit has been a major cause of a decrease in manufacturing yield of liquid crystal display devices.
[0026]
The present invention has been made to solve the above-described problems, and one object of the present invention is a semiconductor including a thin film field effect transistor and a capacitor formed adjacent to the thin film field effect transistor. It is an object of the present invention to provide a semiconductor device capable of preventing the occurrence of defects such as a short circuit between a gate electrode and a capacitor electrode of the thin film field effect transistor and a method for manufacturing the same.
[0027]
Another object of the present invention is to provide a liquid crystal display device comprising a thin film field effect transistor and a capacitor formed adjacent to the thin film field effect transistor, and comprising a gate electrode of the thin film field effect transistor and a capacitive electrode of the capacitor. It is to provide a liquid crystal display device capable of preventing the occurrence of defects such as a short circuit therebetween and a method for manufacturing the same.
[0028]
[Means for Solving the Problems]
A semiconductor device according to one aspect of the present invention is a semiconductor device including a thin film field effect transistor formed on a transparent substrate and a capacitance region adjacent to the thin film field effect transistor, and the thin film field effect transistor is a transparent substrate. A semiconductor film is formed including a channel region and a conductive region adjacent to the channel region. The capacitance region includes a lower electrode formed on the transparent substrate, and an upper electrode formed to face the lower electrode and having an opening. Further, the semiconductor device is formed on the conductive region and the upper electrode, has an upper surface, reaches a first contact hole from the upper surface to the conductive region, and reaches from the upper surface to the lower electrode. An insulating film in which a second contact hole is formed, and a connection extending from the inside of the first and second contact holes to the upper surface of the insulating film and connecting the conductive region and the lower electrode of the capacitor region And a conductor film.
[0029]
As described above, since the connection conductor film is provided, even if the semiconductor film and the lower electrode are formed separately as shown in the manufacturing method described later, the conductive region and the lower electrode of the semiconductor film are formed by the connection conductor film. Can be reliably connected electrically. For this reason, it is used as a protective film for preventing unnecessary conductive impurities from being injected into the semiconductor film and the lower electrode in the manufacturing process described later, and on the gate electrode and the capacitor region of the thin film field effect transistor. When forming a conductor film for forming an electrode, it is possible to completely separate a portion located on the semiconductor film and a portion located on the lower electrode. Then, if the gate electrode and the upper electrode are formed by etching the conductor film again, the region located between the gate electrode of the thin film field effect transistor and the upper electrode of the capacitor region is etched at least twice. Will receive. Therefore, even if a pattern defect occurs in the resist film due to the influence of impurities or the like in one of the two etching processes, the gate electrode can be formed if a pattern with a predetermined shape is formed in the other etching process. The region between the upper electrode and the upper electrode is etched. As a result, it is possible to reduce the probability of occurrence of a defect such as a short circuit between the gate electrode and the upper electrode of the capacitor region. Thereby, the manufacturing yield of the semiconductor device can be improved.
[0030]
In the semiconductor device according to the first aspect, it is preferable that the second contact hole reaches the lower electrode from the upper surface of the insulating film through the opening of the upper electrode.
[0031]
As described above, when the opening is formed in the upper electrode and the second contact hole in which the connection conductor film is formed is formed through the opening, the connection between the connection conductor film and the lower electrode of the capacitor region is formed. In order to secure the region, it is not necessary to extend the lower electrode to a region that is located outside the region where the lower electrode is formed and does not overlap with the upper electrode in plan view. For this reason, it is not necessary to unnecessarily increase the area occupied by the lower electrode of the capacitor region, so that the semiconductor device can be easily highly integrated.
[0032]
In the semiconductor device according to the first aspect, the opening of the upper electrode is preferably a recess in the planar outer shape of the upper electrode.
[0033]
In this case, a recess is formed in the planar outer shape of the upper electrode, and the second contact hole for forming the connection conductor film is formed through the recess, so that an opening is formed in the upper electrode. Similarly, in order to secure a connection region between the second contact hole and the lower electrode, it is not necessary to extend the lower electrode outward from the region where the lower electrode is to be formed. As a result, the area occupied by the capacity region can be reduced.
[0034]
In addition, when the opening is formed in the upper electrode by using wet etching or the like, the opening is not formed in the etching process, or it occurs with a probability that there is an etching defect such that the shape of the opening is different from the predetermined shape. . However, in etching that forms a recess in the planar outer shape of the upper electrode, the etching failure that occurs when the opening is formed does not occur. For this reason, it can prevent that the manufacturing yield of a semiconductor device falls due to the above defects.
[0035]
Further, a step portion is formed on the upper surface of the insulating film due to the presence of the upper electrode. However, since the second contact hole is formed so as to pass through the concave portion in the planar outer shape of the upper electrode, the second contact hole is located in the peripheral portion in the planar outer shape of the upper electrode. For this reason, the connection conductor film can be formed so as to extend into the second contact hole through a region that does not overlap the upper electrode in plan view. That is, the connection conductor film can be prevented from being formed on the step portion on the upper surface of the insulating film due to the presence of the upper electrode. As a result, it is possible to prevent the occurrence of defects such as disconnection of the connection conductor film due to the presence of the stepped portion.
[0036]
In the semiconductor device according to the first aspect or the other aspect, it is preferable that the lower electrode is formed of the same layer as the semiconductor film and formed separately from the semiconductor film.
[0037]
In this case, as shown in the manufacturing method described later, the semiconductor film and the lower electrode are formed separately, so that a mask for preventing unnecessary conductive impurities from being implanted into the semiconductor film and the lower electrode. The conductor film for forming the gate electrode of the thin film field effect transistor and the upper electrode of the capacitor region is completely separated into a part located on the semiconductor film and a part located on the lower electrode The two conductor films can be formed using an etching process (first etching process). Then, if the gate electrode and the upper electrode are formed by re-etching the two conductor films (second etching step), the gap between the gate electrode of the thin film field effect transistor and the upper electrode of the capacitor region The conductor film portion located at is subjected to at least two etchings of the first and second etching steps. Therefore, even if a pattern failure occurs in the resist film due to the influence of impurities or the like in one of the two etching steps, if a pattern having a predetermined shape is formed in the other etching step of the two times, The conductor film located in the region between the gate electrode and the upper electrode is subjected to etching. As a result, it is possible to reduce the probability of occurrence of a defect such as a short circuit between the gate electrode and the upper electrode of the capacitor region due to the remaining conductive film located in the region between the gate electrode and the upper electrode due to etching failure. it can. Thereby, the manufacturing yield of the semiconductor device can be improved.
[0038]
In the semiconductor device according to the first aspect or the other aspect, the lower electrode may be formed of the same layer as the conductor film and may be formed in contact with the semiconductor film (claim 5).
[0039]
In this case, since the semiconductor film in which the conductive region is formed and the lower electrode are configured by the same layer, no step is formed in the connection portion between the semiconductor film and the lower electrode. For this reason, in the region located on the connection portion between the semiconductor film and the lower electrode, a step due to the connection portion between the semiconductor film and the upper electrode is not formed on the upper surface of the insulation film, and the upper surface of the insulation film is not formed. It can be a relatively flat shape. As a result, when the connection conductor film is formed in the region on the connection portion between the conductor film and the lower electrode, it is possible to prevent the occurrence of defects such as disconnection of the connection conductor film due to the step.
[0040]
In the semiconductor device according to the first aspect or the other aspect, the conductivity type of the thin film field effect transistor is preferably n-type.
[0041]
In this case, since the n-type thin film field effect transistor has higher carrier mobility than the p-type thin film field effect transistor, a thin film field effect transistor having a high operation speed can be realized. If such a semiconductor device according to the present invention is applied to a display pixel or the like of a liquid crystal display device having a thin film field effect transistor and a capacitor region, the manufacturing yield in the liquid crystal display device can be improved and at the same time high response can be achieved. realizable.
[0042]
A liquid crystal display device according to another aspect of the present invention includes the semiconductor device according to the first aspect or the other aspect (claim 7).
[0043]
In this case, the semiconductor device according to the present invention includes the thin film field effect transistor and the capacitor region adjacent to the thin film field effect transistor as described above, and this structure is similar to the structure of the display pixel region of the liquid crystal display device. Applicable. Thus, by applying the semiconductor device according to the present invention to a liquid crystal display device, the yield of the liquid crystal display device can be improved.
[0044]
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method, a first thin film field effect transistor, a second thin film field effect transistor having a conductivity type different from the first thin film field effect transistor, A method of manufacturing a semiconductor device comprising a capacitor region adjacent to a thin film field effect transistor, the first semiconductor film to be a conductive region of the first thin film field effect transistor on the substrate, and a second thin film field effect A lower layer preparation step for forming the second semiconductor film including the conductive region of the transistor and the lower electrode of the capacitor region is performed. A step of forming an upper conductor film to be the gate electrode of the first and second thin film field effect transistors and the upper electrode of the capacitance region on the first and second semiconductor films and the lower electrode is performed. . In the upper conductor film, a region to be the gate electrode of the first thin film field effect transistor, a region located on the second semiconductor film, and a region located on the lower electrode and on the second semiconductor film Forming a resist film on each of the regions spaced apart from each other. By partially removing the conductor film by etching using the resist film as a mask, the gate electrode of the first thin film field effect transistor, the first remaining conductor film located on the second semiconductor film, A step of forming a second remaining conductor film located on the lower electrode at a distance from the one remaining conductor film is performed. The resist film is removed. A step of injecting conductive impurities into the first semiconductor film is performed using the gate electrode of the first thin film field effect transistor and the first and second remaining conductor films as a mask. After injecting conductive impurities into the first semiconductor film, one resist film is formed on the first remaining conductor film on the region where the gate electrode of the second thin film field effect transistor is to be formed; The step of forming the other resist film on the region where the upper electrode is to be formed on the remaining conductive film 2 and spaced apart from the one resist film and where the upper electrode of the capacitance region is to be formed is performed. An upper layer for forming the gate electrode of the second thin film field effect transistor and the upper electrode of the capacitor region by partially removing the first and second remaining conductor films by etching using one and the other resist films as a mask. A preparatory step is carried out (claim 8).
[0045]
In this case, the upper conductor in the region located between the first remaining conductor film and the second remaining conductor film by etching in the step of forming the first and second remaining conductor films. The film undergoes a first etch. The gate electrode of the second thin film field effect transistor is formed from the first remaining conductor film, and the upper electrode of the capacitor region is formed by partially etching the second remaining conductor film. That is, in the upper layer preparation step, a region located between the first remaining conductor film and the second remaining conductor film (positioned between the gate electrode of the second thin film field effect transistor and the upper electrode of the capacitor region). Region) undergoes a second etching. That is, the portion of the upper conductor film located between the gate electrode of the second thin film field effect transistor and the upper electrode of the capacitor region is subjected to etching twice. Therefore, even if a pattern defect due to impurities on the substrate or the like occurs in the resist film in one of the two etching processes, the pattern of the resist film in the other etching process of the two times has a predetermined shape. If so, the gate electrode of the second thin film field effect transistor and the upper electrode of the capacitor region can be formed separately. That is, it is possible to prevent a short circuit from occurring between the gate electrode of the second thin film field effect transistor and the upper electrode of the capacitor region. For this reason, the fall of the manufacturing yield of the semiconductor device resulting from the said short circuit can be prevented.
[0046]
In the method for manufacturing a semiconductor device according to another aspect, it is preferable that an opening is formed in the upper electrode of the capacitor region in the upper layer preparation step. Furthermore, a step of forming an upper insulating film so as to extend from the conductive region of the second thin film field effect transistor to the upper electrode of the capacitor region, and in the upper insulating film, the conductive layer is conductive from the upper surface of the upper insulating film. A first contact hole reaching the region is formed, and a second contact hole reaching the lower electrode of the capacitor region from the upper surface of the upper insulating film through the opening of the upper electrode of the capacitor region is formed. Extending from the inside of the first contact hole to the inside of the second contact hole via the upper surface of the upper insulating film, and the conductive region of the second thin film field effect transistor and the lower electrode of the capacitor region, And a step of forming a connection conductor film for electrically connecting the two.
[0047]
In this case, since the connecting conductor film is in contact with the lower electrode of the capacitor region through the opening of the upper electrode, the lower electrode is formed in order to secure a connecting region between the connecting conductor film and the lower electrode of the capacitor region. There is no need to extend the lower electrode to a region that is located outside the formed region and does not overlap the upper electrode in plan view. For this reason, the area of the region occupied by the capacitor region can be reduced. As a result, it becomes easier to miniaturize the semiconductor device.
[0048]
In the method for manufacturing a semiconductor device according to another aspect described above, it is preferable that a recess is formed in the planar outer shape of the upper electrode of the capacitor region in the upper layer preparation step. Furthermore, a step of forming an upper insulating film so as to extend from the conductive region of the second thin film field effect transistor to the upper electrode of the capacitor region, and in the upper insulating film, from the upper surface of the upper insulating film to the conductive region And a second contact hole reaching from the upper surface of the upper insulating film to the lower electrode of the capacitor region through the recess in the planar shape of the upper electrode of the capacitor region Extending from the inside of the first contact hole to the inside of the second contact hole through the upper surface of the upper insulating film, and the lower electrode of the conductive region and the capacitor region of the second thin film field effect transistor And a step of forming a connection conductor film that electrically connects the two.
[0049]
In this case, since the connection conductor film is in contact with the lower electrode through the concave portion of the planar outer shape of the upper electrode, the second contact hole and the lower electrode are formed in the same manner as in the case where the opening is formed in the upper electrode. In order to secure the connection region, it is not necessary to extend the lower electrode outward from the region where the lower electrode is to be formed. For this reason, the area occupied by the capacitor region can be reduced. As a result, the semiconductor device can be easily miniaturized.
[0050]
Further, in the etching process for forming the opening in the upper electrode, a defect such that the shape of the opening is deviated from a predetermined shape or the opening is not formed occurs. However, in the etching for forming the concave portion having the planar outer shape of the upper electrode, the above-described defects hardly occur. For this reason, it is possible to prevent a decrease in the manufacturing yield of the semiconductor device due to the defective opening.
[0051]
Further, a step portion is formed on the upper surface of the insulating film due to the presence of the upper electrode, but the second contact hole is formed so as to pass through the concave portion in the planar outer shape of the upper electrode. These contact holes are located in the peripheral portion of the planar outline of the upper electrode. For this reason, the connection conductor film can be formed so as to extend into the second contact hole through a region that does not overlap the upper electrode in plan view. That is, the connection conductor film can be prevented from being formed on the step portion on the upper surface of the insulating film due to the presence of the upper electrode. As a result, it is possible to prevent the occurrence of defects such as disconnection of the connection conductor film due to the presence of the stepped portion.
[0052]
In the method for manufacturing a semiconductor device according to another aspect described above, it is preferable to use wet etching in the upper layer preparation step.
[0053]
In this case, in the wet etching, the etching amount can be changed more accurately by controlling the etching time and the like. As a result, high processing accuracy can be realized.
[0054]
In the method for manufacturing a semiconductor device according to the another aspect, it is preferable that the second semiconductor film and the lower electrode are formed with a gap in the lower layer preparation step.
[0055]
As described above, the second semiconductor film and the lower electrode are formed at a distance from each other, so that the first and second remaining conductor films are stacked in the step of injecting the conductive impurities into the first semiconductor film. Even if they are formed at intervals, it is possible to prevent the semiconductor film and a part of the lower electrode from being located under the gap between the first and second remaining conductor films. For this reason, in the step of injecting conductive impurities into the first semiconductor film, the conductive impurities are not injected into the semiconductor film and the lower electrode. As a result, it is possible to prevent the deterioration of the electrical characteristics of the semiconductor device due to the unnecessary implantation of conductive impurities into the first semiconductor film and the lower electrode.
[0056]
In the method for manufacturing a semiconductor device according to the another aspect, in the lower layer preparation step, the second semiconductor film and the lower electrode may be formed to be in contact with each other by the same layer.
[0057]
In this case, when a gap is formed between the second semiconductor film and the lower electrode, a step is generated in a region located between the second semiconductor film and the lower electrode. If the second semiconductor film and the lower electrode are formed in contact with each other, the above step does not occur. For this reason, if a connection conductor film for electrically connecting the conductive region of the second thin film field effect transistor and the lower electrode is formed on the region between the second semiconductor film and the lower electrode, this is the case. It is possible to prevent the occurrence of defects such as disconnection of the connecting conductor film due to a large step.
[0058]
In the method for manufacturing a semiconductor device according to the other aspect described above, the conductivity type of the second thin film field effect transistor is preferably n-type.
[0059]
Here, since the n-type thin film field effect transistor has higher carrier mobility than the p-type thin film field effect transistor, the operation speed can be improved. A semiconductor device obtained by the method for manufacturing a semiconductor device according to the present invention includes a second thin film field effect transistor and a capacitor region adjacent to the second thin film field effect transistor. Such a structure has a liquid crystal display device. Used in the display pixel region. In the display pixel region of the liquid crystal display device, a high response characteristic is required in the thin film field effect transistor in order to improve the display characteristics of the liquid crystal display device. Therefore, if the method for manufacturing a semiconductor device according to the present invention is applied to a method for manufacturing a display pixel region of such a liquid crystal display device, the manufacturing yield can be improved and the display characteristics of the liquid crystal display device can be improved. it can.
[0060]
A method for manufacturing a liquid crystal display device according to still another aspect of the present invention uses the method for manufacturing a semiconductor device according to another aspect described above (claim 15).
[0061]
In this way, the manufacturing yield of the liquid crystal display device can be improved.
[0062]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
[0063]
(Embodiment 1)
FIG. 1 is a schematic plan view showing Embodiment 1 of a liquid crystal display device according to the present invention. FIG. 1 shows a display pixel region of the liquid crystal display device. FIG. 2 is a schematic cross-sectional view showing the first embodiment of the liquid crystal display device according to the present invention, in which a cross-section of the display pixel region in the line segment 100-100 in FIG. The cross section in is shown. The liquid crystal display device will be described with reference to FIGS.
[0064]
Referring to FIGS. 1 and 2, in a display pixel region of a liquid crystal display device, a base film 2 composed of a two-layer film of a silicon nitride film and a silicon oxide film is formed on a glass substrate 1. On the base film 2, a pixel thin film field effect transistor 36 and a capacitor 37 are formed at a distance from the pixel thin film field effect transistor 36.
[0065]
On the base film 2, n which is a source / drain region as a conductive region ⁺ Type impurity regions 3a-3c, n type impurity regions 4a-4d and n ^- A semiconductor film having type impurity regions 5a to 5d and channel regions 6a and 6b is formed. On the semiconductor film, an insulating film 7 to be a gate insulating film is formed. On the insulating film 7, a gate electrode 8a made of a metal film is formed in a region located on the channel regions 6a and 6b. Gate electrode 8a and insulating film 7 as a gate insulating film and n ⁺ Type impurity regions 3a to 3c, n type impurity regions 4a to 4d, n ^- The pixel type thin film field effect transistor 36 is composed of the type impurity regions 5a to 5d and the channel regions 6a and 6b.
[0066]
In addition, n on the underlayer 2 ⁺ Type impurity regions 3d and n ^- A lower electrode 9 of the capacitor 37 including the type impurity regions 5e and 5f is formed. An insulating film 7 as a dielectric film is formed on the lower electrode 9. On the insulating film 7, an upper electrode 8 b as an upper electrode is formed in a region located on the lower electrode 9. An opening 21 is formed in the upper electrode 8b. An interlayer insulating film 10 is formed on the gate electrode 8a and the upper electrode 8b. n ⁺ Contact holes 11a to 11c are formed in the insulating film 7 and the interlayer insulating film 10 in regions located on the type impurity regions 3a, 3c, and 3d. The contact hole 11c extends from the upper surface of the interlayer insulating film 10 through the opening 21 of the upper electrode 8b. ⁺ It is formed so as to reach the type impurity region 3d. n ⁺ Metal interconnection 12a is formed so as to be electrically connected to type impurity region 3a and to extend from the inside of contact hole 11a onto the upper surface of interlayer insulating film 10. Further, it extends from the inside of the contact hole 11b as the first contact hole and the contact hole 11c as the second contact hole to the upper surface of the interlayer insulating film 10, and n as the conductive region ⁺ Type impurity region 3c and n of lower electrode 9 ⁺ A metal wiring 12b is formed as a connection conductor film connecting the type impurity region 3d. A passivation film (not shown) is formed on the metal wirings 12a and 12b. A planarizing film 13 is formed on the passivation film. In the planarizing film 13, a contact hole 14 is formed in a region located on the opening 21 of the upper electrode 8b. A pixel electrode 15 made of a transparent conductor extending from the inside of the contact hole 14 to the upper surface of the planarizing film 13 and electrically connected to the metal wiring 12b is formed. An alignment film 16 a is formed on the pixel electrode 15.
[0067]
The upper glass substrate 17 is disposed so as to face the glass substrate 1 on which the pixel thin film field effect transistor 36 and the capacitor 37 are formed. A color filter 18 is formed on the surface of the upper glass substrate 17 facing the glass substrate 1. A counter electrode 19 is formed on the surface of the color filter 18 facing the glass substrate 1. An alignment film 16 b is formed on the surface of the counter electrode 19 facing the glass substrate 1. A liquid crystal 20 is injected and sealed between the alignment film 16a and the alignment film 16b.
[0068]
In the drive circuit region, a base film 2 made of a silicon nitride film and a silicon oxide film is formed on the glass substrate 1. A p-type thin film field effect transistor 38 and an n-type thin film field effect transistor 39 are formed on the base film 2. The n-type thin film field effect transistor 39 and the p-type thin film field effect transistor 38 constitute a part of the drive circuit.
[0069]
A semiconductor film including p-type impurity regions 27 a and 27 b and a channel region 6 c is formed on the base film 2. On this semiconductor film, an insulating film 7 to be a gate insulating film is formed. On the insulating film 7, a gate electrode 8c is formed in a region located on the channel region 6c. A p-type thin film field effect transistor 38 is constituted by the gate electrode 8c, the insulating film 7 as a gate insulating film, the channel region 6c, and the p-type impurity regions 27a and 27b.
[0070]
In the drive circuit region, a channel region 6d and n as source / drain regions are formed on the base film 2. ⁺ Type impurity regions 3e, 3f, n type impurity regions 4e, 4f and n ^- A semiconductor film including the type impurity regions 5g and 5h is formed. An insulating film 7 as a gate insulating film is formed on the semiconductor film. On the insulating film 7, a gate electrode 8d is formed in a region located on the channel region 8d. Gate electrode 8d, insulating film 7 as a gate insulating film, channel region 6d, and n as a source / drain region having an LDD structure ⁺ Type impurity regions 3e, 3f, n type impurity regions 4e, 4f and n ^- An n-type thin film field effect transistor 39 is constituted by the type impurity regions 5g and 5h.
[0071]
An interlayer insulating film 10 is formed on the gate electrodes 8c and 8d. p-type impurity regions 27a, 27b and n ⁺ In regions located above the type impurity regions 3e and 3f, contact holes 11d to 11g are formed by removing portions of the insulating film 7 and the interlayer insulating film 10. Metal interconnection 12c is formed to extend from the inside of contact hole 11d to the upper surface of interlayer insulating film 10. Extending from the inside of contact hole 11e to the inside of contact hole 11f through the upper surface of interlayer insulating film 10, p-type impurity region 27b and n ⁺ Metal interconnection 12d is formed to electrically connect type impurity region 3e. Extending from the inside of the contact hole 11g to the upper surface of the interlayer insulating film 10, n ⁺ Metal interconnection 12e electrically connected to type impurity region 3f is formed. A passivation film (not shown) is formed on the metal wirings 12c to 12e, and a planarizing film 13 is formed on the passivation film. The upper glass substrate 17 is disposed so as to face the glass substrate 1 on which the p-type thin film field effect transistor 38 and the n-type thin film field effect transistor 39 are formed. A liquid crystal 20 is injected and sealed in a region between the upper glass substrate 17 and the glass substrate 1.
[0072]
Here, as can be seen from FIGS. 1 and 2, the channel regions 6a and 6b of the pixel thin film field effect transistor 36 and n as the conductive region are used. ⁺ The semiconductor film having the type impurity region 3c and the lower electrode 9 of the capacitor 37 are formed of the same layer as is apparent from the manufacturing process described later, and are formed separately so as to form a gap therebetween. ing. For this reason, as shown in the manufacturing process described later, it is used as a mask for preventing unnecessary conductive impurities from being implanted into the semiconductor film and the lower electrode 9, and the gate of the n-type thin film field effect transistor 36. Etching process as a conductor film for forming the electrode 8a and the upper electrode 8b of the capacitor 37 as two conductor films completely separated into a part located on the semiconductor film and a part located on the lower electrode 9 It can be formed using (first etching step). Then, if the gate electrode 8a and the upper electrode 8b are formed by etching the two conductor films again (second etching step), the upper side of the gate electrode 8a and the capacitor 37 of the thin film field effect transistor 36 is formed. The conductor film portion located between the electrodes 8b is subjected to at least two etchings, the first and second etching steps. Therefore, even if a pattern failure occurs in the resist film due to the influence of impurities or the like in one of the two etching steps, if a pattern having a predetermined shape is formed in the other etching step of the two times, The conductor film located in the region between the gate electrode 8a and the upper electrode 8b is subjected to etching. As a result, the probability of occurrence of a defect such as a short circuit between the gate electrode 8a and the upper electrode 8b of the capacitor 37 due to the remaining conductive film located in the region between the gate electrode 8a and the upper electrode 8b due to etching failure is reduced. Can be reduced.
[0073]
N ⁺ Since the type impurity region 3c and the lower electrode 9 are electrically connected by the metal wiring 12b, this n ⁺ The electrical connection between the type impurity region 3c and the lower electrode 9 can be reliably performed.
[0074]
Further, the contact hole 11c where the metal wiring 12b is connected to the lower electrode 9 is formed from the upper surface of the interlayer insulating film 10 through the opening 21 formed in the upper electrode 8b. ⁺ It is formed so as to reach the type impurity region 3d. For this reason, in order to form the connection part of this metal wiring 12b and the lower electrode 9, it is not necessary to form the lower electrode 9 so that it may extend outside the area | region in which the upper electrode 8b was formed. As a result, the area of the region occupied by the capacitor 37 can be reduced.
[0075]
Moreover, although the conductivity type of the pixel thin film field effect transistor 36 is n-type, such an n-type thin film field effect transistor has higher carrier mobility than a p-type thin film field effect transistor. For this reason, in the display pixel region where high response characteristics are required to improve the display characteristics of the liquid crystal, the n-type thin film field effect transistor as shown in the first embodiment of the present invention is replaced with the thin film field effect transistor for pixels. The use as 36 is particularly effective.
[0076]
Next, a manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 to 10 are schematic plan views for explaining a method of manufacturing the liquid crystal display device shown in FIGS. 1 and 2, and show a region 200 in FIG. 11 to 20 are schematic cross-sectional views for explaining a method of manufacturing the liquid crystal display device shown in FIGS. 1 and 2, and correspond to the schematic cross-sectional view shown in FIG.
[0077]
First, a base film 2 (see FIG. 11) composed of a two-layer film of a silicon nitride film and a silicon oxide film is formed on a glass substrate 1 (see FIG. 11). An amorphous silicon film 22 (see FIG. 11) is formed on the base film 2. Then, as shown in FIG. 11, a laser annealing process is performed by irradiating the amorphous silicon film 22 with laser light. By this laser annealing process, the amorphous silicon film 22 is turned into polysilicon.
[0078]
Next, resist films 23 a and 23 b having a predetermined shape as shown in FIG. 3 are formed on the polysilicon film of the amorphous silicon film 22. By using the resist films 23a and 23b as masks, the polysilicon film obtained by forming the amorphous silicon film 22 into polysilicon is partially removed by etching, whereby channel regions 6a, 6b and n ⁺ A semiconductor film in which type impurity regions 3 a to 3 c and the like are to be formed and a semiconductor film to be the lower electrode 9 are formed. The planar shape of the semiconductor film in which the channel regions 6a, 6b and the like are to be formed is almost equal to the planar shape of the resist film 23a shown in FIG. 3, and the planar shape of the semiconductor film to be the lower electrode 9 is as shown in FIG. The planar shape of the resist film 23b shown in FIG. Also in the drive circuit region, a polysilicon film 25b (FIG. 25), which is a semiconductor film in which the channel region 6c and the p-type impurity regions 27a and 27b are to be formed from a film obtained by converting the amorphous silicon film 22 into polysilicon by the same process. 12) and a semiconductor film in which the channel region 6d is to be formed.
[0079]
Next, after removing the resist film, an insulating film 7 (see FIG. 12) is formed on the semiconductor film. Next, as shown in FIGS. 4 and 12, resist films 24 a to 24 c having a predetermined shape are formed on the insulating film 7. Here, the resist film 24a is formed on a region where the gate electrode 8a (see FIG. 2) is to be formed. The resist film 24b is formed so as to cover a region where the p-type thin film field effect transistor 38 is to be formed in the drive circuit region. The resist film 24c is formed on a region where the gate electrode 8d (see FIG. 2) of the n-type thin film field effect transistor 39 (see FIG. 2) is to be formed. Then, using the resist films 24a to 24c as masks, phosphorus ions are implanted into a predetermined region of the semiconductor film as shown in FIG. By this phosphorus ion implantation, n ⁺ Type impurity regions 3a-3c, 3e, 3f and lower electrode 9 are formed. Since phosphorus ions are not implanted into the regions located under the resist films 24a, 24c, channel regions 6a, 6b, 6d are formed in the semiconductor film regions located under the resist films 24a, 24c. Thereafter, the resist films 24a to 24c are removed.
[0080]
Next, a conductor film (not shown) made of a metal film or the like to be the gate electrodes 8a, 8c, 8d and the upper electrode 8b is formed on the insulating film 7. Resist films 28a and 28b having a pattern as shown in FIG. 5 are formed on this conductor film. In the drive circuit region, a resist film (not shown) is formed in each of a region located on the gate electrode 8c of the p-type thin film field effect transistor and a region covering the region where the n-type thin film field effect transistor 39 is located. Form. Then, the conductor film is removed by etching using the resist films 28a and 28b as a mask. Here, referring to FIG. 5, resist film 28 a is formed so as to cover a region where pixel thin film field effect transistor 36 in the display pixel region is to be formed. The resist film 28b is formed so as to cover a region where the lower electrode 9 (see FIG. 2) is to be formed. Then, after the etching process is finished, the resist films 28a and 28b and the resist film formed in the drive circuit region are removed. As a result, a structure as shown in FIG. 13 is obtained.
[0081]
Referring to FIG. 13, a conductor film 26 a as a first remaining conductor film is formed on insulating film 7 in a region where pixel thin film field effect transistor 36 is to be formed. In the region located on the lower electrode 9, a conductor film 26 b as a second remaining conductor film is formed on the insulating film 7 so as to cover the lower electrode 9. The planar shape of the conductor films 26a and 26b is substantially equal to the planar shape of the resist films 28a and 28b shown in FIG. Also in the drive circuit region, the gate electrode 8c of the p-type thin film field effect transistor 38 is formed, and the n-type thin film field effect transistor 39 is formed in the region where the n-type thin film field effect transistor 39 is to be formed. A conductor film 26c is formed so as to cover the power region.
[0082]
Here, in the etching process described with reference to FIGS. 5 and 13, the resist film 28b is formed at a distance from the resist film 28a. Therefore, the conductor film in the region located between the resist films 28a and 28b is etched in the etching process, and the conductor film portion located between the conductor films 26a and 26b as shown in FIG. Has been removed by etching. That is, by this etching process, the conductor film 26a including a portion to be the gate electrode 8a and the conductor film 26b to be the upper electrode 8b are formed separately.
[0083]
Next, as shown in FIG. 14, p-type impurity regions 27a and 27b are formed by implanting boron ions into predetermined regions using the conductor films 26a to 26c and the gate electrode 8c as a mask. Since boron ions are not implanted into the portion located under the gate electrode 8c, this portion of the polysilicon film 25b becomes the channel region 6c.
[0084]
Next, as shown in FIGS. 6 and 15, resist films 29a to 29d are formed on the conductor films 26a to 26c and the gate electrode 8c. The resist film 29a is formed on the region where the gate electrode 8a is to be formed. The resist film 29b is a resist film for forming the upper electrode 8b, and an opening 30 is formed in the resist film 29b.
[0085]
Then, the conductive films 26a to 26c are partially removed by etching using the resist films 29a to 29d as a mask, thereby forming gate electrodes 8a and 8d and an upper electrode 8b (see FIG. 16). In the upper electrode 8b, an opening 21 (see FIG. 16) is formed in a region located below the opening 30 of the resist film 29b by this etching process. In this etching step, the etching process conditions are adjusted and the sidewalls of the gate electrodes 8a and 8d are removed by a predetermined width by etching, whereby the positions of the sidewalls of the gate electrodes 8a and 8d are changed to those of the resist films 29a and 29d. Retreat from the side wall position.
[0086]
In the etching process for forming the gate electrodes 8a and 8d and the upper electrode 8b, a region located between the gate electrode 8a and the upper electrode 8b (a region between the resist film 29a and the resist film 29b in FIG. 6). The conductive films 26a and 26b located at () are subjected to etching. That is, in addition to the first etching process described in FIG. 5, the second etching process described in FIGS. 6 and 15 is performed. For this reason, when a pattern shape defect or the like occurs due to foreign matter or the like existing on the glass substrate 1 in the resist films 29a and 29b, the resist films 28a, 28b, 29a, and 29b used in the first and second etching steps are completely different. The probability of such a defect occurring at the same location is very low. Therefore, the probability that the conductive film located in the region between the gate electrode 8a and the upper electrode 8b is etched in at least one of the first etching process and the second etching process can be extremely increased. As a result, the probability of occurrence of a defect such as a short circuit between the gate electrode 8a and the upper electrode 8b due to an etching failure can be reduced.
[0087]
Further, in the boron ion implantation process shown in FIG. 14, a gap is formed between the semiconductor film in which the channel regions 6a and 6b are formed and the lower electrode 9, so that description will be given with reference to FIG. Even if the conductor films 26a and 26b are separated in the first etching step, neither the semiconductor film nor the lower electrode 9 extends under the gap between the conductor films 26a and 26b. Therefore, it is possible to prevent the problem that boron ions are unnecessarily implanted into the semiconductor film or the lower electrode 9 in the implantation step shown in FIG.
[0088]
Next, as shown in FIG. 16, by using the resist films 29a to 29d as a mask, phosphorus ions are implanted into a predetermined region, whereby n-type impurity regions 4a to 4f and n ⁺ A type impurity region 3d is formed.
[0089]
Here, the widths of the resist films 29a and 29d are set to be smaller than the widths of the resist films 24a and 24c shown in FIG. Therefore, in the implantation step shown in FIG. 16, phosphorus ions can be newly implanted into a region (region adjacent to the gate electrodes 8a and 8d) where phosphorus ions were not implanted in the implantation step shown in FIG. The regions into which phosphorus ions are newly implanted are n-type impurity regions 4a to 4f. The resist film 29 c functions as a protective film that prevents excessive phosphorus ions from being implanted into the p-type thin film field effect transistor 38. Thereafter, the resist films 29a to 29d are removed.
[0090]
Next, as shown in FIG. 17, phosphorus ions are implanted into a predetermined region by using the gate electrodes 8a and 8d and the upper electrode 8b as a mask, so that n ^- Type impurity regions 5a to 5h are formed. Here, as shown in FIG. 16, the positions of the side walls of the gate electrodes 8a and 8d are set back relative to the positions of the side walls of the resist films 29a and 29d. Therefore, in the implantation step shown in FIG. 17, from the region where phosphorus ions are not implanted in the implantation step shown in FIG. 16, that is, from the position below the sidewalls of the gate electrodes 8a and 8d, below the sidewalls of the resist films 29a and 29d. Phosphorus ions are first implanted into the portion of the semiconductor film located in the region between the positions. And this part is n ^- Type impurity regions 5a to 5h. Since the doping amount of phosphorus ions in the implantation step shown in FIG. 17 is extremely low, the electrical properties of the p-type thin film field effect transistor 38 can be provided without providing a protective film or the like for the p-type thin film field effect transistor 38. The characteristics are hardly influenced by phosphorus ions implanted by the implantation process shown in FIG.
[0091]
Next, as shown in FIG. 18, an interlayer insulating film 10 is formed on the gate electrodes 8a, 8c, 8d and the upper electrode 8b.
[0092]
Next, as shown in FIG. 7, a resist film 30 is formed on the interlayer insulating film 10. In the resist film 30, openings 31a to 31c are formed in regions where the contact holes 11a to 11c are to be formed, respectively. Similarly, in the drive circuit region, a resist film having an opening formed on the interlayer insulating film 10 is formed. Each opening is formed on a region where the contact holes 11d to 11g are to be formed. Using this resist film 30 as a mask, interlayer insulating film 10 and insulating film 7 are partially removed by etching. As a result, contact holes 11a to 11g are formed. Thereafter, the resist film 30 is removed.
[0093]
Next, a metal film (not shown) is formed so as to extend from the upper surface of the interlayer insulating film 10 to the inside of the contact holes 11a to 11g. Resist films 32a and 32b as shown in FIG. 8 are formed on the metal film. Also in the drive circuit region, a resist film having a predetermined pattern is formed on the metal film. Referring to FIG. 8, resist film 32a is arranged on a region where metal interconnection 12a (see FIG. 19) is to be formed. The resist film 32b is disposed on the region where the metal wiring 12b (see FIG. 19) is to be formed. In the drive circuit region, a resist film is formed on each region where the metal wirings 12c to 12e are to be formed. By using the resist films 32a and 32b as a mask, the metal film is partially removed by etching to form metal wirings 12a to 12e. Thereafter, the resist films 32a and 32b are removed. In this way, a structure as shown in FIG. 19 is obtained.
[0094]
Here, the metal wiring 12b extends from the inside of the contact holes 11b and 11c as the first and second contact holes to the upper surface of the interlayer insulating film 10 as the insulating film, and 3c as the conductive region It acts as a connecting conductor film that connects the lower electrode 9 of the capacitor. For this reason, n ⁺ The type impurity region 3c and the lower electrode 9 can be reliably electrically connected.
[0095]
Thereafter, a passivation film (not shown) and a planarizing film 13 (see FIG. 20) are formed on the metal wirings 12a to 12e.
[0096]
As shown in FIG. 9, a resist film 33 is formed on the planarizing film 13. In the resist film 33, an opening 34 is formed in a region where the contact hole 14 (see FIG. 20) is to be formed. By using this resist film 33 as a mask, a part of the planarizing film 13 and the passivation film is removed by etching, thereby forming a contact hole 14 (see FIG. 20). Thereafter, the resist film 33 is removed.
[0097]
Then, a transparent conductor film (not shown) serving as a pixel electrode is formed so as to extend from the upper surface of the planarizing film 13 to the inside of the contact hole 14. A resist film 35 having a predetermined shape is formed on the transparent conductor film as shown in FIG. The pixel electrode 15 (see FIG. 20) is formed by partially removing the transparent conductor film by etching using the resist film 35 as a mask. The planar shape of the resist film 35 shown in FIG. 10 is almost the same as the planar shape of the pixel electrode 15 (see FIG. 20). Thereafter, the resist film 35 is removed. Thus, a structure as shown in FIG. 20 is obtained.
[0098]
Thereafter, an alignment film 16 a (see FIG. 2) is formed on the pixel electrode 15. Then, the upper glass substrate 17 (see FIG. 2) on which the color filter 18, the counter electrode 19 and the alignment film 16b are formed is disposed so as to face the glass substrate 1, and the liquid crystal 20 (see FIG. 2) is disposed between the alignment films 16a and 16b. 2) is injected and sealed, the liquid crystal display device shown in FIGS. 1 and 2 can be obtained.
[0099]
(Embodiment 2)
21 and 22 are a schematic plan view and a schematic cross-sectional view showing Embodiment 2 of the liquid crystal display device according to the present invention. FIG. 21 corresponds to FIG. FIG. 22 corresponds to FIG. Note that the display pixel region in FIG. 22 corresponds to a schematic cross-sectional view taken along line segment 300-300 in FIG. The liquid crystal display device will be described with reference to FIGS.
[0100]
Referring to FIGS. 21 and 22, the liquid crystal display device basically has the same structure as the liquid crystal display device shown in FIGS. However, a recess 40 is formed in the planar outer shape of the upper electrode 8b. Then, the contact hole 11 c as the second contact hole extends from the upper surface of the interlayer insulating film 10 through the recess 40 to the n of the lower electrode 9. ⁺ It is formed so as to reach the type impurity region 3d.
[0101]
Here, as shown in the first embodiment of the present invention, an opening 21 (see FIGS. 1 and 2) is formed in the upper electrode 8b in order to secure a region for forming the contact hole 11c in the upper electrode 8b. Consider the case. In this case, in the etching process for forming the opening 21, an etching failure occurs such that the shape of the opening 21 does not become a predetermined shape stochastically or the opening 21 is not formed at all. However, as shown in FIGS. 21 and 22, when etching is performed so as to form the recess 40 in the planar outer shape of the upper electrode 8b, the above-described etching defects that occur when the opening 21 is formed hardly occur. . For this reason, generation | occurrence | production of the structural defect of the liquid crystal display device resulting from an etching defect can be prevented. As a result, it is possible to prevent the manufacturing yield of the liquid crystal display device from being lowered due to the above structural defects.
[0102]
In the liquid crystal display device shown in FIGS. 1 and 2, since the contact hole 11c is formed in the region where the opening 21 of the upper electrode 8b is formed, the contact hole 11b is not formed between the contact hole 11b and the contact hole 11c. A part of the upper electrode 8b exists. For this reason, a step 43 is formed between the contact hole 11b and the contact hole 11c on the upper surface of the interlayer insulating film 10 due to the presence of a part of the upper electrode 8b. The metal wiring 12b is formed on the step portion 43. When the metal wiring 12b is formed on the stepped portion 43, there is a risk that the metal wiring 12b is disconnected at the stepped portion 43. However, in the liquid crystal display device shown in FIGS. 21 and 22, a part of the upper electrode 8b does not exist between the contact hole 11b and the contact hole 11c. For this reason, a step portion due to the presence of a part of the upper electrode 8b is not formed on the upper surface of the interlayer insulating film 10 in this region. Therefore, in the region located between contact hole 11b and contact hole 11c, metal wiring 12b is not formed on the above stepped portion. Thereby, generation | occurrence | production of defects, such as disconnection of the metal wiring 12b resulting from presence of a level | step-difference part, can be suppressed. As a result, it is possible to prevent a decrease in manufacturing yield of the liquid crystal display device due to such disconnection of the metal wiring 12b.
[0103]
Next, a manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22 will be described with reference to FIGS. 23 to 27 are schematic plan views corresponding to the region 200 in FIG. 28 to 33 are schematic cross-sectional views corresponding to FIG.
[0104]
First, the manufacturing process shown in FIGS. 3 to 5 and FIGS. 11 to 14 in Embodiment 1 of the present invention is performed. Thereafter, as shown in FIGS. 23 and 28, resist films 29a to 29d having a predetermined pattern are formed on the conductor films 26a, 26b, 26c and the gate electrode 8c. This process corresponds to the process shown in FIGS. 6 and 15 in the manufacturing process of the first embodiment of the liquid crystal display device according to the present invention. However, in the process shown in FIGS. 23 and 28, the shape of the resist film 29b is different from the manufacturing process of the first embodiment of the liquid crystal display device according to the present invention. That is, the resist film 29b is used as a mask for forming the upper electrode 8b (see FIGS. 21 and 22). However, the resist film 29b is formed on the resist film 29b in order to form the recess 40 (see FIGS. 21 and 22) of the upper electrode 8b. Is formed with a recess 41.
[0105]
Thereafter, similar to the manufacturing process of the first embodiment of the liquid crystal display device according to the present invention, by using the resist films 29a to 29d as a mask, the conductor films 26a, 26b and 26c are partially removed by etching. The gate electrodes 8a and 8d and the upper electrode 8b (see FIG. 29) are formed. At this time, a recess 40 is formed in the upper electrode 8b below the region where the recess 41 of the resist film 29b is formed. For this etching step, wet etching can be used.
[0106]
In the etching step for forming the upper electrode 8b, when the opening 21 (see FIGS. 1 and 2) is formed as in the first embodiment of the present invention, the shape of the opening 21 is predetermined with a certain probability. Etching defects such as the shape of the above or the opening 21 is not formed. However, when the recess 40 is formed in the planar outer shape of the upper electrode 8b as in the second embodiment of the present invention, there is almost no probability that the above-described etching failure occurs. For this reason, it is possible to prevent the occurrence of the problem that the manufacturing yield of the liquid crystal display device is lowered due to the etching failure such that the recess 40 is not formed or the shape of the recess 40 does not become a predetermined shape.
[0107]
In addition, wet etching is used in the etching step. In this case, the etching amount can be accurately controlled by controlling process parameters such as etching time.
[0108]
Further, as in the first embodiment of the present invention, since the connection region between the metal wiring 12b (see FIGS. 21 and 22) and the lower electrode 9 is formed, the lower electrode 9 does not overlap the upper electrode 8b in a plane. Since it is not necessary to form the region so as to extend to the region, the area occupied by the capacitor 37 can be reduced as a result.
[0109]
In the above-described etching step, the process conditions are set so that the side wall positions of the gate electrodes 8a and 8d are recessed from the side wall positions of the resist films 29a and 29d as in the first embodiment of the present invention. It is controlled.
[0110]
Thereafter, as shown in FIG. 29, phosphorus ions are implanted into a predetermined region. The process conditions and the like of the step of implanting phosphorus ions are basically the same as the manufacturing steps of the liquid crystal display device in the first embodiment of the present invention shown in FIG. Thereafter, the resist films 29a to 29d are removed.
[0111]
Next, a phosphorus ion implantation step is performed as shown in FIG. The process conditions in this phosphorus ion implantation step are basically the same as those in the manufacturing process of the liquid crystal display device in the first embodiment of the present invention shown in FIG.
[0112]
Next, as shown in FIG. 31, an interlayer insulating film 10 is formed on the gate electrodes 8a, 8c, 8d and the upper electrode 8b. The process shown in FIG. 31 is basically the same as the manufacturing process of the liquid crystal display device according to the first embodiment of the present invention shown in FIG.
[0113]
Next, as shown in FIG. 24, a resist film 30 having a predetermined pattern is formed on the interlayer insulating film 10. In the resist film 30, openings 31a to 31c are formed in regions where contact holes 11a to 11c are to be formed in the display pixel region. Also in the drive circuit region, openings for forming contact holes 11d to 11g are formed in predetermined regions as in the first embodiment of the present invention. Then, by using this resist film 30 as a mask, a part of the interlayer insulating film 10 and the insulating film 7 is removed by etching, thereby forming contact holes 11a to 11g (see FIG. 32). Thereafter, the resist film 30 is removed.
[0114]
Next, a conductor film (not shown) is formed on the interlayer insulating film 10 as in the first embodiment of the present invention. Resist films 32a and 32b are formed on the conductor film as shown in FIG. The process shown in FIG. 25 is basically the same as the process shown in FIG. 8 of the manufacturing process of the liquid crystal display device in the first embodiment of the present invention. Metal wirings 12a and 12b (see FIG. 32) are formed by partially removing the conductor film by etching using the resist films 32a and 32b as a mask. Similarly, metal wirings 12c to 12e are formed by etching in the drive circuit region. Thereafter, the resist films 32a and 32b are removed. In this way, a structure as shown in FIG. 32 is obtained.
[0115]
Next, as in the first embodiment of the present invention, a passivation film (not shown) and a planarizing film 13 (see FIG. 33) are formed on the metal wirings 12a to 12e. As shown in FIG. 26, a resist film 33 having a predetermined pattern is formed on the planarizing film 13. In the resist film 33, an opening 34 is formed in a region where the contact hole 14 (see FIG. 33) is to be formed. By using this resist film 33 as a mask, a part of the planarizing film 13 and the passivation film is removed by etching, thereby forming a contact hole 14 (see FIG. 33). Thereafter, the resist film 33 is removed.
[0116]
Next, a transparent conductor film (not shown) is formed on the planarizing film 13 as in the first embodiment of the present invention. Next, as shown in FIG. 27, a resist film 35 having a predetermined pattern is formed on the transparent conductor film. The resist film 35 basically has the same planar shape as that of the pixel electrode 15 (see FIG. 33). Then, by using this resist film 35 as a mask, a part of the transparent conductor film is removed by etching to form the pixel electrode 15 (see FIG. 33). Thereafter, the resist film 35 is removed. As a result, a structure as shown in FIG. 33 is obtained.
[0117]
Thereafter, an alignment film 16a is formed on the pixel electrode 15 as in the first embodiment of the present invention. Further, an upper glass substrate 17 on which the color filter 18, the counter electrode 19 and the alignment film 16b are formed is prepared. By disposing the upper glass substrate 17 so as to face the glass substrate 1 and injecting and sealing the liquid crystal 20, a liquid crystal display device as shown in FIGS. 21 and 22 can be obtained.
[0118]
(Embodiment 3)
34 and 35 are a schematic plan view and a schematic cross-sectional view showing Embodiment 3 of the liquid crystal display device according to the present invention. 34 corresponds to FIG. 1, and FIG. 35 corresponds to FIG. 35 is a schematic cross-sectional view taken along line segment 400-400 shown in FIG. A liquid crystal display device will be described with reference to FIGS.
[0119]
Referring to FIGS. 34 and 35, the liquid crystal display device basically has the same structure as that of the second embodiment of the liquid crystal display device according to the present invention shown in FIGS. However, in the liquid crystal display device shown in FIGS. 34 and 35, n as a conductive region is used. ⁺ The lower electrode 9 is constituted by the same layer as the semiconductor film in which the type impurity region 3c is formed, and the lower electrode 9 is formed in contact with the semiconductor film, that is, by one continuous semiconductor film. For this reason, in the region located between the contact hole 11b and the contact hole 11c, n ⁺ A step portion on the upper surface of the interlayer insulating film 10 due to the presence of the end portion of the semiconductor film in which the type impurity region 3 c is formed and the end portion of the lower electrode 9 is not formed. That is, in the region between the contact holes 11b and 11c, there is no stepped portion as described above on the upper surface of the interlayer insulating film 10, so that the metal wiring as the connection conductor film is formed on the upper surface of the flat interlayer insulating film 10. 12b is formed. As a result, it is possible to reliably prevent the occurrence of defects such as disconnection of the metal wiring 12b due to the presence of the stepped portion as described above.
[0120]
Next, a method for manufacturing the liquid crystal display device shown in FIGS. 34 and 35 will be described with reference to FIGS. 36 to 43 are schematic plan views corresponding to the region 200 in FIG. 34, and FIGS. 44 to 52 are schematic cross-sectional views corresponding to FIG.
[0121]
First, after performing the process shown in FIG. 11, a resist film 23c is formed on the polysilicon film obtained by converting the amorphous silicon film 22 into polysilicon by laser annealing as shown in FIG. FIG. 36 corresponds to FIG. Here, the resist film 23c shown in FIG. 36 is different from the resist films 23a and 23b shown in FIG. 3 in that n as a conductive region of the pixel thin film field effect transistor 36 is used. ⁺ The semiconductor film in which the type impurity region 3c is formed and the lower electrode 9 of the capacitor 37 are contacted and patterned so as to be continuously formed. That is, the resist film portion for forming the semiconductor film by etching is connected to the resist film portion for forming the lower electrode 9 by etching.
[0122]
Using this resist film 23c as a mask, the polysilicon film formed by the laser annealing is partially removed by etching, thereby forming a polysilicon film 25c (see FIG. 44). In the drive circuit region, the channel region 6c of the p-type thin film field effect transistor 38 and the p-type impurity regions 27a and 27b are to be formed by the same etching process, and the channel region of the n-type thin film field effect transistor 39. 6d and n ⁺ A semiconductor film in which type impurity regions 3 e and 3 f and n type impurity regions 4 e and 4 f are to be formed is formed on base film 2. Thereafter, the resist film 23c is removed.
[0123]
Next, the insulating film 7 (see FIG. 44) is formed on the polysilicon film 25c and the semiconductor film in the drive circuit region.
[0124]
Next, as shown in FIGS. 37 and 44, resist films 42 a to 42 c are formed on the insulating film 7. In the display pixel region, the resist film 42a is n as a source / drain region which is a conductive region of the pixel thin film field effect transistor 38. ⁺ It is formed so as to cover the regions to be the type impurity regions 3a to 3c, the n type impurity regions 4a to 4d and the channel regions 6a and 6b. In the drive circuit region, resist films 42b and 42c are formed so as to cover the regions where the p-type thin film field effect transistor 38 and the n-type thin film field effect transistor 39 are to be formed. Then, as shown in FIG. 44, boron ions are implanted into a predetermined region using the resist films 42a to 42c as a mask. As a result, a p-type impurity region 27d to be the lower electrode 9 is formed. Thereafter, the resist films 42a to 42c are removed.
[0125]
Next, a conductor film (not shown) such as a metal film to be the gate electrodes 8a, 8c, 8d and the upper electrode 8b is formed on the insulating film 7. Resist films 28a and 28b are formed on this conductor film as shown in FIG. The resist film 28a includes the region where the gate electrode 8a is to be formed and the n thin film field effect transistor 36 for the pixel. ⁺ Type impurity regions 3a to 3c and n type impurity regions 4a to 4d are formed so as to cover the regions where they should be formed. The resist film 28b is formed so as to cover the region where the upper electrode 8b of the capacitor 37 is to be formed. The resist film 28b has a recess 41 for forming a recess 40 having a planar outer shape of the upper electrode 8b. In the drive circuit region, a resist film is formed so as to cover the region where the gate electrode 8c of the P-type thin film field effect transistor 38 is to be formed and the region where the n-type thin film field effect transistor 39 is to be formed. ing.
[0126]
The conductor films 26a to 26c and the gate electrode 8c (see FIG. 45) are removed by partially removing the conductor film by etching using the resist films 28a and 28b and the resist film formed in the drive circuit region as a mask. Form. Thereafter, the resist films 28a and 28b and the resist film formed in the drive circuit region are removed. In this way, a structure as shown in FIG. 45 is obtained. At this time, the concave portion 40 having a planar outer shape of the upper electrode 8b is already formed in the conductor film 26b to be the upper electrode 8b.
[0127]
Next, as shown in FIG. 46, boron ions are implanted into a predetermined region of the semiconductor film using the conductor films 26a to 26c and the gate electrode 8c as a mask. The process shown in FIG. 46 is basically the same as the process shown in FIG. At this time, since the conductor film 26a is formed so as to cover a region where the pixel thin film field effect transistor 36 is to be formed, a semiconductor film for forming boron thin film field effect transistors 36 by boron ions. It acts as a protective film that prevents excessive injection into the substrate. Similarly, the conductor film 26b also functions as a protective film for preventing boron ions from being excessively implanted into the semiconductor film. Therefore, in the process shown in FIG. 46, the semiconductor located under the conductor film 26b. Boron ions are not implanted into the membrane.
[0128]
Next, as shown in FIGS. 39 and 47, resist films 29a to 29d are formed on the conductor films 26a to 26c and the gate electrode 8c. The resist film 29a is used as a mask in etching for forming the gate electrode 8a. The resist film 29d is used as a mask in the etching process for forming the gate electrode 8d.
[0129]
Next, the conductor films 26a to 26c are partially removed by etching using the resist films 29a, 29b, and 29d as masks, thereby forming gate electrodes 8a and 8d (see FIG. 48). In the etching process for forming the gate electrodes 8a and 8d, the resist films 29a and 29d are basically the same as the processes described in FIGS. 15 and 16 in the manufacturing process of the liquid crystal display device according to the first embodiment of the present invention. Etching process conditions are adjusted so that the positions of the side walls of the gate electrodes 8a and 8d are set back relative to the positions of the side walls.
[0130]
Next, as shown in FIG. 48, phosphorus ions are implanted using resist films 29a-29d as a mask. The phosphorus ion implantation process shown in FIG. 48 is basically the same as the phosphorus ion implantation process shown in FIG. In the implantation step shown in FIG. 48, phosphorus ions are implanted by using the resist films 29a, 29b, and 29d as masks. ⁺ Type impurity regions 3a to 3c, 3e, and 3f are formed. Thereafter, the resist films 29a to 29d are removed.
[0131]
Next, as shown in FIG. 49, low concentration phosphorus ions are implanted into a predetermined region using the gate electrodes 8a and 8d and the upper electrode 8b as a mask. This low concentration phosphorus ion implantation step is basically the same as the phosphorus ion implantation step shown in FIG. In the process shown in FIG. 49, low concentration phosphorus ions are implanted using the gate electrodes 8a and 8d having a width narrower than that of the resist films 29a and 29d as a mask. In other words, in the semiconductor film located under the region adjacent to the gate electrodes 8a and 8d in FIG. 49, a region into which phosphorus ions are implanted is formed for the first time in this step. This portion is n-type impurity regions 4a to 4f. 49. Since the concentration of phosphorus implanted in FIG. 49 is extremely low, the p-type thin film field effect transistor 38 and the p-type impurity region 27c in the lower electrode 9 do not have an adverse effect on the electrical characteristics.
[0132]
Next, as shown in FIG. 50, an interlayer insulating film 10 is formed on the gate electrodes 8a, 8c, 8d and the upper electrode 8b. At this time, n which is a conductive region of the pixel thin film field effect transistor 36 ⁺ Since the region where the type impurity region 3c is formed and the lower electrode 9 are continuously formed by one layer, it is formed on the upper surface of the interlayer insulating film 10 located between the gate electrode 8a and the upper electrode 8b. Has a flat shape without any steps. Therefore, when the metal wiring 12b (see FIG. 51) is formed in the region between the gate electrode 8a and the upper electrode 8b, no step is formed on the upper surface of the interlayer insulating film 10. It is possible to prevent the occurrence of defects such as disconnection of the metal wiring 12b due to such a step.
[0133]
Next, as shown in FIG. 40, a resist film 30 having a predetermined pattern is formed on the interlayer insulating film 10. In the resist film 30, openings 31a to 31c for forming the contact holes 11a to 11c are formed in regions where the contact holes 11a to 11c (see FIG. 51) are to be formed. 40 corresponds to the process described with reference to FIG. 7 of the manufacturing process of the liquid crystal display device according to the first embodiment of the present invention. In the drive circuit region, as in the first and second embodiments of the present invention, openings are formed in the resist film 30 in regions where the contact holes 11e to 11g are to be formed. By using this resist film 30 as a mask, part of interlayer insulating film 10 and insulating film 7 is removed by etching, thereby forming contact holes 11a to 11g. Thereafter, the resist film 30 is removed.
[0134]
Next, a metal film (not shown) to be the metal wirings 12 a to 12 e is formed on the interlayer insulating film 10. Next, as shown in FIG. 41, resist films 32a and 32b are formed on the metal film. The resist film 32a is formed on the region where the metal wiring 12a is to be formed. The resist film 32b is formed on the region where the metal wiring 12b is to be formed. Also in the drive circuit region, resist films are formed on regions where the metal wirings 12c to 12e are to be formed. By using the resist films 32a and 32b and the resist film in the drive circuit region as a mask, the metal film is partially removed by etching to form metal wirings 12a to 12e. Thereafter, the resist films 32a and 32b and the resist film in the drive circuit region are removed. In this way, a structure as shown in FIG. 51 is obtained.
[0135]
Next, a passivation film and a planarizing film 13 (see FIG. 52) are formed on the metal wirings 12a to 12e in the same manner as the manufacturing method of the liquid crystal display device shown in the first and second embodiments of the present invention. A resist film 33 is formed on the upper surface of the planarizing film 13 as shown in FIG. An opening 34 is formed in the resist film 33 on the region where the contact hole 14 is to be formed. Using the resist film 33 as a mask, the planarizing film 13 and the passivation film are partially removed by etching to form a contact hole 14 (see FIG. 52). Thereafter, the resist film is removed.
[0136]
Next, a transparent conductor film (not shown) to be a pixel electrode is formed on the planarizing film 13. A resist film 35 is formed on the transparent conductor film as shown in FIG. The planar outer shape of the resist film 35 is the same as the planar outer shape of the pixel electrode 15. The transparent conductive film is partially removed by etching using the resist film 35 as a mask, thereby forming the pixel electrode 15 (see FIG. 52). Thereafter, the resist film 35 is removed. In this way, a structure as shown in FIG. 52 is obtained.
[0137]
Thereafter, in the same manner as in the liquid crystal display manufacturing method according to the first and second embodiments of the present invention, the alignment film 16a is formed on the pixel electrode 15, and the color filter 18, the counter electrode 19 and the alignment film 16b are provided. A glass substrate 17 is prepared and arranged at a predetermined position. Further, by performing steps such as injecting and sealing the liquid crystal 20 between the glass substrate 1 and the upper glass substrate 17, the liquid crystal display device shown in FIGS. 34 and 35 can be obtained.
[0138]
Note that the conductivity type of the capacitor 37 may be either p-type or n-type.
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above-described embodiment but by the scope of claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of claims.
[0139]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent the occurrence of defects such as short circuit between the gate electrode of the thin film field effect transistor and the capacitor electrode of the capacitor adjacent to the thin film field effect transistor, thereby realizing a high manufacturing yield. A semiconductor device and a manufacturing method thereof, and a liquid crystal display device and a manufacturing method thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing a first embodiment of a liquid crystal display device according to the present invention.
FIG. 2 is a schematic cross-sectional view showing a first embodiment of a liquid crystal display device according to the present invention.
3 is a schematic plan view for explaining a second step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
4 is a schematic plan view for explaining a third step in the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
5 is a schematic plan view for explaining a fourth step in the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
6 is a schematic plan view for explaining a seventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
7 is a schematic plan view for explaining an eleventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
8 is a schematic plan view for explaining a twelfth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
9 is a schematic plan view for explaining a fourteenth process of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
10 is a schematic plan view for explaining a fifteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
11 is a schematic cross-sectional view for explaining a first step in the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
12 is a schematic cross-sectional view for explaining a third step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
13 is a schematic cross-sectional view for explaining a fifth step of the manufacturing steps of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
14 is a schematic cross-sectional view for explaining a sixth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
15 is a schematic cross-sectional view for explaining a seventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
16 is a schematic cross-sectional view for explaining an eighth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
17 is a schematic cross-sectional view for explaining a ninth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
18 is a schematic cross-sectional view for explaining a tenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
19 is a schematic cross-sectional view for explaining a thirteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
20 is a schematic cross-sectional view for explaining a sixteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 1 and 2. FIG.
FIG. 21 is a schematic plan view showing a second embodiment of a liquid crystal display device according to the present invention.
FIG. 22 is a schematic sectional view showing Embodiment 2 of a liquid crystal display device according to the present invention.
23 is a schematic plan view for explaining a first step in the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
24 is a schematic plan view for explaining a fifth step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
25 is a schematic plan view for explaining a sixth step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
26 is a schematic plan view for explaining an eighth step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
FIG. 27 is a schematic plan view for explaining a ninth step of the manufacturing steps of the liquid crystal display device shown in FIGS. 21 and 22.
FIG. 28 is a schematic cross-sectional view for explaining a first step in the manufacturing process of the liquid crystal display device shown in FIGS.
29 is a schematic cross-sectional view for explaining a second step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
30 is a schematic cross-sectional view for explaining a third step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
31 is a schematic cross-sectional view for explaining a fourth step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
32 is a schematic cross-sectional view for explaining a seventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
33 is a schematic cross-sectional view for explaining a tenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 21 and 22. FIG.
FIG. 34 is a schematic plan view showing a third embodiment of the liquid crystal display device according to the present invention.
FIG. 35 is a schematic sectional view showing Embodiment 3 of a liquid crystal display device according to the present invention.
36 is a schematic plan view for illustrating a first step in the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
FIG. 37 is a schematic plan view for illustrating a second step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35.
38 is a schematic plan view for explaining a third step of the manufacturing steps of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
39 is a schematic plan view for illustrating a sixth step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
40 is a schematic plan view for illustrating a tenth process of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
41 is a schematic plan view for explaining an eleventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
42 is a schematic plan view for explaining a thirteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
43 is a schematic plan view for explaining a fourteenth step of manufacturing the liquid crystal display device shown in FIGS. 34 and 35. FIG.
44 is a schematic cross-sectional view for explaining a second step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
45 is a schematic cross-sectional view for explaining a fourth step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
46 is a schematic cross-sectional view for explaining a fifth step of the manufacturing steps of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
47 is a schematic cross-sectional view for explaining a sixth step of the manufacturing steps of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
48 is a schematic cross-sectional view for explaining a seventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
49 is a schematic cross-sectional view for explaining an eighth step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
50 is a schematic cross-sectional view for explaining a ninth step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
51 is a schematic cross-sectional view for explaining a twelfth step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
52 is a schematic cross-sectional view for explaining a fifteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 34 and 35. FIG.
FIG. 53 is a schematic plan view showing a conventional liquid crystal display device.
FIG. 54 is a schematic cross-sectional view showing a conventional liquid crystal display device.
FIG. 55 is a schematic plan view for illustrating a second step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54.
56 is a schematic plan view for explaining a third step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
57 is a schematic plan view for illustrating a fourth step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
58 is a schematic plan view for explaining a seventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
59 is a schematic plan view for explaining an eleventh process of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
60 is a schematic plan view for illustrating a twelfth process of the manufacturing process for the liquid crystal display device shown in FIGS. 53 and 54. FIG.
61 is a schematic plan view for explaining a fourteenth process of the manufacturing process for the liquid crystal display device shown in FIGS. 53 and 54. FIG.
62 is a schematic plan view for illustrating a fifteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
63 is a schematic cross-sectional view for explaining a first step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
64 is a schematic cross-sectional view for explaining a third step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
65 is a schematic cross-sectional view for explaining a fifth step of the manufacturing steps of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
66 is a schematic cross-sectional view for explaining a sixth step of the manufacturing steps of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
67 is a schematic cross-sectional view for explaining a seventh step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
68 is a schematic cross-sectional view for explaining an eighth step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
69 is a schematic cross-sectional view for explaining a ninth step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
70 is a schematic cross-sectional view for explaining a tenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
71 is a schematic cross-sectional view for explaining a thirteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
72 is a schematic cross-sectional view for explaining a sixteenth step of the manufacturing process of the liquid crystal display device shown in FIGS. 53 and 54. FIG.
[Explanation of symbols]
1 glass substrate, 2 base film, 3a-3gn ⁺ Type impurity region, 4a-4f n-type impurity region, 5a-5h n ^- Type impurity region, 6a-6d channel region, 7 insulating film, 8a, 8c, 8d gate electrode, 8b upper electrode, 9 lower electrode, 10 interlayer insulating film, 11a-11g, 14 contact hole, 12a-12e metal wiring, 13 Flattening film, 15 pixel electrode, 16a, 16b alignment film, 17 upper glass substrate, 18 color filter, 19 counter electrode, 20 liquid crystal, 21, 31a-31c, 34 opening, 22 amorphous silicon film, 23a-23c, 24a -24c, 28a, 28b, 29a-29d, 32a, 32b, 33, 30, 35, 42a-42c resist film, 25a-25c polysilicon film, 26a-26c conductor film, 27a-27d p-type impurity region, 36 Thin film field effect transistor for pixels, 37 capacitance, 38 p-type thin film field effect transistor, 39n thin Field effect transistors, 40 and 41 recesses, 43 stepped portion.

Claims (15)

A semiconductor device comprising a thin film field effect transistor formed on a transparent substrate, and a capacitance region adjacent to the thin film field effect transistor,
The thin film field effect transistor includes a semiconductor film formed on the transparent substrate and having a channel region and a conductive region adjacent to the channel region,
The capacity region is
A lower electrode formed on the transparent substrate;
An upper electrode formed on the lower electrode so as to face the lower electrode and having an opening, and
A first contact hole formed on the conductive region and on the upper electrode, having an upper surface, reaching from the upper surface to the conductive region, and a first contact hole reaching from the upper surface to the lower electrode. An insulating film formed with two contact holes;
A semiconductor device comprising: a connection conductor film extending from the inside of the first and second contact holes to the upper surface of the insulating film and connecting the conductive region and the lower electrode of the capacitor region. The semiconductor device according to claim 1, wherein the second contact hole reaches the lower electrode from the upper surface of the insulating film through the opening of the upper electrode. The semiconductor device according to claim 2, wherein the opening of the upper electrode is a recess in a planar outer shape of the upper electrode. The semiconductor device according to claim 1, wherein the lower electrode is formed of the same layer as the semiconductor film and is formed separately from the semiconductor film. The semiconductor device according to claim 1, wherein the lower electrode is formed of the same layer as the conductor film and is formed so as to be in contact with the semiconductor film. The semiconductor device according to claim 1, wherein a conductivity type of the thin film field effect transistor is an n-type. A liquid crystal display device comprising the semiconductor device according to claim 1. A semiconductor device comprising: a first thin film field effect transistor; a second thin film field effect transistor having a conductivity type different from that of the first thin film field effect transistor; and a capacitance region adjacent to the second thin film field effect transistor. A manufacturing method of
A first semiconductor film to be a conductive region of the first thin film field effect transistor on a substrate; a second semiconductor film including a conductive region of the second thin film field effect transistor; and a lower electrode of the capacitor region A lower layer preparation step for forming
Forming an upper conductor film to be the gate electrode of the first and second thin film field effect transistors and the upper electrode of the capacitor region on the first and second semiconductor films and the lower electrode; When,
In the upper conductor film, a region to be a gate electrode of the first thin film field effect transistor, a region located on the second semiconductor film, and the second semiconductor film on the lower electrode Forming a resist film on each of the regions spaced from the regions located above,
The conductive film is partially removed by etching using the resist film as a mask, so that the gate electrode of the first thin film field effect transistor and the first remaining conductor located on the second semiconductor film Forming a film and a second remaining conductor film located on the lower electrode, spaced apart from the first remaining conductor film;
Removing the resist film;
Injecting conductive impurities into the first semiconductor film using the gate electrode of the first thin film field effect transistor and the first and second remaining conductor films as a mask;
After injecting a conductive impurity into the first semiconductor film, a first resist film is formed on a region where the gate electrode of the second thin film field effect transistor is to be formed in the first remaining conductor film, And a step of forming the other resist film on a region where the upper electrode is to be formed on the second remaining conductor film and spaced apart from the one resist film;
Using the one and other resist films as a mask, the first and second remaining conductor films are partially removed by etching, whereby a gate electrode of the second thin film field effect transistor and an upper electrode of the capacitor region A method for manufacturing a semiconductor device, comprising: an upper layer preparation step for forming a semiconductor layer. In the upper layer preparation step, an opening is formed in the upper electrode of the capacitor region,
Forming an upper insulating film so as to extend from the conductive region of the second thin film field effect transistor to the upper electrode of the capacitor region;
In the upper insulating film, a first contact hole reaching from the upper surface of the upper insulating film to the conductive region is formed, and from the upper surface of the upper insulating film through the opening of the upper electrode of the capacitor region. Forming a second contact hole reaching the lower electrode of the capacitor region;
Extending from the inside of the first contact hole to the inside of the second contact hole through the upper surface of the upper insulating film, and under the conductive region and the capacitance region of the second thin film field effect transistor The method of manufacturing a semiconductor device according to claim 8, further comprising: forming a connection conductor film that electrically connects the electrode. In the upper layer preparation step, a recess is formed in the planar outer shape of the upper electrode of the capacitor region,
Forming an upper insulating film so as to extend from the conductive region of the second thin film field effect transistor to the upper electrode of the capacitor region;
In the upper insulating film, a first contact hole reaching from the upper surface of the upper insulating film to the conductive region is formed, and a recess in the planar outer shape of the upper electrode of the capacitor region from the upper surface of the upper insulating film Forming a second contact hole reaching the lower electrode of the capacitance region via
Extending from the inside of the first contact hole to the inside of the second contact hole through the upper surface of the upper insulating film, and under the conductive region and the capacitance region of the second thin film field effect transistor The method of manufacturing a semiconductor device according to claim 8, further comprising: forming a connection conductor film that electrically connects the electrode. The method for manufacturing a semiconductor device according to claim 10, wherein wet etching is used in the upper layer preparation step. 12. The method of manufacturing a semiconductor device according to claim 8, wherein, in the lower layer preparation step, the second semiconductor film and the lower electrode are formed with an interval. 12. The method of manufacturing a semiconductor device according to claim 8, wherein, in the lower layer preparation step, the second semiconductor film and the lower electrode are formed to be in contact with each other by the same layer. The method of manufacturing a semiconductor device according to claim 8, wherein a conductivity type of the second thin film field effect transistor is n-type. The manufacturing method of the liquid crystal display device using the manufacturing method of the semiconductor device of any one of Claims 8-14.

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