JP3855576B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP3855576B2
JP3855576B2 JP2000036138A JP2000036138A JP3855576B2 JP 3855576 B2 JP3855576 B2 JP 3855576B2 JP 2000036138 A JP2000036138 A JP 2000036138A JP 2000036138 A JP2000036138 A JP 2000036138A JP 3855576 B2 JP3855576 B2 JP 3855576B2
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peltier element
metal plate
semiconductor
semiconductor device
temperature
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JP2001230354A (en
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隆幸 吉田
詔夫 杭東
精一 影山
望 下石坂
和弘 石川
毅 川端
徹 野村
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

【０００１】
【発明の属する技術分野】
本発明は消費電力の大きな半導体素子を搭載する冷却機構を備えた半導体装置に関するものである。
【０００２】
【従来の技術】
近年、電子機器は益々高機能化し、動作速度が高速化するとともに消費電力も増大している。このため、半導体素子の冷却が大きな問題となっている。こうした中でペルチェ素子を用いた冷却機構が数多く提案されている。
【０００３】
従来の半導体装置の一例として、例えば特許第２６８２５８６号に示されるように、冷却半導体からなる冷却器を半導体チップ裏面側に直接、またはダイパッドを介して接合し、半導体チップの検出温度に応じて温度制御回路から出力信号を出し、冷却器に与えることにより半導体チップの温度上昇を抑制し、所定温度に抑えるという構造が提案されている。
【０００４】
以下、従来の冷却機構を有した半導体装置について説明する。図４は従来の冷却機構を有した半導体装置を示す図であり、図４（ａ）は内部構成を示す透過型の平面図であり、図４（ｂ）はその中央部の断面図である。
【０００５】
従来の冷却機構を備えた半導体装置としては図示するように、リードフレームのダイパッド１０１上に温度制御回路素子１０２とともに、パワー系の半導体チップ１０３が搭載され、そのダイパッド１０１の底面には半導体よりなる冷却器１０４が設けられ、半導体チップ１０３、冷却器１０４とリード１０５が各々金属細線１０６で電気的に接続されたものである。そしてダイパッド１０１の外囲として半導体チップ１０３、冷却器１０４、およびリード１０５の内部リード部の外囲は封止樹脂１０７により封止された構造である。
【０００６】
以上のような構造により、従来は冷却器１０４を半導体チップ１０３の裏面に直接、またはダイパッド１０１を介して接合し、半導体チップ１０３の検出温度に応じて温度制御回路素子１０２から出力信号を出し、冷却器１０４に与えることにより半導体チップ１０３の温度上昇を抑制していた。
【０００７】
【発明が解決しようとする課題】
しかしながら前記従来の構成では、温度制御回路素子を半導体素子に組み込むか、または、温度制御回路を持った別の半導体素子をパッケージ内に同時に実装しなければならないという問題と、ペルチェ素子の発熱面の熱をいかに外部へ放熱させるかという問題を有し、実装面と放熱面との課題を有していた。
【０００８】
本発明は前記課題に鑑み、キャリア基材上に搭載した半導体素子の裏面または表面にペルチェ素子の冷却面を密着し、ペルチェ素子の発熱面にバイメタル構造の金属プレートを配置し、これを半導体素子を実装しているキャリア基材に電気的、機械的に接続し、発熱面の熱を高熱伝導率のバイメタル金属板を通してキャリア基材からキャリア基材を搭載している母配線基板に伝達し、放熱特性を高めると共に、ペルチェ素子の発熱板が高温になった場合、バイメタル金属板のそれぞれの金属の熱膨張係数の差により接点が外れペルチェ素子を停止し、再び冷えた場合、接点部分が接続してペルチェ素子が動作を開始するサーモスタット構造を有する半導体装置を提供するものである。
【０００９】
【課題を解決するための手段】
前記従来の課題を解決するために本発明の半導体装置は、半導体素子と、前記半導体素子を搭載した基板と、前記半導体素子に配置されたぺルチェ素子と、前記ペルチェ素子に密着したバイメタル構造の第１の金属板と、前記第１の金属板に一端が接続し、他端が前記基板に接続したバイメタル構造の第２の金属板とよりなる半導体装置である。
【００１１】
そして本発明の半導体装置は、ペルチェ素子が高温になった場合、金属の熱膨張係数の差により第２の金属板が変形し、前記ペルチェ素子に密着したバイメタル構造の第１の金属板と前記第２の金属板との接点が外れ、前記ペルチェ素子を停止させ、再び温度が低下した場合、前記接点部分が接続してペルチェ素子が動作を開始するサーモスタット構造を有する半導体装置である。
【００１２】
前記構成の通り、ペルチェ素子の発熱面の熱を金属板を通して基板へ効率よく伝達し、さらに基板から母配線基板へ熱を伝達することにより、熱の空気への放熱効率を上昇させることができる。このため、ペルチェ素子の発熱面の温度上昇を所望範囲内におさめることが可能となり、半導体素子と機器全体の雰囲気温度を安定させることができ、システムに誤動作、または動作不良をなくすことができる。
【００１３】
また、半導体素子の発熱量が大きいとペルチェ素子に大きな電流が通電され続ける状態となるが、このときの金属板をバイメタル原理を利用した構造のサーモスタットとすることにより、ペルチェ素子の発熱板が高温になった場合、バイメタル金属板のそれぞれの金属の熱膨張係数差により接点が外れ、ペルチェ素子を停止させ、再び冷えた場合、サーモスタットの接点部分が接続してペルチェ素子の動作を開始させることができる。ここでペルチェ素子の熱容量を充分大きくすると、半導体素子の温度上昇を所望以下に抑えた状態でペルチェ素子の発熱面の温度を下降させ、再びサーモスタットが通電してペルチェ素子が半導体素子の冷却を開始するという動作を繰り返すことが可能となり、半導体素子を確実に所望温度以下にするとともに、ペルチェ素子からの発熱も効率よく外部へ伝達し、かつ必要以上の発熱を抑えることができ、機器全体の雰囲気温度を安定させることができ、システムに誤動作、または動作不良をなくすことができる。
【００１４】
【発明の実施の形態】
以下、本発明の半導体装置の一実施形態について図面を参照しながら説明する。図１は本実施形態の半導体装置を示す断面図である。
【００１５】
本実施形態の半導体装置は、半導体素子と、その半導体素子を搭載し、半導体素子の電気信号や電力を入出力する配線を有するキャリア基板と、半導体素子の表面または裏面にその一面が配置されたぺルチェ素子と、そのペルチェ素子の他面に密着した金属板と、その金属板に一端が接続し、他端がキャリア基板に接続した金属板とよりなる半導体装置である。
【００１６】
具体的には図示するように、底面に外部電極を有し、表面に配線パターンを有し、その配線パターンと外部電極とが内部ビアで接続された積層基板であるキャリア基板１と、そのキャリア基板１の表面にバンプ２を介してその主面で接続された半導体素子３と、半導体素子３とキャリア基板１との間隙を充填封止したエポキシ系のアンダーフィル樹脂４（封止樹脂）と、半導体素子３の裏面に配置されたペルチェ素子５と、そのペルチェ素子５の外囲面に密着させて設けた金属プレート６ａと、金属プレート６ａと接続し、その金属プレート６ａからキャリア基板１に熱を伝導させ、電気的に接続した金属プレート６ｂとより構成されているものである。
【００１７】
本実施形態の熱対策型の半導体装置は、ペルチェ素子５の発熱面の熱は、金属プレート６ａ，６ｂを通してキャリア基板１へ効率よく伝達され、さらにキャリア基板１から実装基板である母配線基板（図示せず）へ熱を伝達することにより、熱の空気への放散面積を増加させ、放熱効率を上昇させることができ、ペルチェ素子５の発熱面の温度上昇を所望範囲内に抑えることが可能となり、電子機器全体の雰囲気温度を安定させることができる。そのため電子機器のシステムに誤動作、または動作不良をなくすことができる。また金属プレート６ａ，６ｂはキャップ状に構成し、ペルチェ素子５からの熱をキャリア基板１に伝導できる構造であればよい。
【００１８】
なお、本実施形態では半導体素子をフェースダウン搭載したＣＳＰ（ＣｈｉｐＳｉｚｅ Ｐａｃｋａｇｅ）の構造を例に記述してるが、ＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ），ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）等でも類似構造で同様な効果を得ることが可能である。
【００１９】
次に本発明の第２の実施形態について説明する。図２は本実施形態の半導体装置を示す断面図である。図３は本実施形態の半導体装置の動作を示す断面図であり、図３（ａ）は導通状態（初期状態）を示し、図３（ｂ）は温度上昇時の状態を示す。
【００２０】
まず本実施形態の半導体装置は、半導体素子と、その半導体素子を搭載し、半導体素子の電気信号や電力を入出力する配線を有するキャリア基板と、半導体素子の表面または裏面にその一面が配置されたぺルチェ素子と、そのペルチェ素子の他面に密着したバイメタル構造の第１の金属板と、その第１の金属板に一端が接続して接点を構成し、他端がキャリア基板に接続したバイメタル構造の第２の金属板とよりなる半導体装置であり、ペルチェ素子が高温になった場合、金属の熱膨張係数の差により第２の金属板が変形し、ペルチェ素子に密着したバイメタル構造の第１の金属板と第２の金属板との接点が外れ、ペルチェ素子を停止させ、再び温度が低下した場合、接点部分が接続してペルチェ素子が動作を開始するサーモスタット構造を有する半導体装置である。
【００２１】
具体的には図２に示すように、底面に外部電極を有し、表面に配線パターンを有し、その配線パターンと外部電極とが内部ビアで接続された積層基板であるキャリア基板１と、そのキャリア基板１の表面にバンプ２を介してその主面で接続された半導体素子３と、半導体素子３とキャリア基板１との間隙を充填封止したアンダーフィル樹脂４と、半導体素子３の裏面に配置されたペルチェ素子５と、そのペルチェ素子５の外囲面に密着させて設けたバイメタル原理を用いた金属板よりなるバイメタルサーモスタット７ａと、そのバイメタルサーモスタット７ａと一端が電気的、機械的に接点８を有して接続し、他端がバイメタルサーモスタット７ａからの熱をキャリア基板１に伝導させるとともに、電気的に接続したバイメタルサーモスタット７ｂとより構成されているものである。
【００２２】
本実施形態の半導体装置の放熱動作としては、図３（ａ）に示すように、まずペルチェ素子５の半導体素子３側の面が冷却され、バイメタルサーモスタット７ａ，７ｂ側で発熱し始める。この図３（ａ）の状態では、ペルチェ素子５、バイメタルサーモスタット７ａ，７ｂ、キャリア基板１が接続することにより、電気的に導通しているものである。
【００２３】
そして図３（ｂ）に示すように、ペルチェ素子５のバイメタルサーモスタット７ａ，７ｂ側の温度が上昇し、バイメタル自体が変形することにより、バイメタルサーモスタット７ｂの接点８が外れる。半導体素子３の温度がしきい値を超える前にペルチェ素子５のバイメタルサーモスタット７ａ，７ｂ側の温度が下降し、バイメタル自体が元の形状状態に戻り、サーモスタット７ｂの接点８がバイメタルサーモスタット７ａの端部と接触し、ペルチェ素子３への通電が再開された状態に戻る（図３（ａ））。
【００２４】
以上の動作を繰り返し、半導体素子３と、ペルチェ素子５の発熱面、冷却面の温度をある範囲内に安定させることができるものである。
【００２５】
なお、ここでも第１の実施形態と同様、半導体素子をフェースダウン搭載したＣＳＰを例に記述してるが、ＢＧＡ，ＱＦＰ等でも類似構造で同様な効果を得ることが可能である。
【００２６】
このように半導体素子３の発熱量が大きいとき、ペルチェ素子５に大きな電流が通電され続ける状態となるが、バイメタル構造のバイメタルサーモスタット７ａ，７ｂを用いることにより、ペルチェ素子５の発熱板が高温になった場合、バイメタル構造の金属板よりなるバイメタルサーモスタット７ａ，７ｂのそれぞれの金属の熱膨張係数差により、接点８が外れ、導通が解除されてペルチェ素子５が停止する。そして再び温度が低下してペルチェ素子５が冷えた場合、バイメタルサーモスタット７ａ，７ｂの接点８部分が接続してペルチェ素子５の動作を開始させることができる。
【００２７】
この時、ペルチェ素子５の熱容量を充分大きくすると半導体素子３の温度上昇を所望以下に抑えた状態でペルチェ素子５の発熱面の温度を下降させ、再びバイメタルサーモスタット７ａ，７ｂが通電してペルチェ素子５が半導体素子３の冷却を開始するという動作を繰り返すことが可能となり、半導体素子３を確実に所望温度以下にできる。したがってペルチェ素子５からの発熱も抑制し、かつバイメタルサーモスタット７ａ，７ｂのバイメタルを通じて効率よく外部へ伝達することができ、機器全体の雰囲気温度を安定させることができ、電子機器のシステムに誤動作、または動作不良をなくすことができる。
【００２８】
【発明の効果】
以上、本発明の半導体装置は、キャリア基板上に搭載した半導体素子の裏面または表面にペルチェ素子の冷却面を密着し、ペルチェ素子の発熱面に金属プレートを配置し、これを半導体素子を実装しているキャリア基材に電気的、かつ機械的に接続し、発熱面の熱を高熱伝導率の金属プレートを通してキャリア基板からキャリア基板を搭載している母配線基板に伝達し、放熱特性を高めることにより、ペルチェ素子の発熱面の温度上昇を所望範囲内におさめることが可能となり、半導体素子と機器全体の雰囲気温度を安定させることができ、システムに誤動作、または動作不良をなくすことができる。
【００２９】
また、金属プレートをバイメタル構造として、ペルチェ素子の発熱板が高温になった場合、バイメタル金属板のそれぞれの金属の熱膨張係数の差により接点が外れ、ペルチェ素子を停止させ、再び冷えた場合、接点部分が接続してペルチェ素子が動作を開始するサーモスタット構造を備えた構造とすることにより、半導体素子を確実に所望温度以下にするとともに、ペルチェ素子からの発熱も効率よく外部へ伝達し、かつ必要以上の発熱を抑えることができ、機器全体の雰囲気温度を安定させることができ、システムに誤動作、または動作不良をなくすことができる。
【図面の簡単な説明】
【図１】本発明の一実施形態の半導体装置を示す断面図
【図２】本発明の一実施形態の半導体装置を示す断面図
【図３】本発明の一実施形態の半導体装置の動作を示す断面図
【図４】従来の半導体装置を示す図
【符号の説明】
１ キャリア基板
２ バンプ
３ 半導体素子
４ アンダーフィル樹脂
５ ペルチェ素子
６ａ，６ｂ 金属プレート
７ａ，７ｂ バイメタルサーモスタット
８ 接点
１０１ ダイパッド
１０２ 温度制御回路素子
１０３ 半導体チップ
１０４ 冷却器
１０５ リード
１０６ 金属細線
１０７ 封止樹脂[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device provided with a cooling mechanism for mounting a semiconductor element with high power consumption.
[0002]
[Prior art]
In recent years, electronic devices have become more and more functional, operating speeds are increasing, and power consumption is increasing. For this reason, cooling of the semiconductor element is a big problem. Under such circumstances, many cooling mechanisms using Peltier elements have been proposed.
[0003]
As an example of a conventional semiconductor device, for example, as shown in Japanese Patent No. 2682586, a cooler made of a cooling semiconductor is bonded to the back side of the semiconductor chip directly or via a die pad, and the temperature is determined according to the detected temperature of the semiconductor chip. A structure has been proposed in which an output signal is output from a control circuit and applied to a cooler to suppress a rise in the temperature of the semiconductor chip to a predetermined temperature.
[0004]
Hereinafter, a conventional semiconductor device having a cooling mechanism will be described. FIG. 4 is a view showing a conventional semiconductor device having a cooling mechanism, FIG. 4 (a) is a transmissive plan view showing an internal configuration, and FIG. 4 (b) is a cross-sectional view of the central portion thereof. .
[0005]
As shown in the figure, a conventional semiconductor device having a cooling mechanism includes a power semiconductor chip 103 and a temperature control circuit element 102 mounted on a die pad 101 of a lead frame, and the bottom surface of the die pad 101 is made of a semiconductor. A cooler 104 is provided, and the semiconductor chip 103, the cooler 104, and the lead 105 are each electrically connected by a thin metal wire 106. The semiconductor chip 103, the cooler 104, and the internal lead portions of the leads 105 are surrounded by a sealing resin 107 as an outer periphery of the die pad 101.
[0006]
With the structure as described above, conventionally, the cooler 104 is bonded to the back surface of the semiconductor chip 103 directly or via the die pad 101, and an output signal is output from the temperature control circuit element 102 according to the detected temperature of the semiconductor chip 103, By giving to the cooler 104, the temperature rise of the semiconductor chip 103 was suppressed.
[0007]
[Problems to be solved by the invention]
However, in the conventional configuration, the temperature control circuit element is incorporated in the semiconductor element, or another semiconductor element having the temperature control circuit must be mounted in the package at the same time, and the heat generation surface of the Peltier element There is a problem of how to dissipate heat to the outside, and there is a problem with the mounting surface and the heat dissipation surface.
[0008]
In view of the above problems, the present invention has a cooling surface of a Peltier element in close contact with a back surface or a front surface of a semiconductor element mounted on a carrier substrate, and a metal plate having a bimetal structure is disposed on a heat generating surface of the Peltier element. Electrically and mechanically connected to the carrier base material mounting the heat, the heat of the heat generation surface is transmitted from the carrier base material to the mother wiring board mounting the carrier base material through the bimetallic metal plate with high thermal conductivity, In addition to enhancing the heat dissipation characteristics, if the Peltier element's heating plate becomes hot, the contact will come off due to the difference in the thermal expansion coefficient of each metal of the bimetallic metal plate, the Peltier element will stop, and if it cools again, the contact part will be connected Thus, a semiconductor device having a thermostat structure in which the Peltier element starts to operate is provided.
[0009]
[Means for Solving the Problems]
The semiconductor device of the present invention to solve the conventional problems, a semiconductor element, a base plate mounted with the semiconductor element, a Peltier element that is placed on the semiconductor element, the Peltier element a first metal plate coherent bimetal structure, the first end connected to the metal plate, the more becomes the semiconductor device and the second metal plate of the bimetal structure other end connected to the substrate.
[0011]
In the semiconductor device of the present invention, when the Peltier element reaches a high temperature, the second metal plate is deformed due to a difference in thermal expansion coefficient of the metal, and the first metal plate having a bimetal structure in close contact with the Peltier element When the contact with the second metal plate is removed, the Peltier element is stopped, and the temperature is lowered again, the semiconductor device has a thermostat structure in which the contact portion is connected and the Peltier element starts operating.
[0012]
As described above, the heat of the heat generating surface of the Peltier element can be efficiently transmitted to the substrate through the metal plate, and further the heat can be transferred from the substrate to the mother wiring substrate, thereby increasing the heat radiation efficiency to the air. . For this reason, the temperature rise of the heat generating surface of the Peltier device can be kept within a desired range, the ambient temperature of the semiconductor device and the entire device can be stabilized, and malfunction or malfunction of the system can be eliminated.
[0013]
In addition, when the heat generation amount of the semiconductor element is large, a large current continues to be applied to the Peltier element. By using a metal plate at this time as a thermostat using the bimetal principle, the heat generation plate of the Peltier element is heated to a high temperature. In this case, when the contact is released due to the difference in thermal expansion coefficient of each metal of the bimetal metal plate, the Peltier element is stopped and cooled again, the contact part of the thermostat is connected to start the operation of the Peltier element. it can. Here, when the heat capacity of the Peltier element is sufficiently increased, the temperature of the heat generating surface of the Peltier element is lowered with the temperature rise of the semiconductor element kept below the desired level, the thermostat is turned on again, and the Peltier element starts cooling the semiconductor element It is possible to repeat the operation of making sure that the temperature of the semiconductor element is below the desired temperature, the heat generated from the Peltier element is also efficiently transmitted to the outside, and the heat generation more than necessary can be suppressed. The temperature can be stabilized, and malfunction or malfunction of the system can be eliminated.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a semiconductor device of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing the semiconductor device of this embodiment.
[0015]
The semiconductor device according to the present embodiment includes a semiconductor element, a carrier substrate having the semiconductor element mounted thereon and wiring for inputting / outputting electrical signals and electric power of the semiconductor element, and one surface disposed on the front surface or the back surface of the semiconductor element. A semiconductor device includes a Peltier element, a metal plate in close contact with the other surface of the Peltier element, and a metal plate having one end connected to the metal plate and the other end connected to a carrier substrate.
[0016]
Specifically, as shown in the drawing, a carrier substrate 1 that is a laminated substrate having an external electrode on the bottom surface, a wiring pattern on the surface, and the wiring pattern and the external electrode connected by an internal via, and the carrier A semiconductor element 3 connected to the main surface of the substrate 1 via bumps 2 and an epoxy underfill resin 4 (sealing resin) filling and sealing the gap between the semiconductor element 3 and the carrier substrate 1; The Peltier element 5 disposed on the back surface of the semiconductor element 3, the metal plate 6a provided in close contact with the outer surface of the Peltier element 5, and the metal plate 6a are connected to the carrier substrate 1 from the metal plate 6a. It consists of a metal plate 6b that conducts heat and is electrically connected.
[0017]
In the heat countermeasure type semiconductor device of this embodiment, the heat of the heat generating surface of the Peltier element 5 is efficiently transmitted to the carrier substrate 1 through the metal plates 6a and 6b, and further, the mother wiring substrate (mounting substrate) By transferring heat to (not shown), it is possible to increase the diffusion area of the heat to the air, increase the heat dissipation efficiency, and suppress the temperature rise of the heat generating surface of the Peltier element 5 within a desired range. Thus, the atmospheric temperature of the entire electronic device can be stabilized. For this reason, malfunction or malfunction of the electronic device system can be eliminated. The metal plates 6a and 6b may be configured in a cap shape so long as the heat from the Peltier element 5 can be conducted to the carrier substrate 1.
[0018]
In the present embodiment, the structure of a CSP (Chip Size Package) in which a semiconductor element is mounted face down is described as an example. However, similar effects can be obtained with a similar structure in BGA (Ball Grid Array), QFP (Quad Flat Package), and the like. It is possible to obtain.
[0019]
Next, a second embodiment of the present invention will be described. FIG. 2 is a cross-sectional view showing the semiconductor device of this embodiment. FIG. 3 is a cross-sectional view showing the operation of the semiconductor device of the present embodiment. FIG. 3A shows a conductive state (initial state), and FIG. 3B shows a state when the temperature rises.
[0020]
First, in the semiconductor device of this embodiment, a semiconductor element, a carrier substrate having the semiconductor element mounted thereon and having wirings for inputting and outputting electrical signals and power of the semiconductor element, and one surface thereof are arranged on the front surface or the back surface of the semiconductor element. A taper element, a first metal plate with a bimetal structure in close contact with the other surface of the Peltier element, one end connected to the first metal plate to form a contact, and the other end connected to a carrier substrate A semiconductor device comprising a second metal plate having a bimetal structure, and when the Peltier element becomes hot, the second metal plate is deformed due to a difference in thermal expansion coefficient of the metal, and the bimetal structure is in close contact with the Peltier element. When the contact between the first metal plate and the second metal plate is released, the Peltier element is stopped, and the temperature is lowered again, a thermostat structure in which the contact part is connected and the Peltier element starts operating. It is a semiconductor device that.
[0021]
Specifically, as shown in FIG. 2, the carrier substrate 1 is a laminated substrate having an external electrode on the bottom surface, a wiring pattern on the surface, and the wiring pattern and the external electrode connected by internal vias; The semiconductor element 3 connected to the surface of the carrier substrate 1 via the bumps 2 via the main surface, the underfill resin 4 filling and sealing the gap between the semiconductor element 3 and the carrier substrate 1, and the back surface of the semiconductor element 3 A bimetal thermostat 7a made of a metal plate using a bimetal principle provided in close contact with the outer peripheral surface of the Peltier element 5, and one end of the bimetal thermostat 7a electrically and mechanically The bimetal thermostat is connected with a contact 8 and the other end conducts heat from the bimetal thermostat 7a to the carrier substrate 1 and is electrically connected. 7b and those which are more configurations.
[0022]
In the heat dissipation operation of the semiconductor device of this embodiment, as shown in FIG. 3A, first, the surface of the Peltier element 5 on the semiconductor element 3 side is cooled, and heat is generated on the bimetal thermostats 7a and 7b side. In the state of FIG. 3A, the Peltier element 5, the bimetal thermostats 7a and 7b, and the carrier substrate 1 are electrically connected to each other.
[0023]
As shown in FIG. 3B, when the temperature of the bimetal thermostat 7a, 7b side of the Peltier element 5 rises and the bimetal itself is deformed, the contact 8 of the bimetal thermostat 7b is released. Before the temperature of the semiconductor element 3 exceeds the threshold value, the temperature on the bimetal thermostat 7a, 7b side of the Peltier element 5 decreases, the bimetal itself returns to its original shape, and the contact 8 of the thermostat 7b is connected to the end of the bimetal thermostat 7a. It returns to the state which contacted the part and the electricity supply to the Peltier device 3 was restarted (FIG. 3A).
[0024]
By repeating the above operation, the temperatures of the heat generating surface and the cooling surface of the semiconductor element 3 and the Peltier element 5 can be stabilized within a certain range.
[0025]
Here, as in the first embodiment, a CSP in which a semiconductor element is mounted face-down is described as an example. However, similar effects can be obtained with a similar structure in BGA, QFP, and the like.
[0026]
As described above, when the amount of heat generated by the semiconductor element 3 is large, a large current continues to be applied to the Peltier element 5, but by using the bimetal thermostats 7a and 7b, the heat generating plate of the Peltier element 5 is heated to a high temperature. In this case, the contact 8 is released due to the difference in thermal expansion coefficient between the two metal thermostats 7a and 7b made of a metal plate having a bimetal structure, the conduction is released, and the Peltier element 5 stops. And when temperature falls again and the Peltier device 5 cools, the contact 8 part of bimetal thermostat 7a, 7b can connect, and the operation | movement of the Peltier device 5 can be started.
[0027]
At this time, if the heat capacity of the Peltier element 5 is sufficiently increased, the temperature of the heat generating surface of the Peltier element 5 is lowered in a state where the temperature rise of the semiconductor element 3 is suppressed to a desired level or less, and the bimetal thermostats 7a and 7b are energized again. 5 can repeat the operation of starting the cooling of the semiconductor element 3, and the semiconductor element 3 can be reliably brought to a desired temperature or lower. Therefore, heat generation from the Peltier element 5 is also suppressed, and the heat can be efficiently transmitted to the outside through the bimetal of the bimetal thermostats 7a and 7b, the atmospheric temperature of the entire device can be stabilized, and malfunctions in the system of the electronic device, or Malfunctions can be eliminated.
[0028]
【The invention's effect】
As described above, in the semiconductor device of the present invention, the cooling surface of the Peltier element is closely attached to the back surface or the front surface of the semiconductor element mounted on the carrier substrate, the metal plate is disposed on the heat generating surface of the Peltier element, and this is mounted on the semiconductor element. It is electrically and mechanically connected to the carrier substrate, and heat from the heat generation surface is transferred from the carrier substrate to the mother wiring board on which the carrier substrate is mounted through a metal plate with high thermal conductivity to improve heat dissipation characteristics. As a result, the temperature rise of the heat generating surface of the Peltier element can be kept within a desired range, the ambient temperature of the semiconductor element and the entire device can be stabilized, and malfunction or malfunction of the system can be eliminated.
[0029]
Also, if the metal plate has a bimetallic structure and the Peltier element's heating plate becomes hot, the contact will come off due to the difference in thermal expansion coefficient of each metal of the bimetallic metal plate, the Peltier element will stop, and it will cool again. By having a structure with a thermostat structure in which the contact portion is connected and the Peltier element starts operating, the semiconductor element is reliably brought to a desired temperature or less, and heat generated from the Peltier element is efficiently transmitted to the outside, and Heat generation more than necessary can be suppressed, the atmospheric temperature of the entire device can be stabilized, and malfunction or malfunction of the system can be eliminated.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the invention. FIG. 4 is a sectional view showing a conventional semiconductor device.
DESCRIPTION OF SYMBOLS 1 Carrier substrate 2 Bump 3 Semiconductor element 4 Underfill resin 5 Peltier element 6a, 6b Metal plate 7a, 7b Bimetal thermostat 8 Contact 101 Die pad 102 Temperature control circuit element 103 Semiconductor chip 104 Cooler 105 Lead 106 Metal fine wire 107 Sealing resin

Claims (2)

半導体素子と、前記半導体素子を搭載した基板と、前記半導体素子に配置されたぺルチェ素子と、前記ペルチェ素子に密着したバイメタル構造の第１の金属板と、前記第１の金属板に一端が接続して接点を構成し、他端が前記基板に接続したバイメタル構造の第２の金属板とよりなることを特徴とする半導体装置。And the semiconductor element, the semiconductor element mounted with board, and the semiconductor element to the placement has been Peltier element, a first metal plate bimetal structure in close contact with the Peltier element, the first A semiconductor device comprising: a second metal plate having a bimetal structure in which one end is connected to a metal plate to form a contact and the other end is connected to the substrate. ペルチェ素子が高温になった場合、金属の熱膨張係数の差により第２の金属板が変形し、前記ペルチェ素子に密着したバイメタル構造の第１の金属板と前記第２の金属板との接点が外れ、前記ペルチェ素子を停止させ、再び温度が低下した場合、前記接点部分が接続してペルチェ素子が動作を開始するサーモスタット構造を有することを特徴とする請求項１に記載の半導体装置。When the Peltier element becomes high temperature, the second metal plate is deformed due to the difference in the thermal expansion coefficient of the metal, and the contact point between the first metal plate having the bimetal structure and the second metal plate in close contact with the Peltier element 2. The semiconductor device according to claim 1 , wherein the semiconductor device has a thermostat structure in which the Peltier element starts operating when the Peltier element is stopped and the Peltier element is stopped and the temperature is lowered again.
JP2000036138A 2000-02-15 2000-02-15 Semiconductor device Expired - Lifetime JP3855576B2 (en)

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Publication number Priority date Publication date Assignee Title
KR101343049B1 (en) 2010-06-10 2013-12-18 에스티에스반도체통신 주식회사 Semiconductor package having function of heat dissipation

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JP3804629B2 (en) 2002-04-25 2006-08-02 ヤマハ株式会社 Thermoelectric device package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101343049B1 (en) 2010-06-10 2013-12-18 에스티에스반도체통신 주식회사 Semiconductor package having function of heat dissipation

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