JP3850484B2 - 高い訂正能力付きの順次アクセス可能なメモリ装置 - Google Patents

高い訂正能力付きの順次アクセス可能なメモリ装置 Download PDF

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Publication number
JP3850484B2
JP3850484B2 JP08413396A JP8413396A JP3850484B2 JP 3850484 B2 JP3850484 B2 JP 3850484B2 JP 08413396 A JP08413396 A JP 08413396A JP 8413396 A JP8413396 A JP 8413396A JP 3850484 B2 JP3850484 B2 JP 3850484B2
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JP
Japan
Prior art keywords
row
column
clock signal
selection device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP08413396A
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English (en)
Japanese (ja)
Other versions
JPH08287699A (ja
Inventor
フォン バッセ パウル−ヴェルナー
ボル ミヒャエル
テーヴェス ローラント
シュミット−ラントズィーデル ドリス
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Siemens AG
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Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH08287699A publication Critical patent/JPH08287699A/ja
Application granted granted Critical
Publication of JP3850484B2 publication Critical patent/JP3850484B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/86—Masking faults in memories by using spares or by reconfiguring in serial access memories, e.g. shift registers, CCDs, bubble memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Debugging And Monitoring (AREA)
JP08413396A 1995-04-05 1996-04-05 高い訂正能力付きの順次アクセス可能なメモリ装置 Expired - Fee Related JP3850484B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19512791.9 1995-04-05
DE19512791 1995-04-05

Publications (2)

Publication Number Publication Date
JPH08287699A JPH08287699A (ja) 1996-11-01
JP3850484B2 true JP3850484B2 (ja) 2006-11-29

Family

ID=7758876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP08413396A Expired - Fee Related JP3850484B2 (ja) 1995-04-05 1996-04-05 高い訂正能力付きの順次アクセス可能なメモリ装置

Country Status (7)

Country Link
US (1) US5751742A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0738974B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JP3850484B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR100409113B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
AT (1) ATE217987T1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE59609221D1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW312763B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE186152T1 (de) * 1995-09-13 1999-11-15 Siemens Ag Einrichtung zum sprungweisen adressieren bestimmter leitungen eines seriell arbeitenden digitalen speichers
TW399219B (en) * 1997-09-26 2000-07-21 Siemens Ag Pointer-circuit with small space requirement, higher speed and smaller power loss
ATE430365T1 (de) * 2003-05-22 2009-05-15 Nxp Bv Test von ram addressdekodierern auf widerstandsbehaftete leiterunterbrechungen

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3812336A (en) * 1972-12-18 1974-05-21 Ibm Dynamic address translation scheme using orthogonal squares
JPS58139399A (ja) * 1982-02-15 1983-08-18 Hitachi Ltd 半導体記憶装置
EP0189699B1 (en) * 1984-12-26 1992-09-30 STMicroelectronics, Inc. Interdigitated bit line rom
KR910009588B1 (ko) * 1987-05-06 1991-11-21 니뽄 덴끼 가부시끼가이샤 직렬 어드레싱 회로를 갖는 직렬 억세스 메모리 회로
JP2816512B2 (ja) * 1992-07-27 1998-10-27 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
KR100409113B1 (ko) 2004-03-18
US5751742A (en) 1998-05-12
JPH08287699A (ja) 1996-11-01
ATE217987T1 (de) 2002-06-15
KR960038976A (ko) 1996-11-21
EP0738974B1 (de) 2002-05-22
EP0738974A2 (de) 1996-10-23
TW312763B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1997-08-11
EP0738974A3 (de) 1999-06-02
DE59609221D1 (de) 2002-06-27

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