JP3848374B2 - フローティングゲートメモリの集積回路 - Google Patents

フローティングゲートメモリの集積回路 Download PDF

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Publication number
JP3848374B2
JP3848374B2 JP54226097A JP54226097A JP3848374B2 JP 3848374 B2 JP3848374 B2 JP 3848374B2 JP 54226097 A JP54226097 A JP 54226097A JP 54226097 A JP54226097 A JP 54226097A JP 3848374 B2 JP3848374 B2 JP 3848374B2
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JP
Japan
Prior art keywords
cells
voltage
threshold
potential
volts
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP54226097A
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English (en)
Japanese (ja)
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JPH11509955A (ja
JPH11509955A5 (enExample
Inventor
ツェン ヒューエイ シアウ
レイ リン ワン
ユーアン チャン リウ
チュン シウン ヒュン
ワイトン チュアン
ハン スン チェン
フューチア ショーン
Original Assignee
マクロニクス インターナショナル カンパニー リミテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by マクロニクス インターナショナル カンパニー リミテッド filed Critical マクロニクス インターナショナル カンパニー リミテッド
Publication of JPH11509955A publication Critical patent/JPH11509955A/ja
Publication of JPH11509955A5 publication Critical patent/JPH11509955A5/ja
Application granted granted Critical
Publication of JP3848374B2 publication Critical patent/JP3848374B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
JP54226097A 1996-05-22 1996-05-22 フローティングゲートメモリの集積回路 Expired - Lifetime JP3848374B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1996/007490 WO1997044791A1 (en) 1996-05-22 1996-05-22 Flash memory erase with controlled band-to-band tunneling current

Publications (3)

Publication Number Publication Date
JPH11509955A JPH11509955A (ja) 1999-08-31
JPH11509955A5 JPH11509955A5 (enExample) 2004-07-15
JP3848374B2 true JP3848374B2 (ja) 2006-11-22

Family

ID=22255145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54226097A Expired - Lifetime JP3848374B2 (ja) 1996-05-22 1996-05-22 フローティングゲートメモリの集積回路

Country Status (4)

Country Link
EP (1) EP0840929B1 (enExample)
JP (1) JP3848374B2 (enExample)
DE (1) DE69618206T2 (enExample)
WO (1) WO1997044791A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6385093B1 (en) * 2001-03-30 2002-05-07 Advanced Micro Devices, Inc. I/O partitioning system and methodology to reduce band-to-band tunneling current during erase
TWI679647B (zh) * 2019-01-24 2019-12-11 華邦電子股份有限公司 抹除方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0447595A (ja) * 1990-06-15 1992-02-17 Mitsubishi Electric Corp 不揮発性半導体記憶装置
JP3105109B2 (ja) * 1993-05-19 2000-10-30 株式会社東芝 不揮発性半導体記憶装置
US5424993A (en) * 1993-11-15 1995-06-13 Micron Technology, Inc. Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device
US5416738A (en) * 1994-05-27 1995-05-16 Alliance Semiconductor Corporation Single transistor flash EPROM cell and method of operation
US5487033A (en) * 1994-06-28 1996-01-23 Intel Corporation Structure and method for low current programming of flash EEPROMS
US5485423A (en) * 1994-10-11 1996-01-16 Advanced Micro Devices, Inc. Method for eliminating of cycling-induced electron trapping in the tunneling oxide of 5 volt only flash EEPROMS

Also Published As

Publication number Publication date
WO1997044791A1 (en) 1997-11-27
EP0840929A1 (en) 1998-05-13
EP0840929B1 (en) 2001-12-19
DE69618206D1 (de) 2002-01-31
DE69618206T2 (de) 2002-08-08
EP0840929A4 (en) 1999-06-30

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