JP3838593B2

JP3838593B2 - Semiconductor device inspection method and semiconductor device inspection device

Info

Publication number: JP3838593B2
Application number: JP08643797A
Authority: JP
Inventors: 伸一沖; 義朗中田; 知之中山
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 1997-04-04
Filing date: 1997-04-04
Publication date: 2006-10-25
Anticipated expiration: 2017-04-04
Also published as: JPH10284553A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置の検査方法及び検査装置に関し、特に、半導体ウェハに形成された複数の半導体集積回路装置に対して一括してバーンインを行なう半導体装置の検査方法及び検査装置に関する。
【０００２】
【従来の技術】
従来、半導体装置は、半導体集積回路素子とリードフレームとがボンディングワイヤによって電気的に接続された後、半導体集積回路素子とリードフレームのリードとが樹脂又はセラミックスにより封止された状態で供給されて、プリント基板に実装される。
【０００３】
ところが、電子機器の小型化及び低価格化の要求から、半導体装置を半導体ウェハから切り出したままのベアチップ状態で回路基板に実装する方法が開発されており、品質が保証されたベアチップを低価格で供給することが望まれている。ベアチップに対して品質保証を行なうためには、一の半導体ウェハ上に形成された複数の半導体装置に対して一括してバーンインを行なうことが低コスト化の点で好ましい。
【０００４】
このため、半導体ウェハ上に形成された複数の半導体装置の各検査用電極と接続されるバンプを有するコンタクタを用いて、半導体ウェハ上に形成された複数の半導体装置に対してウェハ状態で一括してバーンインを行なう検査方法が提案されている。
【０００５】
ところで、半導体ウェハ上に形成された複数の半導体装置に対してウェハ状態で一括してバーンイン工程を行なうためには、バーンイン工程の前に各半導体装置に対して行なう電気特性の良否判定工程も、ウェハ状態で一括して行なう必要がある。このため、電気特性の良否判定工程は、半導体ウェハの上に形成された複数の半導体装置の検査用電極と対応する位置にバンプを有し且つ半導体ウェハと同程度の大きさを持つプローブカードを用い、プローブカードのバンプと半導体装置の検査用電極とのアライメントを行なった後、プローブカードを半導体ウェハに押し付けてプローブカードの各バンプと半導体装置の各検査用電極とを接触させ、その後、バンプに電源電圧や信号を印加して半導体装置の電気特性の検査を行なう。
【０００６】
【発明が解決しようとする課題】
ところで、半導体装置の検査用電極は通常アルミニウム等の酸化し易い金属により形成されているため、検査用電極の表面はアルミナ等の表面酸化膜によって覆われている。このため、プローブカードのバンプと半導体装置の検査用電極との良好な電気的接続を得るためには、プローブカードを半導体ウェハに対して押圧し、該押圧力によって表面酸化膜を破る必要がある。
【０００７】
ところが、半導体ウェハ上に形成される半導体装置の数が多くなってくると、プローブカードに形成されるバンプの数が増加し、バンプ１個当たりに加えられる押圧力は減少せざるを得ない。このため、表面酸化膜をバンプによって確実に破ることができなくなり、バンプと検査用電極との間の接触抵抗にバラツキが生じ、バーンイン工程の前に行なう電気特性の良否の検査が正確に行なわれないという第１の問題がある。
【０００８】
また、半導体ウェハ上に形成された複数の半導体装置の各検査用電極に、コンタクタのバンプを介して電源電圧又は信号を印加してウェハ状態で一括してバーンインを行なう際に、半導体ウェハとコンタクトとのアライメントが正確に行なわれていなかったり又は複数の半導体装置の各検査用電極とコンタクタの各バンプとの間に異物が介在したりすると、検査用電極とバンプとの電気的接続が確実に行なわれないために、バーンインが正確に行なわれないという第２の問題もある。
【０００９】
前記に鑑み、本発明は、バーンイン工程の前に行なう電気特性の検査が正確に行なわれるようにすることを第１の目的とし、バーンイン工程のおいて検査用電極とバンプとの電気的接続を確実にしてバーンインが正確に行なわれるようにすることを第２の目的とする。
【００１０】
【課題を解決するための手段】
本発明に係る第１の半導体装置の検査方法は、前記の第１の目的を達成するものであって、凹凸形成用カードを用いて、半導体ウェハ上に形成された複数の半導体装置の検査用電極の表面部に凹凸を形成する凹凸形成工程と、半導体ウェハと、複数の半導体装置の検査用電極と対応する部位にバンプを有するコンタクタとを接触させて、表面部に凹凸が形成された検査用電極とバンプとを電気的に接続する電極接続工程と、バンプを介して検査用電極に電源電圧又は信号を印加して、複数の半導体装置の電気特性の良否を検査する特性検査工程とを備えている。
【００１１】
第１の半導体装置の検査方法によると、半導体装置の検査用電極の表面部に凹凸を形成した後に、半導体装置の検査用電極とコンタクタのバンプとを電気的に接続するため、検査用電極とバンプとは検査用電極の表面部に形成されている自然酸化膜が破れたり波打ったりしている状態で接触するので、検査用電極とバンプとは電気的に確実に接続する。
【００１２】
第１の半導体装置の検査方法において、凹凸形成工程は、検査用電極の表面に形成されている自然酸化膜に破れ目を形成する工程を含み、また、電極接続工程は、凹凸形成工程において形成された自然酸化膜の破れ目に新しい自然酸化膜が形成される前に、検査用電極とバンプとを電気的に接続する工程を含むことが好ましい。
【００１３】
第１の半導体装置の検査方法において、電極接続工程は、検査用電極の表面に形成されている自然酸化膜を破りつつ、検査用電極とバンプとを電気的に接続する工程を含むことが好ましい。
【００１４】
本発明に係る第２の半導体装置の検査方法は、前記の第２の目的を達成するものであって、半導体ウェハの上に形成された複数の半導体装置の検査用電極に電源電圧又は信号を印加して複数の半導体装置の電気特性の良否を検査する特性検査工程と、半導体ウェハと、複数の半導体装置の検査用電極と対応する位置にプローブ端子を有するコンタクタとを接触させて、検査用電極とプローブ端子とを接続する電極接続工程と、特性検査工程において電気的特性が良であると認識された良品半導体装置の全ての検査用電極のうちの少なくとも２つの検査用電極に、半導体ウェハと接触しているコンタクタのプローブ端子を介して電源電圧又は信号を印加して検査用電極とプローブ端子との電気的接続の良否を検査する接続検査工程と、接続検査工程における検査結果が良好であると判断する場合に、半導体ウェハと接触しているコンタクタのプローブ端子を介して検査用電極に電源電圧又は信号を印加してバーンインを行なうバーンイン工程とを備えている。
【００１５】
第２の半導体装置の検査方法によると、電気的特性が良であると認識された良品半導体装置の全ての検査用電極のうちの少なくとも２つの検査用電極にプローブ端子を介して電源電圧又は信号を印加して検査用電極とプローブ端子との電気的接続の良否を検査し、該検査の結果が良好であると判断する場合にバーンインを行なうため、バーンイン工程は、半導体ウェハとコンタクタとのアライメントが正確に行なわれた状態で行なわれる。
【００１６】
本発明に係る第３の半導体装置の検査方法は、前記の第２の目的を達成するものであって、半導体ウェハの上に形成された複数の半導体装置の検査用電極に電源電圧又は信号を印加して複数の半導体装置の電気特性の良否を検査する特性検査工程と、特性検査工程において得られた半導体装置の電気特性の良否結果を良否データとして保存しておくデータ保存工程と、半導体ウェハと、複数の半導体装置の検査用電極と対応する位置にプローブ端子を有するコンタクタとを接触させて、検査用電極とプローブ端子とを接続する電極接続工程と、複数の半導体装置の検査用電極に、半導体ウェハと接触しているコンタクタのプローブ端子を介して電源電圧又は信号を印加して検査用電極とプローブ端子との電気的接続の良否を検査し、該検査により得られた良否結果とデータ保存工程において保存されている良否データとを比較することにより、検査用電極とプローブ端子との電気的接続の良否を検査する接続検査工程と、接続検査工程における検査結果が良好であると判断する場合に、半導体ウェハと接触しているコンタクタのプローブ端子を介して検査用電極に電源電圧又は信号を印加してバーンインを行なうバーンイン工程とを備えている。
【００１７】
第３の半導体装置の検査方法によると、特性検査工程において行なった半導体装置の電気特性の良否の検査結果と、接続検査工程において行なう検査用電極とプローブ端子との電気的接続の良否の検査結果とを比較して、検査用電極とプローブ端子との電気的接続の良否を検査し、該検査の結果が良好であると判断する場合にバーンインを行なうため、バーンイン工程は、検査用電極とプローブ端子との電気的接続が確実な状態で行なわれる。
【００１８】
本発明に係る第１の半導体装置の検査装置は、前記の第１の目的を達成するものであって、半導体ウェハ上に形成された複数の半導体装置の検査用電極と対応する部位に、検査用電極の表面部に凹凸を形成するための凹凸形成用バンプを有する凹凸形成用カードからなる凹凸形成手段と、検査用電極と凹凸形成用バンプとが接触するように、半導体ウェハと凹凸形成手段とを互いに接近させる第１の接近手段と、検査用電極と、複数の半導体装置の検査用電極と対応する部位にバンプを有するコンタクタのバンプとが接触するように、半導体ウェハとコンタクタとを互いに接近させる第２の接近手段と、検査用電極と接触しているバンプに電源電圧又は信号を印加して、複数の半導体装置の電気特性の良否を検査する特性検査手段とを備えている。この場合、第１の接近手段と第２の接近手段とは、同じ手段であってもよいし異なる手段であってもよい。
【００１９】
第１の半導体装置の検査装置によると、凹凸形成手段により半導体装置の検査用電極の表面部に凹凸を形成して、検査用電極の表面部に形成されている自然酸化膜を破ったり波打たせた状態で、半導体装置の検査用電極とコンタクタのバンプとを接続できるので、検査用電極とバンプとを電気的に確実に接続することができる。
【００２０】
第１の半導体装置の検査装置は、検査用電極と凹凸形成用バンプとをアライメントするアライメント手段をさらに備えていることが好ましい。
【００２１】
また、第１の半導体装置の検査装置は、凹凸形成用バンプに付着した付着物を除去する付着物除去手段をさらに備えていることが好ましい。
【００２２】
本発明に係る第２の半導体装置の検査装置は、前記の第２の目的を達成するものであって、半導体ウェハの上に形成された複数の半導体装置の検査用電極に電源電圧又は信号を印加して複数の半導体装置の電気特性の良否を検査する特性検査手段と、半導体ウェハと、複数の半導体装置の検査用電極と対応する位置にプローブ端子を有するコンタクタとを接触させて、検査用電極とプローブ端子とを接続させる電極接続手段と、特性検査手段により電気的特性が良であると認識された良品半導体装置の全ての検査用電極のうちの少なくとも２つの検査用電極に、半導体ウェハと接触しているコンタクタのプローブ端子を介して電源電圧又は信号を印加して、検査用電極とプローブ端子との電気的接続の良否を検査する接続検査手段とを備えている。
【００２３】
第２の半導体装置の検査装置によると、接続検査手段により、電気的特性が良であると認識された良品半導体装置の全ての検査用電極のうちの少なくとも２つの検査用電極にプローブ端子を介して電源電圧又は信号を印加して検査用電極とプローブ端子との電気的接続の良否を検査するため、該検査の結果が良好と判断される場合、つまり半導体ウェハとコンタクタとのアライメントが良好な場合にのみ、バーンインを行なうことができる。
【００２４】
本発明に係る第３の半導体装置の検査装置は、前記の第２の目的を達成するものであって、半導体ウェハの上に形成された複数の半導体装置の検査用電極に電源電圧又は信号を印加して複数の半導体装置の電気特性の良否を検査し、得られた電気的特性の良否結果を良否データとして保存しておく特性検査手段と、半導体ウェハと、複数の半導体装置の検査用電極と対応する位置にプローブ端子を有するコンタクタとを接触させて、検査用電極とプローブ端子とを接続する電極接続手段と、複数の半導体装置の検査用電極に、半導体ウェハと接触しているコンタクタのプローブ端子を介して電源電圧又は信号を印加して、検査用電極とプローブ端子との電気的接続の良否を検査し、該検査により得られた良否結果と特性検査手段に保存されている良否データとを比較することにより、検査用電極とプローブ端子との電気的接続の良否を検査する接続検査手段とを備えている。
【００２５】
第３の半導体装置の検査装置によると、接続検査手段は、検査用電極とプローブ端子との電気的接続の良否を検査した結果と、特性検査手段に保存されている良否データとを比較して、最終的な電気的接続の良否を検査するため、検査用電極とプローブ端子とが電気的に確実に接続されている状態でバーンインを行なうことができる。
【００２６】
【発明の実施の形態】
図１は本発明の一実施形態に係る半導体装置の検査装置の全体構成を示している。図１に示すように、半導体装置の検査装置は、半導体ウェハが収納されたウェハトレーを載置しておくトレー載置部１と、半導体ウェハに形成された半導体装置の検査用電極の表面に凹凸を形成する凹凸形成部２と、半導体ウェハの上にプローブカードを搭載して、半導体ウェハの上に形成された半導体装置の検査用電極とプローブカードのバンプとを接続するプローブカード搭載部３と、半導体装置の検査用電極とプローブカードのバンプとの電気的接続の良否を検査する接続検査装置４と、半導体ウェハが収納されたウェハトレーを、トレー載置部１から凹凸形成部２へ移動させた後、凹凸形成部２からプローブカード搭載部３へ移動させたり、プローブカード搭載部３からトレー載置部１に移動させたりするＸＹＺ可動ステージ５とを備えている。尚、トレー載置部１には、ウェハトレーをトレー載置部１とＸＹＺ可動ステージ５との間で移動させるローダ／アンローダが設けられている。
【００２７】
図２は、接続検査装置４の構成及び接続検査装置４とプローブカード搭載部３との関係を示しており、図２に示すように、接続検査装置４は、プローブカードのバンプに電気信号を印加して半導体ウェハ上の半導体装置の電気特性を検査する特性検査手段４ａと、半導体装置の検査用電極とプローブカードのバンプとの電気的接続の良否を検査する接続検査手段４ｂとを有している。
【００２８】
以下、本発明の一実施形態に係る半導体装置の検査方法及び検査装置について詳細に説明する。
【００２９】
（凹凸形成工程）
まず、図３（ａ）を参照しながら、凹凸形成部２において行なわれる、半導体ウェハ上に形成された複数の半導体装置の検査用電極の表面部に凹凸を形成する凹凸形成工程について説明する。
【００３０】
半導体ウェハ載置部の周囲にＯリング６を有するウェハトレー７の上に半導体ウェハ８を収納した後、半導体ウェハ８を収納したウェハトレー７をトレー載置部１からＸＹＺ可動ステージ５の上に移動した後、ＸＹＺ可動ステージ５を駆動してウェハトレー７を凹凸形成部２に移動する。
【００３１】
次に、半導体ウェハ８と凹凸形成手段としての凹凸形成用カード９とのアライメントを行なった後、ＸＹＺ可動ステージ５を駆動して、半導体ウェハ８を凹凸形成用カード９に対して押圧して、半導体装置の検査用電極１０の表面部に凹凸を形成する。この場合、ＸＹＺ可動ステージ５は、半導体ウェハと凹凸形成手段とを互いに接近させる第１の接近手段を構成している。
【００３２】
図４（ａ）は、検査用電極１０の表面部に凹凸を形成する第１の方法を示しており、該第１の方法は、半導体ウェハ８に形成された半導体装置の検査用電極１０と対応する位置に、例えばＮｉよりなる短円柱状又は短角柱状の凹凸形成用バンプ１１Ａを有する凹凸形成用カード９Ａを用いて行なわれる。第１の方法は、半導体装置の検査用電極１０と凹凸形成用カード９Ａの凹凸形成用バンプ１１Ａとを接触させた後、凹凸形成用カード９Ａを半導体ウェハ８と平行な平面内で往復運動又は回転運動させることにより、半導体装置の検査用電極１０の表面部に凹凸を形成するものである。
【００３３】
図４（ｂ）は、検査用電極１０の表面部に凹凸を形成する第２の方法を示しており、該第２の方法は、半導体装置の検査用電極１０と対応する位置に、表面に凹凸部を有する例えばＮｉよりなる半球状の凹凸形成用バンプ１１Ｂを有する凹凸形成用カード９Ｂを用いて行なわれる。第２の方法は、半導体装置の検査用電極１０に対して凹凸形成用カード９Ｂの凹凸形成用バンプ１１Ｂを押し付けて、該凹凸形成用バンプ１１Ｂの表面の凹凸部を検査用電極１０の表面に転写することにより、半導体装置の検査用電極１０の表面部に凹凸を形成するものである。凹凸形成用バンプ１１Ｂの表面の凹凸部は、半球状の凹凸形成用バンプ１１Ｂを、表面に０．１μｍ〜数μｍの凹凸部を有するセラミック板に押し付けたり、半球状の凹凸形成用バンプ１１Ｂの表面に、電気メッキ法によって粒径が１〜１０μｍ程度の粒子よりなるメッキ層を形成したりすることにより形成できる。
【００３４】
前記の第１の方法又は第２の方法を行なうと、検査用電極１０の表面部に凹凸が形成されるため、検査用電極１０の表面部に形成されている自然酸化膜に破れ目が形成されたり、又は自然酸化膜が大きな波打ち状になったりする。
【００３５】
尚、半導体装置の検査用電極１０と凹凸形成用バンプ１１Ａ，１１Ｂとの接触を繰り返すと、凹凸形成用バンプ１１Ａ，１１Ｂの表面に、アルミニウム等の異物が付着してしまう。そこで、図示は省略したが、エアブロー手段、ワイヤブラシのようなブラシ手段又は表面に凹凸を有するセラミック板等の付着物除去手段を設け、エアブロー手段から凹凸形成用バンプ１１Ａ，１１Ｂの表面にエアを吹き付けたり、又は凹凸形成用バンプ１１Ａ，１１Ｂの表面をブラシ手段又はセラミック板と摺接させたりして、凹凸形成用バンプ１１Ａ，１１Ｂの表面に付着した付着物を除去することが好ましい。
【００３６】
（電極接続工程）
次に、図３（ｂ）を参照しながら、プローブカード搭載部３において行なわれる、半導体ウェハ８と、半導体装置の検査用電極１０と対応する部位にバンプ１２を有するコンタクタとしてのプローブカード１３とを接触させて、表面部に凹凸が形成された検査用電極１０とバンプ１２とを電気的に接続する電極接続工程について説明する。
【００３７】
半導体ウェハ８を収納したウェハトレー７を凹凸形成部２からＸＹＺ可動ステージ５の上に移動した後、ＸＹＺ可動ステージ５を駆動してウェハトレー７をプローブカード搭載部３に移動する。
【００３８】
次に、半導体ウェハ８とプローブカード１３とのアライメントを行なった後、ＸＹＺ可動ステージ５を駆動してプローブカード１３を半導体ウェハ８に押し付ける。この場合、ＸＹＺ可動ステージ５は、半導体ウェハとコンタクタとを互いに接近させる第２の接近手段を構成している。前述したように、ウェハトレー７における半導体ウェハ載置部の周囲にはＯリング６が設けられているため、該Ｏリング６の内側の半導体載置部を減圧することにより、プローブカード１３は半導体ウェハ８に大気圧による適当な押圧力で押し付けられるので、半導体ウェハ８の上に形成された半導体装置の検査用電極１０とプローブカード１３のバンプ１２とは確実に接触する。
【００３９】
また、凹凸形成工程において検査用電極１０の表面部に凹凸が形成されているため、検査用電極１０の表面部に形成されている自然酸化膜には破れ目が形成されているか、又は自然酸化膜は大きな波打ち状になっている。このため、電極接続工程において、検査用電極１０とバンプ１２とを接触させると、バンプ１２の押圧力によって、検査用電極１０の表面の自然酸化膜の破れ目が大きくなったり又は自然酸化膜の波打ち状が破れ目に変わったりするので、検査用電極１０とバンプ１２との間の電気的抵抗は低減している。
【００４０】
尚、凹凸形成工程において、検査用電極１０の表面の自然酸化膜に破れ目が形成されている場合には、該破れ目に新たな自然酸化膜が形成されるよりも前に電極接続工程を行なって、検査用電極１０とバンプ１２とを電気的に接続することが好ましい。
【００４１】
また、凹凸形成工程及び電極接続工程は、例えば窒素ガス雰囲気中で行ない、新たな自然酸化膜が形成されない環境下で行なうことが好ましい。
【００４２】
（特性検査工程）
次に、接続検査装置４の特性検査手段４ａによって、電源電圧又は信号をプローブカード１３の外部からプローブカード１３のバンプ１２を介して検査用電極１０に印加して、半導体装置の電気特性の良否を検査する特性検査工程を行なう。前述したように、検査用電極１０の表面の自然酸化膜に破れ目が形成され、検査用電極１０とバンプ１２との間の電気抵抗が大きく低減しているので、半導体ウェハ８の上に形成されている全ての半導体装置の電気特性を良好且つ確実に検査することができる。
【００４３】
この特性検査工程において電気的特性の良否を検査した結果のデータ、すなわち、電気的特性が予定された特性を満たしている良品半導体装置と、電気的特性が予定された特性を満たしていない不良品の半導体装置との判定結果である良否データは、接続検査手段４ｂに転送され、該接続検査手段４ｂが有している記憶手段に保存される。
【００４４】
（不良品半導体装置の絶縁化工程）
次に、特性検査工程が完了した半導体ウェハは、ウェハトレー７に収納された状態で、ＸＹＺ可動ステージ５によりトレー載置部１に移動され、トレー載置部１から、図示していない絶縁膜形成装置に移動され、該絶縁膜形成装置において、半導体ウェハの上に形成されている半導体装置のうち、特性検査工程において不良品と判定された不良品半導体装置を絶縁化する。すなわち、不良品半導体装置の表面に全面に亘って、又は不良品半導体装置の全ての検査用電極の表面に、又は不良品半導体装置における電気的特性の不良個所と電気的に接続されている特定の検査用電極の表面に、絶縁性樹脂等を塗布して、不良品半導体装置の不良個所に電流が流れないようにする。
【００４５】
ところで、次工程のバーンイン工程において、全ての半導体装置の各検査用電極に個別の配線から電源電圧又は信号を印加すると、著しく多数の配線が必要になるので、この弊害を回避するため、共通の電源電圧線又は信号線を経由して各検査用電極１０に電源電圧又は信号を印加することが好ましい。ところが、共通の電源電圧線又は信号線を経由して各検査用電極１２に電源電圧又は信号を印加すると、内部において電気的に短絡している半導体装置を経由して共通の電源電圧線又は信号線に多量の電流が流れてしまう恐れがある。そこで、不良品半導体装置の絶縁化工程において、不良品半導体装置の不良個所に電流が流れないようにするのである。
【００４６】
（接続検査工程）
次に、不良品半導体装置の絶縁化工程が完了した半導体ウェハは、ウェハトレー７に収納された状態でトレイ載置部１に再び移動された後、ＸＹＺ可動ステージ５により、プローブカード搭載部３に移動され、該プローブカード搭載部３において、再び、プローブカード１３と半導体ウェハ８とのアライメントを行なった後、プローブカード１３を半導体ウェハ８に押し付ける。
【００４７】
次に、接続検査装置４の接続検査手段４ｂは、プローブカード１３のバンプ１２を介して半導体ウェハ８の半導体装置の検査用電極１０に電源電圧又は信号を印加して、検査用電極１０とバンプ１２との電気的接続の良否を検査する。
【００４８】
ところで、不良品半導体装置の絶縁化工程が終了した半導体装置に対しては、次工程において、ウェハ状態で一括してバーンインを行なうが、この場合、半導体ウェハ８とプローブカード１３とのアライメントが正しく行なわれていること、良品の半導体装置の検査用電極１０とプローブカード１３のバンプ１２とが電気的に導通していること、及び、不良品の半導体装置の検査用電極１０とプローブカード１３のバンプ１２とが電気的に導通していないこと等を確認することが望まれる。
【００４９】
そこで、接続検査装置４の接続検査手段４ｂは、プローブカード１３のバンプ１２を介して半導体装置の検査用電極１０に電源電圧又は信号を印加して、半導体装置の検査用電極１０とプローブカード１３のバンプ１２との電気的接続の良否を検査する。具体的には、接続検査手段４ａは、該接続検査工程において行なった電気的接続の良否の結果と、電気特性検査工程において行なった後、記憶手段に保存している良否データとを比較することにより、半導体ウェハ８とプローブカード１３とのアライメントが正しく行なわれているか否か、良品の半導体装置の検査用電極１０とプローブカード１３のバンプ１２とが電気的に導通しているか否か、及び、不良品の半導体装置の検査用電極１０とプローブカード１３のバンプ１２とが電気的に導通しているか否かの検査のうち、少なくとも１つの検査を行なう。
【００５０】
この接続検査工程においては、電源電圧又は信号を印加する半導体装置及び検査用電極１０の数が多ければ多いほど、半導体装置の検査用電極１０とプローブカード１３のバンプ１２との接続検査の精度は高くなるが、接続検査に要する時間は長くなる。従って、接続検査の精度と接続検査に要する時間とを考慮して、電源電圧又は信号を印加する半導体装置及び検査用電極１０の数を決定することが好ましい。
【００５１】
従って、特性検査工程において電気的特性が良であると認識された良品半導体装置の全ての検査用電極１０のうちの少なくとも２つの検査用電極１０に、プローブカード１３のバンプ１２を介して電源電圧又は信号を印加して、検査用電極１０とバンプ１２との電気的接続の良否を検査する場合には、半導体ウェハ８とプローブカード１３とのアライメントが正しく行なわれているか否かの検査を行なうことができる。
【００５２】
（バーンイン工程）
半導体装置の検査用電極１０とプローブカード１３のバンプ１２との電気的接続の検査の結果が満足できない場合には、半導体ウェハ８とプローブカード１３とのアライメントをやり直す一方、前記電気的接続の検査の結果が満足できる場合には、プローブカード１３のバンプ１２を介して半導体ウェハ８の半導体装置の検査用電極１０に電源電圧又は信号を印加してバーンインを行なう。このバーンイン工程においては用いるコンタクタは特に限定されず、特開平７−１６９８０６号公報及び特開平８−５６６６号公報等において示されているプローブカードやプローブシート等を適宜用いることができる。
【００５３】
尚、以上説明した全ての工程を行なうと、バーンインを極めて確実に行なうことができるが、いくつかの工程を省略してもよいのは当然である。例えば、凹凸形成工程を省略しても電極接続工程が良好に行なわれる場合には、凹凸形成工程を省略できるし、接続検査工程を省略してもバーンイン工程が差し支えない程度に行なわれる場合には、接続検査工程を省略してもよい。
【００５４】
また、凹凸形成工程は、コンタクタに形成されたバンプに対して行なうことが効果的であるが、接続検査工程はコンタクタに形成されるプローブ端子の構造は問わない。
【００５５】
【発明の効果】
第１の半導体装置の検査方法によると、半導体装置の検査用電極の表面部に凹凸を形成して、検査用電極の表面部に形成されている自然酸化膜が破れたり波打ったりしている状態で、半導体装置の検査用電極とコンタクタのバンプとを接触するため、検査用電極とバンプとを電気的に確実に接続させることができる。
【００５６】
第１の半導体装置の検査方法において、自然酸化膜の破れ目に新しい自然酸化膜が形成される前に、検査用電極とバンプとを電気的に接続すると、検査用電極とバンプとの電気的接続がより確実になる。
【００５７】
また、第１の半導体装置の検査方法において、検査用電極の表面に形成されている自然酸化膜を破りつつ、検査用電極とバンプとを接続すると、検査用電極とバンプとの電気的接続がより確実になる。
【００５８】
第２の半導体装置の検査方法によると、良品半導体装置の全ての検査用電極のうちの少なくとも２つの検査用電極に電源電圧又は信号を印加して検査用電極とプローブ端子との電気的接続の良否を検査した後にバーンインを行なうため、バーンインは半導体ウェハとコンタクタとのアライメントが正確に行なわれた状態で行なわれるので、バーンイン工程を確実に行なうことができる。
【００５９】
第３の半導体装置の検査方法によると、特性検査工程において行なった半導体装置の電気特性の良否の検査結果と、バーンイン前に行なう検査用電極とプローブ端子との電気的接続の良否の検査結果とを比較して検査用電極とプローブ端子との電気的接続の良否を検査した後にバーンインを行なうため、バーンインは検査用電極とプローブ端子との電気的接続が確実な状態で行なわれるので、バーンイン工程を確実に行なうことができる。
【００６０】
第１の半導体装置の検査装置によると、検査用電極の表面部に形成されている自然酸化膜を破ったり波打たせた状態で、半導体装置の検査用電極とコンタクタのバンプとを接続できるので、検査用電極とバンプとを電気的に確実に接続することができる。
【００６１】
第１の半導体装置の検査装置が、検査用電極と凹凸形成用バンプとをアライメントするアライメント手段を備えていると、検査用電極の表面部に確実に凹凸を形成することができる。
【００６２】
また、第１の半導体装置の検査装置が、凹凸形成用バンプに付着した付着物を除去する付着物除去手段を備えていると、凹凸形成用バンプに付着した付着物を簡易且つ確実に除去できるので、検査用電極の表面部に確実に凹凸を形成することができる。
【００６３】
第２の半導体装置の検査装置によると、検査用電極とプローブ端子との電気的接続の良否を検査し、該検査において電気的接続が良好であると判断された場合にのみバーンインを行なうことができるので、バーンインを半導体ウェハとコンタクタとのアライメントが正確に行なわれた状態で行なうことができる。
【００６４】
第３の半導体装置の検査装置によると、バーンインを行なう前に、検査用電極とプローブ端子との最終的な電気的接続の良否の検査を行ない、該検査の結果が良好であると判断される場合にのみバーンインを行なうことができるので、バーンインを検査用電極とプローブ端子との電気的接続が確実に行なわれている状態で行なうことができる。
【図面の簡単な説明】
【図１】本発明の一実施形態に係る半導体装置の検査装置の全体構成を示す図である。
【図２】前記一実施形態に係る半導体装置の検査装置を構成する接続検査装置の構成及び該接続検査装置とプローブカード搭載部との関係を示すブロック図である。
【図３】（ａ）は、本発明の一実施形態に係る半導体装置の検査方法における凹凸形成工程を説明する断面図であり、（ｂ）は前記一実施形態に係る半導体装置の検査方法における電極接続工程を説明する断面図である。
【図４】（ａ）は前記一実施形態に係る半導体装置の検査方法における凹凸形成工程の第１の方法を示す断面図であり、（ｂ）は前記一実施形態に係る半導体装置の検査方法における凹凸形成工程の第２の方法を示す断面図である。
【符号の説明】
１トレー載置部
２凹凸形成部
３プローブカード載置部
４接続検査装置
４ａ特性検査手段
４ｂ接続検査手段
５ＸＹＺ可動ステージ
６Ｏリング
７ウェハトレー
８半導体ウェハ
９、９Ａ、９Ｂ凹凸形成用カード
１０検査用電極
１１Ａ、１１Ｂ凹凸形成部
１２バンプ
１３プローブカード[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an inspection method and an inspection apparatus for a semiconductor device, and more particularly to an inspection method and an inspection apparatus for a semiconductor device in which a plurality of semiconductor integrated circuit devices formed on a semiconductor wafer are collectively burned in.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor device is supplied after a semiconductor integrated circuit element and a lead frame are electrically connected by a bonding wire, and then the semiconductor integrated circuit element and a lead frame lead are sealed with resin or ceramics. Mounted on a printed circuit board.
[0003]
However, due to the demand for downsizing and cost reduction of electronic devices, a method of mounting a semiconductor device on a circuit board in a bare chip state cut out from a semiconductor wafer has been developed. It is desired to supply. In order to assure the quality of the bare chip, it is preferable to perform burn-in on a plurality of semiconductor devices formed on one semiconductor wafer in terms of cost reduction.
[0004]
For this reason, a plurality of semiconductor devices formed on a semiconductor wafer are collectively collected in a wafer state using a contactor having a bump connected to each inspection electrode of the plurality of semiconductor devices formed on the semiconductor wafer. An inspection method for performing burn-in has been proposed.
[0005]
By the way, in order to collectively perform a burn-in process in a wafer state on a plurality of semiconductor devices formed on a semiconductor wafer, an electrical property quality determination process performed on each semiconductor device before the burn-in process is also performed. It is necessary to carry out all at once in the wafer state. For this reason, in the electrical property pass / fail judgment step, a probe card having bumps at positions corresponding to the inspection electrodes of a plurality of semiconductor devices formed on the semiconductor wafer and having a size similar to that of the semiconductor wafer is provided. After aligning the probe card bumps with the inspection electrodes of the semiconductor device, the probe card is pressed against the semiconductor wafer to bring the probe card bumps into contact with the inspection electrodes of the semiconductor device. A power supply voltage or signal is applied to the semiconductor device to inspect the electrical characteristics of the semiconductor device.
[0006]
[Problems to be solved by the invention]
By the way, since the inspection electrode of the semiconductor device is usually formed of an easily oxidized metal such as aluminum, the surface of the inspection electrode is covered with a surface oxide film such as alumina. For this reason, in order to obtain a good electrical connection between the bump of the probe card and the inspection electrode of the semiconductor device, it is necessary to press the probe card against the semiconductor wafer and break the surface oxide film by the pressing force. .
[0007]
However, as the number of semiconductor devices formed on the semiconductor wafer increases, the number of bumps formed on the probe card increases, and the pressing force applied to each bump inevitably decreases. For this reason, the surface oxide film cannot be reliably broken by the bumps, the contact resistance between the bumps and the inspection electrode varies, and the electrical property quality inspection performed before the burn-in process is accurately performed. There is a first problem of not.
[0008]
In addition, when a burn-in is performed collectively in a wafer state by applying a power supply voltage or a signal to each inspection electrode of a plurality of semiconductor devices formed on the semiconductor wafer via bumps of a contactor, contact with the semiconductor wafer is made. Are not accurately aligned with each other, or foreign matter is interposed between each inspection electrode of a plurality of semiconductor devices and each bump of the contactor, the electrical connection between the inspection electrode and the bump is ensured. There is also a second problem that burn-in is not performed accurately because it is not performed.
[0009]
In view of the foregoing, it is a first object of the present invention to accurately perform an electrical property inspection performed before the burn-in process, and to electrically connect the inspection electrode and the bump in the burn-in process. A second object is to ensure that burn-in is performed accurately.
[0010]
[Means for Solving the Problems]
A first semiconductor device inspection method according to the present invention achieves the first object, Using the card for forming irregularities, Concavity and convexity forming step for forming concavities and convexities on the surface portions of the inspection electrodes of the plurality of semiconductor devices formed on the semiconductor wafer, a semiconductor wafer, and a contactor having bumps at portions corresponding to the inspection electrodes of the plurality of semiconductor devices, A plurality of semiconductors by applying a power supply voltage or a signal to the inspection electrode via the bump, and an electrode connection step for electrically connecting the inspection electrode having a concavo-convex formed on the surface portion and the bump. And a characteristic inspection step for inspecting the quality of the electrical characteristics of the apparatus.
[0011]
According to the first method for inspecting a semiconductor device, after forming irregularities on the surface portion of the inspection electrode of the semiconductor device, the inspection electrode of the semiconductor device and the bump of the contactor are electrically connected, The bump contacts the surface of the inspection electrode in a state where the natural oxide film formed on the surface portion is torn or undulated. Therefore, the inspection electrode and the bump are electrically connected reliably.
[0012]
In the first method for inspecting a semiconductor device, the unevenness forming step includes a step of forming a break in the natural oxide film formed on the surface of the inspection electrode, and the electrode connecting step is formed in the unevenness forming step. It is preferable to include a step of electrically connecting the inspection electrode and the bump before a new natural oxide film is formed at the break of the natural oxide film.
[0013]
In the first method for inspecting a semiconductor device, the electrode connecting step preferably includes a step of electrically connecting the inspection electrode and the bump while breaking the natural oxide film formed on the surface of the inspection electrode. .
[0014]
The second method for inspecting a semiconductor device according to the present invention achieves the second object, and applies a power supply voltage or signal to the inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer. A characteristic inspection process for inspecting the quality of the electrical characteristics of a plurality of semiconductor devices by applying, a semiconductor wafer, and a contactor having a probe terminal at a position corresponding to the inspection electrodes of the plurality of semiconductor devices, for inspection At least two inspection electrodes among all the inspection electrodes of the non-defective semiconductor device recognized as having good electrical characteristics in the electrode connection step for connecting the electrode and the probe terminal and in the characteristic inspection step, the semiconductor wafer Connection inspection process for inspecting the electrical connection between the inspection electrode and the probe terminal by applying a power supply voltage or signal via the probe terminal of the contactor in contact with the contact terminal, and the connection inspection And a burn-in process for performing burn-in by applying a power supply voltage or a signal to the inspection electrode via the probe terminal of the contactor in contact with the semiconductor wafer when it is determined that the inspection result is good. .
[0015]
According to the second method for inspecting a semiconductor device, a power supply voltage or a signal is supplied to at least two inspection electrodes of all the inspection electrodes of a non-defective semiconductor device recognized as having good electrical characteristics via a probe terminal. Is applied to inspect the electrical connection between the inspection electrode and the probe terminal, and burn-in is performed when it is determined that the result of the inspection is good. Is carried out in a state where is correctly performed.
[0016]
A third method for inspecting a semiconductor device according to the present invention achieves the second object, and applies a power supply voltage or a signal to inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer. A characteristic inspection step for inspecting the quality of electrical characteristics of a plurality of semiconductor devices by applying, a data storage step for storing the quality results of the electrical characteristics of the semiconductor devices obtained in the characteristic inspection step, and a semiconductor wafer And an electrode connection step for connecting the inspection electrode and the probe terminal by contacting a contactor having a probe terminal at a position corresponding to the inspection electrode of the plurality of semiconductor devices, and an inspection electrode of the plurality of semiconductor devices. The power supply voltage or signal is applied via the probe terminal of the contactor that is in contact with the semiconductor wafer to inspect the electrical connection between the inspection electrode and the probe terminal. The connection inspection process for inspecting the quality of the electrical connection between the inspection electrode and the probe terminal by comparing the quality result obtained and the quality data stored in the data storage process, and the inspection in the connection inspection process And a burn-in process for performing burn-in by applying a power supply voltage or a signal to the inspection electrode via the probe terminal of the contactor in contact with the semiconductor wafer when it is determined that the result is good.
[0017]
According to the third method for inspecting a semiconductor device, the inspection result of the electrical characteristics of the semiconductor device performed in the characteristic inspection process and the inspection result of the electrical connection between the inspection electrode and the probe terminal performed in the connection inspection process. The burn-in process is performed when the quality of the electrical connection between the inspection electrode and the probe terminal is checked and the result of the inspection is determined to be good. The electrical connection with the terminal is performed in a reliable state.
[0018]
The inspection apparatus for a first semiconductor device according to the present invention achieves the first object, and inspects a portion corresponding to the inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer. Have bumps for forming irregularities on the surface of the electrode for forming irregularities Consists of cards for forming irregularities For inspecting a plurality of semiconductor devices, a first approaching means for bringing the semiconductor wafer and the concavo-convex forming means close to each other so that the concavo-convex forming means is in contact with the inspection electrode and the concavo-convex forming bump. Second contact means for bringing the semiconductor wafer and the contactor closer to each other so that the bumps of the contactor having bumps in contact with the electrodes correspond to the electrodes, and supply voltage or signal to the bumps in contact with the inspection electrodes. And a characteristic inspection means for inspecting the quality of the electrical characteristics of the plurality of semiconductor devices. In this case, the first approach means and the second approach means may be the same means or different means.
[0019]
According to the inspection apparatus of the first semiconductor device, the unevenness is formed on the surface portion of the inspection electrode of the semiconductor device by the unevenness forming means, and the natural oxide film formed on the surface portion of the inspection electrode is broken or corrugated. Since the inspection electrode of the semiconductor device and the bump of the contactor can be connected in the state of being covered, the inspection electrode and the bump can be electrically connected reliably.
[0020]
The inspection device for the first semiconductor device preferably further includes an alignment means for aligning the inspection electrode and the bump for forming the unevenness.
[0021]
Moreover, it is preferable that the inspection apparatus for the first semiconductor device further includes a deposit removing means for removing deposits adhering to the bumps for forming irregularities.
[0022]
A second semiconductor device inspection apparatus according to the present invention achieves the second object, and applies a power supply voltage or a signal to inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer. A characteristic inspection means for inspecting the quality of electrical characteristics of a plurality of semiconductor devices by applying, a semiconductor wafer, and a contactor having a probe terminal at a position corresponding to the inspection electrodes of the plurality of semiconductor devices, for inspection An electrode connecting means for connecting the electrode and the probe terminal, and at least two inspection electrodes of all the inspection electrodes of the non-defective semiconductor device recognized as having good electrical characteristics by the characteristic inspection means, on the semiconductor wafer Connection inspection means for inspecting the electrical connection between the inspection electrode and the probe terminal by applying a power supply voltage or a signal through the probe terminal of the contactor in contact with the contact terminal That.
[0023]
According to the inspection apparatus of the second semiconductor device, the connection inspection means passes the probe terminal to at least two inspection electrodes of all the inspection electrodes of the non-defective semiconductor device recognized as having good electrical characteristics. If the result of the inspection is judged to be good, that is, the alignment between the semiconductor wafer and the contactor is good. Only in some cases can burn-in be performed.
[0024]
A third semiconductor device inspection apparatus according to the present invention achieves the second object, and applies a power supply voltage or a signal to inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer. A characteristic inspection means for inspecting the electrical characteristics of the plurality of semiconductor devices by applying them and storing the obtained electrical characteristics results as quality data; a semiconductor wafer; and an inspection electrode for the plurality of semiconductor devices A contactor having a probe terminal at a position corresponding to the electrode contact means for connecting the inspection electrode and the probe terminal, and the contactor of the contactor in contact with the semiconductor wafer to the inspection electrode of the plurality of semiconductor devices A power supply voltage or signal is applied through the probe terminal to check the quality of the electrical connection between the inspection electrode and the probe terminal, and the quality result obtained by the inspection is stored in the characteristic inspection means. By comparing the quality data that, and a connection test means for checking the quality of the electrical connection between the testing electrodes and the probe terminals.
[0025]
According to the third semiconductor device inspection apparatus, the connection inspection means compares the result of the inspection of the electrical connection between the inspection electrode and the probe terminal with the quality data stored in the characteristic inspection means. In order to inspect the quality of the final electrical connection, burn-in can be performed in a state where the inspection electrode and the probe terminal are electrically connected reliably.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows the overall configuration of a semiconductor device inspection apparatus according to an embodiment of the present invention. As shown in FIG. 1, a semiconductor device inspection apparatus includes a tray mounting portion 1 on which a wafer tray in which a semiconductor wafer is stored is placed, and a surface of an inspection electrode of the semiconductor device formed on the semiconductor wafer. A concavo-convex forming portion 2 for forming a probe card, and a probe card mounting portion 3 for mounting a probe card on a semiconductor wafer and connecting inspection electrodes of the semiconductor device formed on the semiconductor wafer and bumps of the probe card; The inspection device 4 for inspecting the electrical connection between the inspection electrode of the semiconductor device and the bump of the probe card and the wafer tray storing the semiconductor wafer are moved from the tray mounting portion 1 to the unevenness forming portion 2. After that, an XYZ movable stage 5 that is moved from the concave / convex forming portion 2 to the probe card mounting portion 3 or moved from the probe card mounting portion 3 to the tray mounting portion 1 is moved. Eteiru. The tray mounting unit 1 is provided with a loader / unloader that moves the wafer tray between the tray mounting unit 1 and the XYZ movable stage 5.
[0027]
FIG. 2 shows the configuration of the connection inspection device 4 and the relationship between the connection inspection device 4 and the probe card mounting portion 3. As shown in FIG. 2, the connection inspection device 4 sends electric signals to the bumps of the probe card. Characteristic inspection means 4a for inspecting the electrical characteristics of the semiconductor device on the semiconductor wafer by applying, and connection inspection means 4b for inspecting the quality of the electrical connection between the inspection electrode of the semiconductor device and the bump of the probe card ing.
[0028]
Hereinafter, a semiconductor device inspection method and inspection apparatus according to an embodiment of the present invention will be described in detail.
[0029]
(Unevenness forming process)
First, with reference to FIG. 3A, a description will be given of a concavo-convex forming step for forming concavo-convex on the surface portions of the inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer, which is performed in the concavo-convex forming portion 2.
[0030]
After the semiconductor wafer 8 was stored on the wafer tray 7 having the O-ring 6 around the semiconductor wafer mounting portion, the wafer tray 7 storing the semiconductor wafer 8 was moved from the tray mounting portion 1 onto the XYZ movable stage 5. Thereafter, the XYZ movable stage 5 is driven to move the wafer tray 7 to the unevenness forming unit 2.
[0031]
Next, after performing alignment between the semiconductor wafer 8 and the concave / convex forming card 9 as the concave / convex forming means, the XYZ movable stage 5 is driven to press the semiconductor wafer 8 against the concave / convex forming card 9, Unevenness is formed on the surface portion of the inspection electrode 10 of the semiconductor device. In this case, the XYZ movable stage 5 constitutes a first approach means for bringing the semiconductor wafer and the unevenness forming means closer to each other.
[0032]
FIG. 4A shows a first method of forming irregularities on the surface portion of the inspection electrode 10, which includes the inspection electrode 10 of the semiconductor device formed on the semiconductor wafer 8. For example, the concave / convex forming card 9A having the concave / convex forming bumps 11A made of Ni, for example, made of Ni is used at the corresponding position. In the first method, after the inspection electrode 10 of the semiconductor device and the bumps 11A for forming the unevenness of the card 9A for forming the unevenness are brought into contact, the card 9A for forming the unevenness is reciprocated in a plane parallel to the semiconductor wafer 8 or By rotating it, irregularities are formed on the surface portion of the inspection electrode 10 of the semiconductor device.
[0033]
FIG. 4B shows a second method of forming irregularities on the surface portion of the inspection electrode 10, and this second method is performed on the surface at a position corresponding to the inspection electrode 10 of the semiconductor device. This is performed by using a concave / convex forming card 9B having a concave / convex concave bump 11B made of, for example, Ni. The second method is to press the unevenness forming bump 11B of the unevenness forming card 9B against the inspection electrode 10 of the semiconductor device so that the unevenness portion on the surface of the unevenness forming bump 11B is brought to the surface of the inspection electrode 10. By transferring, irregularities are formed on the surface portion of the inspection electrode 10 of the semiconductor device. As for the concavo-convex portion on the surface of the concavo-convex forming bump 11B, the hemispherical concavo-convex forming bump 11B is pressed against a ceramic plate having a concavo-convex portion of 0.1 μm to several μm on the surface, or the hemispherical concavo-convex forming bump 11B. It can be formed by forming a plating layer made of particles having a particle size of about 1 to 10 μm on the surface by electroplating.
[0034]
When the first method or the second method is performed, irregularities are formed on the surface portion of the inspection electrode 10, so that a tear is formed in the natural oxide film formed on the surface portion of the inspection electrode 10. Or the natural oxide film becomes wavy.
[0035]
If the contact between the inspection electrode 10 of the semiconductor device and the bumps 11A and 11B is repeated, foreign matter such as aluminum adheres to the surface of the bumps 11A and 11B. Therefore, although not shown, an air blow means, a brush means such as a wire brush, or a deposit removing means such as a ceramic plate having unevenness on the surface is provided, and air is supplied from the air blow means to the surfaces of the bumps 11A and 11B for forming the unevenness. It is preferable to remove the deposits attached to the surfaces of the bumps 11A and 11B by spraying or by bringing the surfaces of the bumps 11A and 11B for unevenness into sliding contact with the brush means or the ceramic plate.
[0036]
(Electrode connection process)
Next, referring to FIG. 3B, the probe card 13 as a contactor having bumps 12 at the portion corresponding to the semiconductor wafer 8 and the inspection electrode 10 of the semiconductor device, which is performed in the probe card mounting unit 3. An electrode connecting step for electrically connecting the inspection electrode 10 having the irregularities formed on the surface portion and the bump 12 by bringing them into contact with each other will be described.
[0037]
After the wafer tray 7 containing the semiconductor wafer 8 is moved from the concave / convex forming portion 2 onto the XYZ movable stage 5, the XYZ movable stage 5 is driven to move the wafer tray 7 to the probe card mounting portion 3.
[0038]
Next, after the semiconductor wafer 8 and the probe card 13 are aligned, the XYZ movable stage 5 is driven to press the probe card 13 against the semiconductor wafer 8. In this case, the XYZ movable stage 5 constitutes a second approach means for bringing the semiconductor wafer and the contactor closer to each other. As described above, since the O-ring 6 is provided around the semiconductor wafer mounting portion in the wafer tray 7, the probe card 13 is attached to the semiconductor wafer by reducing the pressure of the semiconductor mounting portion inside the O-ring 6. 8 is pressed with an appropriate pressing force due to atmospheric pressure, the inspection electrodes 10 of the semiconductor device formed on the semiconductor wafer 8 and the bumps 12 of the probe card 13 are surely in contact with each other.
[0039]
Further, since the unevenness is formed on the surface portion of the inspection electrode 10 in the unevenness forming step, the natural oxide film formed on the surface portion of the inspection electrode 10 has a tear or is formed on the natural oxide film. Is wavy. For this reason, when the inspection electrode 10 and the bump 12 are brought into contact with each other in the electrode connecting step, the natural oxide film breaks on the surface of the inspection electrode 10 due to the pressing force of the bump 12, or the natural oxide film is waved. Since the shape changes to a break, the electrical resistance between the inspection electrode 10 and the bump 12 is reduced.
[0040]
In the unevenness forming step, if a break is formed in the natural oxide film on the surface of the inspection electrode 10, the electrode connecting step is performed before a new natural oxide film is formed at the break. The inspection electrode 10 and the bump 12 are preferably electrically connected.
[0041]
Moreover, it is preferable to perform the uneven | corrugated formation process and an electrode connection process, for example in a nitrogen gas atmosphere, and to perform in the environment where a new natural oxide film is not formed.
[0042]
(Characteristic inspection process)
Next, the power supply voltage or signal is applied from the outside of the probe card 13 to the inspection electrode 10 via the bump 12 of the probe card 13 by the characteristic inspection means 4a of the connection inspection device 4 to determine whether the electrical characteristics of the semiconductor device are good or bad. A characteristic inspection process for inspecting As described above, a tear is formed in the natural oxide film on the surface of the inspection electrode 10, and the electrical resistance between the inspection electrode 10 and the bump 12 is greatly reduced, so that it is formed on the semiconductor wafer 8. The electrical characteristics of all the semiconductor devices can be inspected satisfactorily and reliably.
[0043]
Data of the result of inspecting the quality of the electrical characteristics in this characteristic inspection process, that is, a non-defective semiconductor device that satisfies the planned characteristics of the electrical characteristics and a defective product that does not meet the planned characteristics of the electrical characteristics The pass / fail data as a result of the determination with the semiconductor device is transferred to the connection inspection means 4b and stored in the storage means included in the connection inspection means 4b.
[0044]
(Insulation process for defective semiconductor devices)
Next, the semiconductor wafer on which the characteristic inspection process has been completed is moved to the tray mounting unit 1 by the XYZ movable stage 5 while being stored in the wafer tray 7, and an insulating film (not shown) is formed from the tray mounting unit 1. In the insulating film forming apparatus, the defective semiconductor device determined to be defective in the characteristic inspection process is insulated from the semiconductor devices formed on the semiconductor wafer. That is, it is specified that the entire surface of the defective semiconductor device is electrically connected to the whole surface of the defective semiconductor device, the surface of all inspection electrodes of the defective semiconductor device, or the defective portion of the electrical characteristics of the defective semiconductor device. An insulating resin or the like is applied to the surface of the inspection electrode so that no current flows through the defective portion of the defective semiconductor device.
[0045]
By the way, in the next burn-in process, if a power supply voltage or a signal is applied to each inspection electrode of all semiconductor devices from an individual wiring, a considerably large number of wirings are required. It is preferable to apply a power supply voltage or a signal to each inspection electrode 10 via a power supply voltage line or a signal line. However, when a power supply voltage or signal is applied to each inspection electrode 12 via a common power supply voltage line or signal line, the common power supply voltage line or signal passes through a semiconductor device that is electrically short-circuited inside. A large amount of current may flow through the wire. Therefore, in the process of insulating a defective semiconductor device, current is prevented from flowing to a defective portion of the defective semiconductor device.
[0046]
(Connection inspection process)
Next, the semiconductor wafer that has been subjected to the insulating process of the defective semiconductor device is moved again to the tray mounting portion 1 while being accommodated in the wafer tray 7, and then moved to the probe card mounting portion 3 by the XYZ movable stage 5. In the probe card mounting portion 3, the probe card 13 and the semiconductor wafer 8 are aligned again, and then the probe card 13 is pressed against the semiconductor wafer 8.
[0047]
Next, the connection inspection unit 4 b of the connection inspection device 4 applies a power supply voltage or a signal to the inspection electrode 10 of the semiconductor device of the semiconductor wafer 8 via the bump 12 of the probe card 13, and the inspection electrode 10 and the bump The electrical connection with 12 is checked.
[0048]
By the way, for the semiconductor device in which the insulating process of the defective semiconductor device is completed, in the next step, burn-in is performed collectively in the wafer state. In this case, the alignment between the semiconductor wafer 8 and the probe card 13 is correct. The inspection electrode 10 of the non-defective semiconductor device and the bump 12 of the probe card 13 are electrically connected, and the inspection electrode 10 of the defective semiconductor device and the probe card 13 It is desirable to confirm that the bump 12 is not electrically connected.
[0049]
Therefore, the connection inspection unit 4b of the connection inspection device 4 applies a power supply voltage or a signal to the inspection electrode 10 of the semiconductor device via the bumps 12 of the probe card 13, so that the inspection electrode 10 of the semiconductor device and the probe card 13 are applied. The quality of the electrical connection with the bump 12 is inspected. Specifically, the connection inspection unit 4a compares the result of the electrical connection performed in the connection inspection process with the quality data stored in the storage unit after the electrical characteristic inspection process. Therefore, whether or not the alignment of the semiconductor wafer 8 and the probe card 13 is correctly performed, whether the inspection electrode 10 of the non-defective semiconductor device and the bump 12 of the probe card 13 are electrically connected, and Then, at least one of the inspections of whether or not the inspection electrodes 10 of the defective semiconductor device and the bumps 12 of the probe card 13 are electrically connected is performed.
[0050]
In this connection inspection process, the greater the number of semiconductor devices and inspection electrodes 10 to which a power supply voltage or signal is applied, the more accurate the connection inspection between the inspection electrodes 10 of the semiconductor device and the bumps 12 of the probe card 13 is. Although it becomes higher, the time required for connection inspection becomes longer. Therefore, it is preferable to determine the number of semiconductor devices and inspection electrodes 10 to which the power supply voltage or signal is applied in consideration of the accuracy of the connection inspection and the time required for the connection inspection.
[0051]
Accordingly, the power supply voltage is applied to at least two inspection electrodes 10 among all the inspection electrodes 10 of the non-defective semiconductor device which has been recognized as having good electrical characteristics in the characteristic inspection step via the bumps 12 of the probe card 13. Alternatively, when inspecting the electrical connection between the inspection electrode 10 and the bump 12 by applying a signal, the semiconductor wafer 8 and the probe card 13 are inspected for proper alignment. be able to.
[0052]
(Burn-in process)
If the inspection result of the electrical connection between the inspection electrode 10 of the semiconductor device and the bump 12 of the probe card 13 is not satisfactory, the alignment between the semiconductor wafer 8 and the probe card 13 is performed again, while the electrical connection inspection is performed. If the above result is satisfactory, burn-in is performed by applying a power supply voltage or signal to the inspection electrode 10 of the semiconductor device of the semiconductor wafer 8 via the bumps 12 of the probe card 13. The contactor used in the burn-in process is not particularly limited, and a probe card, a probe sheet, and the like shown in Japanese Patent Application Laid-Open Nos. 7-169806 and 8-5666 can be appropriately used.
[0053]
Although all the steps described above can be performed, burn-in can be performed with certainty, but it is natural that some steps may be omitted. For example, if the electrode connection process is performed well even if the unevenness forming process is omitted, the unevenness forming process can be omitted, and if the burn-in process is performed to the extent that the connection inspection process can be omitted. The connection inspection step may be omitted.
[0054]
Moreover, although it is effective to perform the uneven | corrugated formation process with respect to the bump formed in the contactor, the structure of the probe terminal formed in a contactor does not ask | require a connection inspection process.
[0055]
【The invention's effect】
According to the first method for inspecting a semiconductor device, irregularities are formed on the surface portion of the inspection electrode of the semiconductor device, and the natural oxide film formed on the surface portion of the inspection electrode is broken or waved. In this state, since the inspection electrode of the semiconductor device and the bump of the contactor are brought into contact with each other, the inspection electrode and the bump can be electrically connected reliably.
[0056]
In the first method for inspecting a semiconductor device, if the inspection electrode and the bump are electrically connected before the new natural oxide film is formed at the break of the natural oxide film, the electrical connection between the inspection electrode and the bump is established. Is more certain.
[0057]
In the first method for inspecting a semiconductor device, when the inspection electrode and the bump are connected while breaking the natural oxide film formed on the surface of the inspection electrode, the electrical connection between the inspection electrode and the bump is established. Become more certain.
[0058]
According to the second method for inspecting a semiconductor device, a power supply voltage or a signal is applied to at least two inspection electrodes among all the inspection electrodes of the non-defective semiconductor device to establish electrical connection between the inspection electrode and the probe terminal. Since the burn-in is performed after the quality is inspected, the burn-in is performed in a state where the alignment between the semiconductor wafer and the contactor is accurately performed, so that the burn-in process can be performed reliably.
[0059]
According to the third method for inspecting a semiconductor device, the inspection result of the electrical characteristics of the semiconductor device performed in the characteristic inspection process, and the inspection result of the electrical connection between the inspection electrode and the probe terminal performed before burn-in, Since the burn-in is performed after the electrical connection between the inspection electrode and the probe terminal is inspected by comparing the two, the burn-in process is performed with a reliable electrical connection between the inspection electrode and the probe terminal. Can be performed reliably.
[0060]
According to the inspection device of the first semiconductor device, the inspection electrode of the semiconductor device and the bump of the contactor can be connected in a state where the natural oxide film formed on the surface portion of the inspection electrode is broken or waved. The inspection electrodes and the bumps can be electrically connected reliably.
[0061]
When the inspection device of the first semiconductor device includes an alignment unit that aligns the inspection electrode and the bumps for forming the unevenness, the unevenness can be reliably formed on the surface portion of the inspection electrode.
[0062]
In addition, when the inspection device for the first semiconductor device is provided with the deposit removing means for removing deposits attached to the bumps for forming irregularities, the deposits attached to the bumps for forming irregularities can be easily and reliably removed. Therefore, irregularities can be reliably formed on the surface portion of the inspection electrode.
[0063]
According to the inspection apparatus for the second semiconductor device, the electrical connection between the inspection electrode and the probe terminal is inspected, and burn-in is performed only when the electrical connection is determined to be good in the inspection. Therefore, burn-in can be performed in a state where the alignment between the semiconductor wafer and the contactor is accurately performed.
[0064]
According to the third semiconductor device inspection apparatus, the final electrical connection between the inspection electrode and the probe terminal is inspected before and after burn-in, and it is determined that the result of the inspection is good. Since burn-in can be performed only in such a case, burn-in can be performed in a state where the electrical connection between the inspection electrode and the probe terminal is reliably performed.
[Brief description of the drawings]
FIG. 1 is a diagram showing an overall configuration of a semiconductor device inspection apparatus according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of a connection inspection apparatus constituting the semiconductor device inspection apparatus according to the embodiment and a relationship between the connection inspection apparatus and a probe card mounting portion.
FIG. 3A is a cross-sectional view for explaining an unevenness forming step in a semiconductor device inspection method according to an embodiment of the present invention, and FIG. 3B is a semiconductor device inspection method according to the embodiment; It is sectional drawing explaining an electrode connection process.
4A is a cross-sectional view showing a first method of the unevenness forming step in the semiconductor device inspection method according to the embodiment; FIG. 4B is a semiconductor device inspection method according to the embodiment; It is sectional drawing which shows the 2nd method of the uneven | corrugated formation process in FIG.
[Explanation of symbols]
1 Tray placement section
2 Concavity and convexity forming part
3 Probe card placement section
4. Connection inspection device
4a Characteristic inspection means
4b Connection inspection means
5 XYZ movable stage
6 O-ring
7 Wafer tray
8 Semiconductor wafer
9, 9A, 9B Concavity and convexity forming card
10 Inspection electrode
11A, 11B Concavity and convexity forming part
12 Bump
13 Probe card

Claims

Using the unevenness forming card, an unevenness forming step for forming unevenness on the surface portions of the inspection electrodes of a plurality of semiconductor devices formed on the semiconductor wafer;
The semiconductor wafer and a contactor having a bump at a portion corresponding to the inspection electrode of the plurality of semiconductor devices are brought into contact with each other to electrically connect the inspection electrode and the bump formed on the surface portion with the bump. An electrode connecting step,
A semiconductor device inspection method comprising: a characteristic inspection step of inspecting the electrical characteristics of the plurality of semiconductor devices by applying a power supply voltage or a signal to the inspection electrodes via the bumps. .

The irregularity forming step includes a step of forming a break in a natural oxide film formed on the surface of the inspection electrode,
The electrode connecting step includes a step of electrically connecting the inspection electrode and the bump before a new natural oxide film is formed at a break of the natural oxide film formed in the unevenness forming step. The method for inspecting a semiconductor device according to claim 1, wherein:

The electrode connection step includes a step of electrically connecting the inspection electrode and the bump while breaking a natural oxide film formed on a surface of the inspection electrode. The inspection method of the semiconductor device as described.

A characteristic inspection step for inspecting the electrical characteristics of the plurality of semiconductor devices by applying a power supply voltage or a signal to inspection electrodes of the plurality of semiconductor devices formed on the semiconductor wafer;
An electrode connection step of contacting the semiconductor wafer and a contactor having a probe terminal at a position corresponding to the inspection electrode of the plurality of semiconductor devices to connect the inspection electrode and the probe terminal;
Probe terminals of the contactor in contact with the semiconductor wafer at least two inspection electrodes of all the inspection electrodes of a non-defective semiconductor device recognized as having good electrical characteristics in the characteristic inspection step A connection inspection step of inspecting the electrical connection between the inspection electrode and the probe terminal by applying a power supply voltage or a signal through
Burn-in in which a burn-in is performed by applying a power supply voltage or a signal to the inspection electrode via the probe terminal of the contactor in contact with the semiconductor wafer when it is determined that the inspection result in the connection inspection step is good A method for inspecting a semiconductor device.

A characteristic inspection step for inspecting the electrical characteristics of the plurality of semiconductor devices by applying a power supply voltage or a signal to inspection electrodes of the plurality of semiconductor devices formed on the semiconductor wafer;
A data storage step of storing the quality results of the electrical characteristics of the semiconductor device obtained in the characteristic inspection step as quality data,
An electrode connection step of contacting the semiconductor wafer and a contactor having a probe terminal at a position corresponding to the inspection electrode of the plurality of semiconductor devices to connect the inspection electrode and the probe terminal;
A power supply voltage or a signal is applied to the inspection electrodes of the plurality of semiconductor devices via the probe terminals of the contactors that are in contact with the semiconductor wafer, and electrical connection between the inspection electrodes and the probe terminals is performed. The quality of the electrical connection between the inspection electrode and the probe terminal is inspected by inspecting the quality and comparing the quality result obtained by the inspection with the quality data stored in the data storage step. Connection inspection process;
Burn-in in which a burn-in is performed by applying a power supply voltage or a signal to the inspection electrode via the probe terminal of the contactor in contact with the semiconductor wafer when it is determined that the inspection result in the connection inspection step is good A method for inspecting a semiconductor device.

Concavity and convexity forming means comprising a concave / convex forming card having concave / convex forming bumps for forming concave / convex portions on the surface portion of the inspection electrode at portions corresponding to the inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer. When,
First approach means for bringing the semiconductor wafer and the concavo-convex forming means closer to each other so that the inspection electrode and the concavo-convex forming bumps are in contact with each other;
A second approach means for bringing the semiconductor wafer and the contactor closer to each other so that the inspection electrode and the bump of the contactor having a bump at a portion corresponding to the inspection electrode of the plurality of semiconductor devices are in contact with each other; ,
A semiconductor device comprising: characteristic inspection means for inspecting the electrical characteristics of the plurality of semiconductor devices by applying a power supply voltage or a signal to the bumps in contact with the inspection electrodes. Inspection device.

The semiconductor device inspection apparatus according to claim 6, further comprising an alignment unit that aligns the inspection electrode and the bumps for forming the unevenness.

The semiconductor device inspection apparatus according to claim 6, wherein the unevenness forming unit includes an attached matter removing unit that removes the attached matter attached to the bumps for forming the unevenness.

Characteristic inspection means for inspecting the electrical characteristics of the plurality of semiconductor devices by applying a power supply voltage or signal to inspection electrodes of the plurality of semiconductor devices formed on the semiconductor wafer;
An electrode connecting means for contacting the semiconductor wafer and a contactor having a probe terminal at a position corresponding to the inspection electrode of the plurality of semiconductor devices to connect the inspection electrode and the probe terminal;
Probe terminals of the contactor in contact with the semiconductor wafer at least two inspection electrodes of all the inspection electrodes of a non-defective semiconductor device recognized as having good electrical characteristics by the characteristic inspection means An inspection apparatus for a semiconductor device, comprising: a connection inspection means for inspecting the quality of the electrical connection between the inspection electrode and the probe terminal by applying a power supply voltage or a signal through the terminal.

A power supply voltage or a signal is applied to inspection electrodes of a plurality of semiconductor devices formed on a semiconductor wafer to inspect the electrical characteristics of the plurality of semiconductor devices, and the result of the electrical characteristics obtained is acceptable. Characteristic inspection means to be stored as data,
An electrode connecting means for contacting the semiconductor wafer and a contactor having a probe terminal at a position corresponding to the inspection electrode of the plurality of semiconductor devices to connect the inspection electrode and the probe terminal;
A power supply voltage or a signal is applied to the inspection electrodes of the plurality of semiconductor devices via a probe terminal of the contactor in contact with the semiconductor wafer, and electrical connection between the inspection electrode and the probe terminal is performed. The quality of the electrical connection between the inspection electrode and the probe terminal is inspected by comparing the quality result obtained by the inspection with the quality data stored in the characteristic inspection means. An inspection apparatus for a semiconductor device, comprising: