JP3816159B2 - 一定入力インピーダンスを有する受信器回路 - Google Patents

一定入力インピーダンスを有する受信器回路 Download PDF

Info

Publication number
JP3816159B2
JP3816159B2 JP23434896A JP23434896A JP3816159B2 JP 3816159 B2 JP3816159 B2 JP 3816159B2 JP 23434896 A JP23434896 A JP 23434896A JP 23434896 A JP23434896 A JP 23434896A JP 3816159 B2 JP3816159 B2 JP 3816159B2
Authority
JP
Japan
Prior art keywords
transistor
negative feedback
branch
receiver circuit
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23434896A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09130227A5 (enExample
JPH09130227A (ja
Inventor
ラオ マルティーン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Publication of JPH09130227A publication Critical patent/JPH09130227A/ja
Publication of JPH09130227A5 publication Critical patent/JPH09130227A5/ja
Application granted granted Critical
Publication of JP3816159B2 publication Critical patent/JP3816159B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0292Arrangements specific to the receiver end
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0278Arrangements for impedance matching

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)
  • Networks Using Active Elements (AREA)
JP23434896A 1995-09-08 1996-09-04 一定入力インピーダンスを有する受信器回路 Expired - Fee Related JP3816159B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19533274A DE19533274A1 (de) 1995-09-08 1995-09-08 Empfängerschaltung mit konstanten Eingangswiderstand
DE19533274:1 1995-09-08

Publications (3)

Publication Number Publication Date
JPH09130227A JPH09130227A (ja) 1997-05-16
JPH09130227A5 JPH09130227A5 (enExample) 2004-09-02
JP3816159B2 true JP3816159B2 (ja) 2006-08-30

Family

ID=7771647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23434896A Expired - Fee Related JP3816159B2 (ja) 1995-09-08 1996-09-04 一定入力インピーダンスを有する受信器回路

Country Status (4)

Country Link
US (1) US5821768A (enExample)
EP (1) EP0763916B1 (enExample)
JP (1) JP3816159B2 (enExample)
DE (2) DE19533274A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE502835C2 (sv) * 1994-11-23 1996-01-29 Ellemtel Utvecklings Ab Termineringsnätsrelaterat kopplingsarrangemang
US5955894A (en) * 1997-06-25 1999-09-21 Sun Microsystems, Inc. Method for controlling the impedance of a driver circuit
US6181157B1 (en) * 1997-11-10 2001-01-30 Lsi Logic Corporation Resistor mirror
US6181195B1 (en) * 1998-12-23 2001-01-30 Xerox Corporation Impedance transport circuit
US6157206A (en) * 1998-12-31 2000-12-05 Intel Corporation On-chip termination
US6380787B1 (en) * 1999-08-31 2002-04-30 Micron Technology, Inc. Integrated circuit and method for minimizing clock skews
US6737926B2 (en) * 2001-08-30 2004-05-18 Micron Technology, Inc. Method and apparatus for providing clock signals at different locations with minimal clock skew
US7102200B2 (en) * 2001-09-04 2006-09-05 Intel Corporation On-die termination resistor with analog compensation
JP4026593B2 (ja) 2003-12-25 2007-12-26 セイコーエプソン株式会社 受信装置
US7141936B2 (en) * 2004-11-10 2006-11-28 Xerox Corporation Driving circuit for light emitting diode
US9438188B2 (en) * 2014-09-15 2016-09-06 Qualcomm Incorporated Common-gate amplifier for high-speed DC-coupling communications

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573489A (en) * 1969-05-29 1971-04-06 Gen Electric High speed current-mode logic gate
US3972003A (en) * 1974-08-09 1976-07-27 Bell Telephone Laboratories, Incorporated High speed current detection amplifier circuit
DE3116262A1 (de) * 1981-04-24 1982-11-11 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt "schaltungsanordnung zur erzeugung von steuergroessen aus dem schleifenstrom"
DE3345496C2 (de) * 1983-12-16 1986-01-30 Telefunken electronic GmbH, 7100 Heilbronn Selektive Verstärkerstufe
US4941153A (en) * 1987-08-25 1990-07-10 Hughes Aircraft Company High-speed digital data communication system
JPH0379121A (ja) * 1989-08-23 1991-04-04 Hitachi Ltd 半導体集積回路装置
KR100225594B1 (ko) * 1991-03-29 1999-10-15 가나이 쯔도무 반도체 집적회로장치에서 실행되는 전류구동신호 인터페이스
JPH05235649A (ja) * 1992-02-24 1993-09-10 Nec Eng Ltd 増幅回路

Also Published As

Publication number Publication date
EP0763916A3 (de) 2000-09-20
US5821768A (en) 1998-10-13
EP0763916A2 (de) 1997-03-19
DE19533274A1 (de) 1997-03-13
DE59610070D1 (de) 2003-02-27
EP0763916B1 (de) 2003-01-22
JPH09130227A (ja) 1997-05-16

Similar Documents

Publication Publication Date Title
US4766394A (en) Operational amplifier circuit having wide operating range
JP4766769B2 (ja) 半導体集積回路
US5939922A (en) Input circuit device with low power consumption
JP2549540B2 (ja) レベルシフト回路
US5235222A (en) Output circuit and interface system comprising the same
US4833350A (en) Bipolar-CMOS digital interface circuit
US5559448A (en) CMOS terminating resistor circuit
KR940000925B1 (ko) Cmos 전압기준과 버퍼회로
JP2010178346A (ja) プロセス変動に対してスルーレートを補償するためのプリドライバを有する出力バッファ
EP0037406B1 (en) Cmos operational amplifier with reduced power dissipation
JP3816159B2 (ja) 一定入力インピーダンスを有する受信器回路
JPH02260915A (ja) トランジスタ回路
US5418475A (en) Input/output circuit having the input buffer circuit being connected in parallel with two transistors with the same polarity
US5001362A (en) BiCMOS reference network
EP0240114B1 (en) A comparator for comparing differential input signals and method therefor
US5221910A (en) Single-pin amplifier in integrated circuit form
US5864254A (en) Differential amplifier circuit with enlarged range for source voltage and semiconductor device using same
US4602207A (en) Temperature and power supply stable current source
US7053699B2 (en) Current output stages
US6529036B1 (en) Low noise, reduced swing differential output buffer design
US4100478A (en) Monolithic regulator for CML devices
US4996499A (en) Amplitude stabilized oscillator amplifier
US5164614A (en) Low power bias voltage generating circuit comprising a current mirror
US6593769B1 (en) Differential, reduced swing buffer design
JPH04260225A (ja) 半導体集積回路

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051222

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060117

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060413

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060509

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060607

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100616

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100616

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110616

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110616

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120616

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120616

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130616

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees