JP3814548B2 - Information processing control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a processor (information processing control device) that performs operations between data stored in a register or memory while decoding a program, and in particular, assists in reducing the code size of the program and reducing the area of the instruction memory. It is related to the processor which performs.
[0002]
[Prior art]
FIG. 8 shows a configuration of a processor as a general information processing control apparatus. The processor includes an instruction decoding device for decoding an instruction, indicated by 370, an instruction supply control device for controlling an instruction supply, indicated by 372, an instruction memory for storing instructions, indicated by 374, and indicated by 377. The information processing control device includes a register group that holds data to be stored and a plurality of arithmetic units indicated by 379.
[0003]
In the processor, the instruction decoding device 370 decodes the instruction 375, and based on the decoded contents, the instruction decoding device 370 controls the instruction supply control device 372 using the control line 371, and the register group 377 uses the control line 376. In addition, the arithmetic unit 379 is controlled using the control line 378.
[0004]
The arithmetic unit 379 takes in and operates the data of the register group 377 from the signal line 380, and the register group 377 takes in the output data from the arithmetic unit 379 through the signal line 381.
The command supply controller 372 controls the command memory 374 using the control line 373. The instruction decoding device 370 decodes the instruction 375 output from the instruction memory 374.
[0005]
In general, a processor built in an image processing LSI or a sound processing LSI is configured to include an instruction that can execute a plurality of instructions simultaneously and an instruction that executes a single instruction execution instruction that cannot be executed simultaneously in order to improve calculation performance. There are many things.
[0006]
FIG. 9 shows a schematic diagram of the instruction bit field conventionally used. Reference numeral 101 denotes an instruction bit field for executing a plurality of instructions simultaneously, and reference numeral 102 denotes an instruction bit field for executing one instruction execution instruction that is not executed simultaneously. In each instruction bit field, 103 is a bit indicating whether the instruction bit field includes a plurality of instructions that are executed simultaneously or one instruction execution instruction that is not executed simultaneously. Reference numerals 104 and 105 denote a plurality of instructions that can be executed simultaneously in the instruction bit field 101. Reference numeral 106 denotes an instruction execution instruction that is not simultaneously executed in the instruction bit field 102.
[0007]
Further, in order to realize these instructions, the conventional processor includes an instruction supply control device having a configuration as shown in FIG. 11 as the instruction supply control device 372 shown in FIG. FIG. 11 is a block diagram illustrating an example of a detailed configuration of the instruction supply control device 372. Reference numeral 150 denotes a latch that holds a program counter. A signal line 151 indicating the program counter output from the latch 150 is connected to an increment circuit 152. Is incremented at every clock cycle, and the signal line 153 indicating the instruction fetch program counter is also incremented. In the conventional processor, instruction supply from the instruction memory 374 to the instruction decoding device 370 is controlled by the signal line 153 (373) output from the instruction supply control device 372.
[0008]
Further, as a prior art, for example, there is a processor having an instruction bit field in which two instruction execution instructions that are not simultaneously executed are arranged as disclosed in JP-A-9-84004. FIG. 10 shows a schematic diagram of such an instruction bit field. 111 indicates an instruction bit field for executing a plurality of instructions at the same time, 112 indicates an instruction bit field for executing one instruction execution instruction that is not simultaneously executed, and 113 is obtained by compressing one instruction execution instruction that is not simultaneously executed. The instruction bit field including two one instruction execution instructions that are not simultaneously executed is shown. In each instruction bit field, 114 and 115 are combinations of 2 bits, and the instruction bit field includes a plurality of instructions that can be executed simultaneously, a single instruction execution instruction that is not executed simultaneously, or two instructions that are not executed simultaneously Is a bit indicating whether or not to include.
Reference numerals 116 and 117 denote a plurality of instructions that can be executed simultaneously, and reference numerals 118, 119, and 120 denote one instruction execution instructions that are not executed simultaneously.
[0009]
By defining the instruction bit field as described above and providing an instruction that can execute a plurality of instructions simultaneously, one instruction that cannot be executed simultaneously by compressing the instruction as compared with the information processing apparatus including the instruction shown in FIG. Although it is possible to reduce the waste of the instruction bit field when executing the instruction to be executed, in such a configuration, only two instructions can be compressed and arranged in the unit instruction bit field, so that an effective instruction code is reduced. There is a problem that the effective area of the instruction memory cannot be reduced.
[0010]
Furthermore, even if the code is reduced by arranging a plurality of instructions that are not simultaneously executed on the instruction bit field, the instruction supply control device configured as shown in FIG. Since it is compressed into two packages, the instruction is double-counted, and the address in the instruction memory and the value of the instruction fetch program counter 153 are misaligned. It was.
[0011]
Further, in the conventional configuration as shown in FIG. 9, since a plurality of instructions that are not simultaneously executed are not arranged on the instruction bit field, it is necessary to always access the instruction memory, and the power consumption in the memory is reduced. There was a problem of increasing.
[0012]
[Problems to be solved by the invention]
The conventional information processing control apparatus is configured as described above, and when executing a single instruction execution instruction that is not executed simultaneously, the problem is that the area of the instruction memory increases, and it is necessary to always access the instruction memory. There is a problem that power consumption in the memory increases.
[0013]
The present invention has been made to solve the above-described problems, and provides an information processing control apparatus capable of reducing instruction codes, and consequently reducing the area of the instruction memory, and performing correct instruction supply control to the instruction memory. The purpose is to do.
It is another object of the present invention to provide an information processing control apparatus that can reduce power consumption in a memory.
[0014]
[Means for Solving the Problems]
An information processing control apparatus according to claim 1 of the present invention includes an instruction decoding means for decoding an instruction, an instruction supply control means for controlling instruction supply, a register group for holding data, an instruction memory for storing instructions, According to the instruction decoded by the instruction decoding means, it has a plurality of arithmetic circuits that read data from the register group and execute an operation using this data, and do not execute simultaneously with an instruction that executes a plurality of instructions simultaneously In the information processing control device that accepts a command to execute a single command execution command, the command Supply control means Unit instruction bit field In Bit indicating that multiple instructions that are not executed simultaneously are placed as well as Bit indicating the total number of instructions executed by one instruction Based on the control, the supply of the unit instruction from the instruction memory to the instruction decoding means is controlled. To do.
[0015]
An information processing control apparatus according to claim 2 of the present invention is the information processing control apparatus according to claim 1, wherein the instruction supply control means has a first counter representing an address on the instruction memory. , Having a second counter representing an instruction number on the instruction bit field, and performing addressing by the first counter in accordance with a bit indicating the total number of one instruction execution instructions that cannot be executed simultaneously A program counter control means for controlling is provided.
[0016]
An information processing control apparatus according to claim 3 of the present invention is the information processing control apparatus according to claim 2, wherein the instruction supply control means includes the first counter and the first counter for each clock cycle. An increment circuit that outputs a value obtained by increasing the value of the first counter, and a selector that selects and outputs either the value held by the first counter or the value output by the increment circuit. The program counter control means counts the value of the bit indicating the total number of one instruction execution instructions that cannot be executed simultaneously at the same timing as the operation of the first counter, and until the counting is completed. During this period, a signal for controlling the selector is output so that the value of the first counter is selected from the selector and output.
[0017]
An information processing control apparatus according to claim 4 of the present invention is the information processing control apparatus according to claim 2, wherein a program counter value representing an address on the instruction memory at the time of issuing the branch instruction and an instruction bit field On the instruction bit field, the counter value representing the instruction number, the program counter value representing the address on the instruction memory in the delay slot that exists between the time when the branch instruction is decoded and the time when the branch destination instruction is actually decoded Branch address correction means for dynamically setting the branch address by controlling the address by the instruction supply control means based on the counter value representing the instruction number.
[0018]
An information processing control apparatus according to claim 5 of the present invention is the information processing control apparatus according to claim 2, wherein a program counter value representing an address on the instruction memory when an interrupt occurs and a unit instruction bit field Resource saving means for saving a counter value representing an instruction number is provided.
[0019]
An information processing control apparatus according to claim 6 of the present invention is the information processing control apparatus according to claim 2, wherein one instruction execution instruction that is not simultaneously executed is bit-compressed, and a plurality of non-simultaneous execution instructions are provided on the instruction bit field An identifier indicating whether or not an instruction execution instruction is arranged is provided in the code of the instruction.
[0020]
An information processing control apparatus according to claim 7 of the present invention is the information processing control apparatus according to claim 2, wherein the program counter control means detects a plurality of instruction execution instructions that cannot be executed simultaneously by the instruction decoding means. And an instruction memory control means for prohibiting access to the instruction memory.
[0021]
An information processing control apparatus according to claim 8 of the present invention is the information processing control apparatus according to claim 2, wherein when the branch instruction is decoded, it indicates whether the branch destination instruction is a plurality of one instruction execution instructions that are not simultaneously executed. Data holding means for temporarily holding information and a value indicating the processing order on the instruction bit field, and the program counter control device executes the execution order number of the instruction held in the data holding means at the branch destination Are read out and processing corresponding to each command is performed.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
The information processing control apparatus according to the first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram showing an instruction bit field of the information processing control apparatus according to the first embodiment. 131 indicates an instruction bit field for simultaneously executing a plurality of instructions, 132 indicates an instruction bit field for executing one instruction execution instruction that is not simultaneously executed, 133 indicates an instruction including a plurality of one instruction execution instructions that are not simultaneously executed Indicates a bit field. Further, in each instruction bit field, 134 and 135 indicate whether the instruction bit field includes a plurality of instructions that can be executed simultaneously, one instruction execution instruction that is not executed simultaneously, or a plurality of instruction execution instructions that are not executed simultaneously. Is a bit.
[0023]
In the instruction bit field 131, 136 and 137 indicate a plurality of instructions that can be executed simultaneously. In the instruction bit field 132, 138 indicates one instruction execution instruction that is not simultaneously executed. Further, in the instruction bit field 133, 139 indicates the total number of instructions that are not simultaneously executed included in the instruction bit field, and 140, 141, and 142 indicate instructions that are not executed simultaneously. .
[0024]
FIG. 2A is a block diagram showing a configuration of the information processing control apparatus according to the first embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 8 denote the same or corresponding parts, and reference numeral 290 denotes a program counter that outputs an instruction supply control command 291 for controlling the operation of the instruction supply control apparatus 400 according to the decoding result of the instruction decoding apparatus 370. PC) control device. Other configurations are the same as those in FIG.
[0025]
FIG. 2B is a block diagram showing a detailed configuration of the instruction supply control device 400 and the program counter control device 290 constituting the information processing control device. In the figure, 160 indicates a program counter indicating an address in the instruction memory, 170 indicates a latch indicating whether or not a plurality of instructions that are not simultaneously executed are executed, and 171 indicates an instruction bit field. This is a latch counter that represents the instruction number. Reference numeral 177 denotes a signal line sent from the instruction decoding device 370, which indicates whether or not the instruction being decoded is an instruction execution instruction that is not simultaneously executed. Reference numeral 178 denotes a signal line sent from the instruction decoding device 370, which indicates the total number of instructions that are being decoded and that are not simultaneously executed. These signals on the signal lines 177 and 178 are latched with the latch 170 only when the currently executed instruction is a plurality of one instruction execution instructions that are not simultaneously executed and is the first instruction to be executed on the instruction bit field. The counter 171 is set as an initial value.
[0026]
The signal line 172 indicating the counter value output from the latch counter 171 that holds the counter value is decremented by the decrement circuit 173, thereby decrementing the latch counter 171 that holds the latch every clock cycle. The input signal line 174 is also decremented.
[0027]
Reference numeral 176 denotes a control circuit for controlling the instruction supply controller 400, and a control line signal 175 for controlling the operation of the instruction supply controller 400 from the output signal 180 from the latch 170 and the output signal 179 from the latch counter 171. (291) is generated. The signal line 161 indicating the program counter value output from the latch (program counter) 160 that holds the program counter value is incremented by the increment circuit 162, and the program counter 160 is incremented every clock cycle, or the previous value is left as it is. Whether the signal is held is determined by controlling the selector 164 to control the signal on the control line 175 to be controlled.
[0028]
For example, a value indicating that a plurality of one instruction execution instructions that cannot be executed simultaneously is input to the signal line 177 and a total number “3” of one instruction execution instructions that cannot be executed simultaneously is input to the signal line 178. In this case, a signal for controlling the selector 164 to hold the value of the program counter 160 is supplied to the selector 164 of the instruction supply control device 400 via the control signal 175, and the value of the latch counter 171 is decremented by the decrement circuit 173. This state is continued for a period until “0” becomes “0”. Since the program counter 160, the latch counter 171 and the decrement circuit 173 operate with the same clock, the value of the program counter 160 is held and output during the period of three clocks.
Similarly, the value of the signal line 163 indicating the instruction fetch program counter is determined by the signal of the control line 175.
[0029]
Next, the command processing operation of the information processing control apparatus having the above configuration will be described with reference to FIG.
First, when processing is started, in step S1200, the instruction is decoded by the instruction decoding device 370, and it is determined whether or not a plurality of one instruction execution instructions that cannot be executed simultaneously are included.
[0030]
If it is determined in step S1200 that the decoded instruction does not include a plurality of instructions that cannot be executed simultaneously, the process proceeds to step S1202, and the instruction supply control device 400 increments the value of the program counter by one. Output the value.
[0031]
On the other hand, if it is determined in step S1200 that the decoded instruction includes a plurality of one instruction execution instructions that cannot be executed simultaneously, the process proceeds to step S1201 and the latch counter 171 constituting the program counter control device 290 is executed. It is checked whether or not the value of 0 is 0, and the process is repeated until this value becomes 0. As a result, the same value (instruction fetch) is output from the instruction supply control device 400 during the clock period until the value of the latch counter 171 becomes zero.
[0032]
If it is determined in step S1201 that the value of the latch counter 171 has become 0, the process proceeds to step S1202, and the instruction supply control device 400 determines that the value obtained by incrementing the value of the program counter 160 by one. Is output.
[0033]
As described above, according to the first embodiment, a plurality of one instruction execution instructions that cannot be executed simultaneously are arranged in the unit instruction bit field, and the total number of one instruction execution instructions 140 to 142 that cannot be executed simultaneously is calculated. Since the instruction decoding device 370 detects the bit 139 and controls the count value of the instruction supply control device 400 by the program counter control device 290, the address on the instruction memory 374 and the instruction fetch program counter are provided. Since the value of 163 coincides with that of one instruction execution instruction that cannot be executed at the same time, the instruction code can be reduced, and the instruction supply can be correctly executed to realize the normal operation of the circuit.
[0034]
(Embodiment 2)
The information processing control apparatus according to the second embodiment of the present invention will be described below. FIG. 3A is a block diagram showing the configuration of the information processing control apparatus according to the second embodiment. The same reference numerals as those in FIG. 2 denote the same or corresponding parts. In FIG. 3, 401 is a branch address correction apparatus. In response to the output signal of the program counter control device 290 and the output signal (offset value) 402 of the instruction decoding device 370, the corrected branch address 203 is output to the instruction supply control device 400a.
[0035]
FIG. 3B is a block diagram showing a detailed configuration of the command supply control device 400a constituting the information processing control device. The branch address correction circuit 401 includes an adder 200, a branch address control circuit 202, and a branch address control circuit control circuit 218 as main elements.
[0036]
When the instruction bit format includes a plurality of instructions that are not executed simultaneously, a delay slot caused by a branch instruction (an instruction input after the period from when the branch instruction is decoded until branch processing is actually performed) ), The assembler becomes complicated for the instruction assembler to correctly calculate the branch destination, and there is a possibility that the branch cannot be realized.
[0037]
The branch address control circuit 202 is a branch address control circuit that dynamically controls the branch destination address from the state of the branch instruction and the state of the instruction in the delay slot in the branch, that is, the presence or absence of compression and the address information. This makes it possible to realize branching accurately.
[0038]
In the branch address control circuit control circuit 218, 210 is a latch indicating whether or not the branch instruction is an instruction execution instruction that is not simultaneously executed, and 211 is an instruction bit format in one instruction execution instruction that is not a branch instruction. This is a latch indicating the order of the instruction to be processed. 214 is a latch indicating whether or not the branch delay instruction is a non-simultaneous execution instruction, and 215 is the instruction processed in the instruction bit format in the single instruction execution instruction where the branch delay instruction is not simultaneous execution. This is a latch indicating the above.
[0039]
212, 213, 216, and 217 are signals output from the latches 210, 211, 214, and 215, and are input to the control circuit 218a. The control circuit 218a is configured to generate a control line signal 220 from the branch instruction state and the branch delay instruction state, and to control the branch address control circuit 202 by the signal 220. Reference numeral 203 denotes a signal line indicating a branch address generated from the branch address control circuit 202. The signal line 161 indicating the value of the program counter output from the latch 160 is incremented by the increment circuit 162 and increments the program counter 160 every clock cycle, keeps the previous value as it is, or branches to Whether the address is taken in is determined by the operation state of the selectors 230 and 164. Reference numeral 165 denotes an input signal to the latch 160 that holds the program counter. The output signal 163 from the increment circuit 162 is added to the offset 402 by the adder 200, and the added output signal 201 is input to the branch address control circuit 202. The instruction fetch program counter value 231 is determined by switching the signal line 203 representing the branch address and the output signal line 163 of the increment circuit 162 with the selector 230.
[0040]
Further, in the instruction supply control device 400a, a selector 230 for selecting and outputting either the output of the increment circuit 162 or the output of the branch address correction device 401 is added. Different from the control device 400. The selector 230 is controlled by an output signal 371a of the instruction decoding device 370, and an input of the selector 164 is connected to an output terminal thereof.
[0041]
Next, the instruction processing operation of the information processing control apparatus having the above configuration will be described with reference to FIG.
When the process starts, it is determined in step S1300 whether or not there is a branch in the instruction decoding device 370. If there is no branch, the process proceeds to step S1200, and the flow process described in FIG. 12 is performed.
[0042]
On the other hand, if it is determined in step S1300 that there is a branch, the process proceeds to step S1301, and the control circuit 218a executes a branch instruction based on the output of the branch address control circuit control circuit 218 constituting the branch address correction device 401. From the relationship between the branch delay instruction and the branch delay instruction, it is determined whether or not the branch destination address needs to be corrected. If correction is not necessary, the process proceeds to step S1302, and the branch address control circuit 202 offsets the value of the program counter. A value obtained by adding the values is output, the branch address 203 is selected by the selector 230, and is finally output as an instruction fetch.
[0043]
On the other hand, if it is determined in step S1301 that the branch destination address needs to be corrected, the process proceeds to step S1303, where the branch address control circuit 202 adds the offset value to the value of the program counter. Further, a branch instruction and a correction value corresponding to the delay slot are added and outputted, and the branch address 203 is selected by the selector 230 and outputted as an instruction fetch.
[0044]
As described above, according to the information processing control apparatus according to the second embodiment, the branch address correction apparatus 401 is provided, and the branch destination address is corrected from the relationship between the branch instruction and the delay slot. The upper address matches the value of the instruction fetch program counter 231. Even when a branch instruction is included, one instruction execution instruction that cannot be executed simultaneously can be more efficiently compressed to reduce the instruction code. At the same time, the normal operation of the circuit can be realized by correctly executing the instruction supply.
[0045]
(Embodiment 3)
Next, an information processing control apparatus according to the third embodiment of the present invention will be described. FIG. 4A is a block diagram showing the configuration of the information processing control apparatus according to the third embodiment. In the figure, the same reference numerals as those in FIG. 3 denote the same or corresponding parts, and 403 indicates when an interrupt occurs. This is a resource saving device that saves a program counter value representing an address on the instruction memory 374 and a counter value representing an instruction number on the instruction bit field.
[0046]
FIG. 4B is a block diagram showing a detailed configuration of the instruction supply control device 400b and the program counter control device 290 constituting the information processing control device. In the figure, when an interrupt occurs, the value of the program counter 160 is saved in the latch 280, and further, the value of the latch 170 indicating whether the instruction is not executed simultaneously is saved in the latch 281, and the instruction number in the instruction bit field is changed. The counter 251 to be represented is configured to be retracted to the latch 282.
[0047]
Furthermore, when restoring from an interrupt, the value of the latch 280 saved at the time of the interrupt is set as an address on the memory of the value of the program counter 160, and the value of the latch 281 is set as one instruction execution instruction that is not executed simultaneously with the branch instruction. The latch 170 indicating whether or not is set, and the value of the latch 282 is set to the counter 251 indicating the instruction number on the instruction bit field. With the configuration as described above, by performing the above setting at the time of interrupt and at the time of restoration from an interrupt, the address on the instruction memory 374 and the value of the instruction fetch program counter 231 are made to coincide with each other, so When the instruction code is reduced by efficient compression, the instruction can be correctly supplied to realize normal operation of the circuit.
[0048]
The signal line 161 indicating the program counter output from the latch 160 is incremented by the increment circuit 162. Whether the program counter 160 takes in the incremented value of the program counter 160 every clock cycle, or takes in the previous value as it is, Whether the branch address 270 (data line A) supplied from the interrupt controller 404 when an interrupt occurs or whether the value saved in the latch 280 is used for restoration from the interrupt is determined by the selector 230a and the selector 164. It is comprised so that it may be selected using.
[0049]
Next, the command processing operation of the information processing control apparatus having the above configuration will be described with reference to FIG.
First, when the process is started, if no interrupt is detected by the interrupt controller in step S1400, the process proceeds to step S1200, and the process is performed in the same procedure as shown in FIG.
[0050]
On the other hand, if an interrupt is detected by the interrupt controller, the process proceeds to step S1401, and the interrupt controller 404 sends an instruction supply control device 400b indicated by the data line B to the resource saving device 403 by a signal on the control line B. And an instruction to save the value of the latch 170 and the value of the counter 251 to the latches 281 and 282 indicated by the data line D, respectively.
[0051]
Next, when an interrupt routine is executed in step S1402, then in step S1403, the instruction decoding device 370 latches 280 to 282 with respect to the resource saving device 403 by a signal indicated by the control line C in step S1401. The program counter 160, the latch 170, and the counter 251 are instructed to restore the values saved in the data lines C and E, respectively.
[0052]
As described above, according to the third embodiment, the resource saving device 403 is provided, and when an interrupt is detected by the interrupt controller 404, the program counter value indicating the address on the instruction memory 374 and the instruction bit field are displayed. The counter value indicating the instruction number of the instruction is saved in the resource saving device 403, and the value saved in the resource saving device 403 is restored to the original after completion of the interrupt processing. When the instruction code is reduced by efficient compression, the process can be reliably restored even if an interrupt process occurs.
[0053]
(Embodiment 4)
Next, an information processing control apparatus according to Embodiment 4 of the present invention will be described. FIG. 5 illustrates a directive indicating whether one instruction execution instruction that is not simultaneously executed is compressed and a plurality of instructions that are not simultaneously executed are arranged on the instruction bit field in the information processing control apparatus according to the fourth embodiment. The state of data when an instruction assembler is provided is shown.
[0054]
In the figure, reference numerals 300 and 301 denote directives that specify that compression is not performed. When the instruction assembler detects a code enclosed by the directives 300 and 301 in the instruction code, the instruction assembler does not perform bit compression on the instructions in between. That is, when creating an instruction code, by creating a portion surrounded by directives, it is possible to set that there is no plural instruction execution instructions that are not simultaneously executed on the instruction bit field.
As described above, according to the fourth embodiment, since a code is enclosed in a direct manner with respect to an instruction unsuitable for compression, a command unsuitable for compression can be protected.
[0055]
(Embodiment 5)
Next, an information processing control apparatus according to Embodiment 5 of the present invention will be described. When an instruction including multiple instruction execution instructions that are not simultaneously executed on the instruction bit field is being executed, in practice, multiple instructions can be fetched by accessing the instruction memory once. In such a case, it is virtually unnecessary to access the instruction memory every time an instruction is executed. In the fifth embodiment, unnecessary access to the memory in such a case is reduced to reduce power consumption.
[0056]
6A is a block diagram illustrating the configuration of the information processing control apparatus according to the fifth embodiment. The same reference numerals as those in FIG. 2 denote the same or corresponding parts, and the 176 control circuit includes the latch 170. From the output signal 180 and the output signal 179 of the counter 171, a control signal (control line) 340 for stopping access to the instruction memory 374 and a control signal 341 for stopping data fetching into the buffer 346 are generated.
[0057]
Reference numeral 342 denotes an access determination circuit. When a control signal 340 for stopping access to the instruction memory 374 is received, the access to the instruction memory 374 is stopped using the control line 343 to the instruction memory 374. Reference numeral 345 represents output data from the instruction memory 374.
[0058]
Further, when the buffer 346 receives the control signal 341 for stopping the data capture, the buffer 346 stops the data capture from the instruction memory 374. Thus, once an instruction including a plurality of instruction execution instructions that are not simultaneously executed is fetched onto the instruction bit field, the instruction decoding device 370 reads all the instructions that are not simultaneously executed from the buffer 346 until all instructions are decoded. The output data 347 is retained, and the instruction is decoded correctly.
[0059]
Next, an instruction processing operation of the information processing control apparatus having the above configuration will be described with reference to FIG.
First, when the process is started, access to the normal memory 374 is permitted in step S1500, and the program counter control device 290 enables access to the memory access determination device 342. The control signal 340 is sent to permit access to the memory 374, and the control signal 341 is sent to the buffer 346 to indicate that data take-in is permitted to take in data from the memory 374. If normal processing is permitted, the process proceeds to step S1501.
[0060]
Next, in step S1501, the instruction decoding device 370 determines whether or not it includes a plurality of one instruction execution instructions that cannot be executed simultaneously. If a plurality of one instruction execution instructions that cannot be executed simultaneously are not included, step S1504 The program counter 160 is incremented by one. On the other hand, in step S1501, the instruction decoding device 370 determines whether or not it includes a plurality of one instruction execution instructions that cannot be executed simultaneously, and determines that a plurality of one instruction execution instructions that cannot be executed simultaneously are included. If it is determined that the access to the memory 374 is not permitted, the program counter control device 290 transmits a control signal 340 indicating that the memory access determination device 342 is not allowed to access to prohibit access to the memory 374. By sending a control signal 341 indicating that data fetching is not permitted to the buffer 346, data fetching from the memory 374 is prohibited.
[0061]
Then, the process proceeds to step S1503, and the state of step S1502 is maintained until the value of the counter 171 constituting the program counter control device 290 becomes zero.
If it is determined in step S1503 that the counter value has become 0, the process proceeds to step S1504, and the value of the program counter 160 is incremented by one.
[0062]
As described above, according to the fifth embodiment, the program counter control device 290 prohibits the memory access determination unit 342 from accessing the memory 374 when a plurality of instructions that cannot be executed simultaneously are detected. Since the control signal 340 and the buffer 346 are output to the control signal 341 for prohibiting the fetching of data from the memory 374, useless access to data that has already been read can be reduced. Power consumption can be reduced.
[0063]
(Embodiment 6)
Next, an information processing control apparatus according to Embodiment 6 of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the information processing control apparatus according to the sixth embodiment. In the figure, the same reference numerals as those in FIG. 2 denote the same or corresponding parts, and 500 denotes a branch instruction in the instruction decoding apparatus 370. When decoded, it is a latch that temporarily holds information indicating whether or not the branch destination instruction is a plurality of one instruction execution instructions that are not simultaneously executed, and a value indicating the processing order on the instruction bit field.
[0064]
The operation will be described below.
In the information processing control apparatus according to the sixth embodiment having the above-described configuration, a branch destination offset and a branch instruction whose branch destination is not simultaneously executed on the instruction bit field are included in the branch instruction as the instruction bit field. By including information on whether or not to branch to an instruction including an execution instruction and information on what order is executed on the bit field of the instruction at the branch destination in the instruction, which instruction is in turn after branching It is possible to arbitrarily decide whether to execute.
[0065]
That is, when a branch instruction is input to the instruction decoding device 370, the value (latch counter value) from the latch 500 when the information branches to the branch destination from the information to the instruction supply control circuit 400 (see FIG. 2). To control the instruction supply correctly.
[0066]
Further, when the branch instruction is issued, information indicating whether or not the branch destination branches to an instruction including a plurality of one instruction execution instructions that are not simultaneously executed on the instruction bit field, and the number of instructions in the instruction memory at the branch destination in the instruction is executed. This information is saved in the latch 500, and the branch instruction is executed. Next, when the instruction decoding unit 370 decodes the branch destination instruction, the program counter control unit 290 reads information from the latch 500 and indicates whether or not it includes a plurality of one instruction execution instructions, and an instruction bit. Values indicating the processing order on the field are set in the latch 170 and the counter 171 respectively.
By doing these things, it is possible to arbitrarily branch to any one of a plurality of one instruction execution instructions that cannot be executed simultaneously.
[0067]
As described above, according to the sixth embodiment, when there are a plurality of one instruction execution instructions that cannot be executed simultaneously, the signal indicating whether or not a plurality of one instruction execution instructions are included and the processing order on the instruction bit field are set. The instruction value is stored in the latch 500 and the order of the instructions is read from the latch 500 by the program counter controller 290 so that the processing according to the order is performed at the branch destination. In this process, the degree of freedom in branching can be improved.
[0068]
In each of the above embodiments, the example in which three instructions are arranged in the unit instruction bit field is shown as an example. However, the number of instructions arranged in the unit instruction bit field is not limited to this. Needless to say.
[0069]
【The invention's effect】
As described above, according to the information processing control apparatus of the first aspect of the present invention, the instruction decoding means for decoding the instruction, the instruction supply control means for controlling the instruction supply, the register group for holding the data, the instruction And a plurality of arithmetic circuits for reading data from the register group and executing an operation using the data according to the instruction decoded by the instruction decoding means, and simultaneously executing a plurality of instructions In the information processing control device that receives an instruction to execute and an instruction to execute one instruction execution instruction that is not simultaneously executed, the above instruction Supply control means Unit instruction bit field In Bit indicating that multiple instructions that are not executed simultaneously are placed as well as Bit indicating the total number of instructions executed by one instruction Based on the control, the supply of the unit instruction from the instruction memory to the instruction decoding means is controlled. Therefore, there is an effect that the instruction code can be further compressed and consequently the memory area can be reduced.
[0070]
According to an information processing control device of a second aspect of the present invention, in the information processing control device according to the first aspect, the instruction supply control means has a first counter representing an address on the instruction memory. A second counter representing an instruction number on the instruction bit field, and the addressing by the first counter is a bit indicating the total number of one instruction execution instructions that cannot be executed simultaneously. Since it has a program counter control means for controlling it accordingly, the effect is that the address in the instruction memory and the value of the instruction fetch program counter can be synchronized even if a plurality of instruction codes are compressed. Is obtained.
[0071]
According to an information processing control device of a third aspect of the present invention, in the information processing control device according to the second aspect, the command supply control means includes the first counter and the first counter every clock cycle. An increment circuit that outputs a value obtained by increasing the counter value, and a selector that selects and outputs either the value held by the first counter or the value output by the increment circuit. The program counter control means counts the value of the bit indicating the total number of one instruction execution instructions that cannot be executed simultaneously at the same timing as the operation of the first counter, and the counting ends. In the meantime, a signal for controlling the selector is output so that the value of the first counter is selected and output from the selector. Be compressed code, there is an advantage that it is possible to synchronize the value of the address and instruction fetch program counter on instruction memory.
[0072]
According to the information processing control apparatus of claim 4 of the present invention, in the information processing control apparatus of claim 2, the program counter value indicating the address on the instruction memory when the branch instruction is issued, and the instruction bit field A counter value representing the instruction number in the program, a program counter value representing an address on the instruction memory in a delay slot existing after the branch instruction is decoded and before the branch destination instruction is actually decoded, and an instruction bit field Since branch address correction means for controlling the address by the instruction supply control means and dynamically setting the branch address from the counter value representing the instruction number above is included, a branch instruction is included. Even in this case, it is possible to more efficiently compress instructions that cannot be executed simultaneously and reduce the instruction code. There is an advantage that it is possible to realize normal operation of the circuit to properly perform.
[0073]
According to the information processing control apparatus of claim 5 of the present invention, in the information processing control apparatus of claim 2, the program counter value indicating the address on the instruction memory when an interrupt occurs, and the unit instruction bit field Since the resource saving means for saving the counter value indicating the instruction number at the time is provided, the process can be surely restored even if interrupt processing occurs.
[0074]
According to the information processing control device of claim 6 of the present invention, in the information processing control device according to claim 2, one instruction execution instruction that is not simultaneously executed is bit-compressed, and a plurality of instructions that are not simultaneously executed on the instruction bit field are compressed. Since an identifier indicating whether or not to execute one instruction execution instruction is provided in the code of the instruction, an effect that a command unsuitable for compression can be protected is obtained.
[0075]
According to an information processing control apparatus of claim 7 of the present invention, in the information processing control apparatus of claim 2, the program counter control means is a plurality of one instruction execution instructions that cannot be executed simultaneously by the instruction decoding means. When an error is detected, instruction memory control means for prohibiting access to the instruction memory is provided, so that useless access to data that has already been read can be reduced, thereby reducing memory power consumption. The effect of being able to be obtained.
[0076]
According to the information processing control apparatus of claim 8 of the present invention, in the information processing control apparatus of claim 2, whether or not the branch destination instruction is a plurality of one instruction execution instructions that are not simultaneously executed when the branch instruction is decoded. And a data holding means for temporarily holding a value indicating the processing order on the instruction bit field, and the program counter control device executes the instruction held in the data holding means at the branch destination. Since the sequence number is read and the processing according to each instruction is performed, it is possible to execute the compressed instruction at an arbitrary branch destination at an arbitrary timing, thereby improving the degree of freedom of processing branching. The effect that it can plan is acquired.
[Brief description of the drawings]
FIG. 1 is a diagram showing an outline of an instruction bit field in a processor which is an information processing control apparatus of the present invention.
FIG. 2 is a diagram illustrating a configuration of a processor that is an information processing control device according to a first embodiment of the present invention, and a detailed configuration of an instruction supply control device that configures the information processing control device.
FIG. 3 is a diagram illustrating a configuration of a processor that is an information processing control device according to a second embodiment of the present invention, and a detailed configuration of an instruction supply control device that configures the information processing control device.
FIG. 4 is a diagram illustrating a configuration of a processor that is an information processing control apparatus according to a third embodiment of the present invention, and a detailed configuration of an instruction supply control apparatus that configures the information processing control apparatus.
FIG. 5 is a diagram showing a data format for explaining instruction compression prohibition designation by direct in a processor which is an information processing control apparatus according to a fourth embodiment of the present invention;
FIG. 6 is a diagram illustrating a configuration of a processor that is an information processing control apparatus according to a fifth embodiment of the present invention, and a detailed configuration of an instruction supply control apparatus that configures the information processing control apparatus.
FIG. 7 is a diagram illustrating a configuration of a processor that is an information processing control apparatus according to a sixth embodiment of the present invention, and a detailed configuration of the information processing control apparatus that configures the information processing control apparatus.
FIG. 8 is a diagram illustrating a configuration of a processor which is a general conventional information processing control apparatus.
FIG. 9 is a diagram showing an outline of an instruction bit field in a conventional processor.
FIG. 10 is a diagram showing an outline of an instruction bit field in another conventional processor.
FIG. 11 is a diagram showing an example of a detailed configuration of an instruction supply control device constituting a conventional processor.
FIG. 12 is a diagram describing a flow for explaining the operation of the information processing control apparatus according to the first embodiment;
FIG. 13 is a diagram describing a flow for explaining the operation of the information processing control apparatus according to the second embodiment;
FIG. 14 is a diagram describing a flow for explaining the operation of the information processing control apparatus according to the third embodiment;
FIG. 15 is a diagram describing a flow for explaining the operation of the information processing control apparatus according to the fifth embodiment;
[Explanation of symbols]
131-133 Instruction bit field
134, 135 is a bit indicating whether the instruction bit field includes a plurality of instructions that can be executed simultaneously, one instruction execution instruction that is not executed simultaneously, or a plurality of one instruction execution instructions that are not executed simultaneously
136-138 instructions
139 A bit indicating the total number of instructions that are not simultaneously executed and are included in the instruction bit field.
140-142 instructions (compressed)
160 Latch holding program counter
161 Signal line indicating program counter
162 Increment circuit (+1)
163 Signal line indicating instruction fetch program counter
164 selector
165 Signal line indicating the input to the latch holding the program counter
170 Latch
171 Latch counter
172 Signal line indicating counter
173 Decrement circuit (-1)
174 Signal line indicating the input to the latch holding the counter
175 Control line
176 Control circuit (command memory control means)
177, 178 Signal line input from instruction decoding device
179 Output signal
180 Signal line output from latch 170
181 Program counter control circuit
200 adder
201 Signal line output from adder
202 Branch address control circuit
203 Signal line output from the branch address control circuit
210, 211 latch
212, 213 Signal line output from latch
214,215 Latch
216, 217 Signal line output from latch
218 Branch address control circuit control circuit
218a control circuit
220 Control line signal
230 Selector
231 Signal line indicating instruction fetch program counter
251 Latch holding the counter
Branch address at 270 interrupt
280-282 latch
290 Program counter (PC) controller
300, 301 directive
340, 341 Control line
342 Memory access determination device
343 Control line
345 data line
346 buffer
347 data line
370 Instruction decoding device
374 instruction memory
377 registers
379 calculator
400, 400a, 400b Command supply control device
401 Branch address correction device
402 Offset value
403 Resource saving device
404 Interrupt controller
500 latches

Claims (8)

Instruction decoding means for decoding instructions, instruction supply control means for controlling instruction supply, a register group for holding data, an instruction memory for storing instructions, and the register group according to the instructions decoded by the instruction decoding means Information processing control having a plurality of arithmetic circuits that read data from and execute operations using this data, and that accept instructions that simultaneously execute a plurality of instructions and instructions that execute a single instruction execution instruction that is not simultaneously executed In the device
The instruction supply control means, based on the bit indicating bits and the total number of said single instruction execution instructions indicate that are arranged a plurality of single instruction execution instruction not simultaneous execution in a unit instruction bit field from said instruction memory Controlling the supply of the unit instruction to the instruction decoding means ;
An information processing control device. The information processing control device according to claim 1,
The instruction supply control means has a first counter representing an address on the instruction memory,
A second counter that represents an instruction number in the instruction bit field, and controls addressing by the first counter according to a bit indicating a total number of instructions that can be executed simultaneously; Provided with a program counter control means for
An information processing control device. The information processing control device according to claim 2,
The instruction supply control means includes the first counter, an increment circuit that outputs a value obtained by increasing the value of the first counter every clock cycle, a value held by the first counter, or the increment And a selector that selects and outputs any one of the values output by the circuit,
The program counter control means counts the value of the bit indicating the total number of one instruction execution instructions that cannot be executed simultaneously, at the same timing as the operation of the first counter, and until the counting is completed. Outputting a signal for controlling the selector so that the value of the first counter is selected and output from the selector;
An information processing control device. The information processing control device according to claim 2,
The program counter value that represents the address in the instruction memory when the branch instruction is issued, the counter value that represents the instruction number in the instruction bit field, and the time after the branch instruction is decoded until the branch destination instruction is actually decoded The address by the instruction supply control means is controlled from the program counter value indicating the address on the instruction memory in the delay slot existing in the memory and the counter value indicating the instruction number on the instruction bit field, and the branch address is dynamically set. With branch address correction means to set,
An information processing control device. The information processing control device according to claim 2,
Provided with a resource saving means for saving a program counter value representing an address on the instruction memory and a counter value representing an instruction number on a unit instruction bit field when an interrupt occurs;
An information processing control device. The information processing control device according to claim 2,
An instruction indicating whether or not one instruction execution instruction that is not simultaneously executed is bit-compressed and a plurality of instructions that are not simultaneously executed are arranged on the instruction bit field is provided in the code of the instruction.
An information processing control device. The information processing control device according to claim 2,
The program counter control means comprises instruction memory control means for prohibiting access to the instruction memory when a plurality of one instruction execution instructions that cannot be executed simultaneously by the instruction decoding means are detected.
An information processing control device. The information processing control device according to claim 2,
A data holding means for temporarily holding information indicating whether or not a branch destination instruction is a plurality of instructions that are not simultaneously executed and a value indicating a processing order on the instruction bit field at the time of branch instruction decoding;
The information processing control apparatus, wherein the program counter control apparatus reads out an execution order number of instructions held in the data holding means at a branch destination and performs processing according to each instruction.

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