JP3799792B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device capable of non-destructively detecting insulation deterioration, and more particularly to a semiconductor device including an insulating substrate on which a metal pattern is formed and capable of detecting microcracks in the insulating substrate.
[0002]
[Prior art]
4A is a plan view showing a conventional semiconductor device, FIG. 4B is a cross-sectional view of the semiconductor device, and FIG. 5A is an insulating substrate constituting a part of the semiconductor device shown in FIG. FIG. 5B is a plan view of the insulating substrate.
[0003]
4A and 4B, 1 is a base plate made of a metal material such as a copper plate, 2 is an insulating substrate soldered to the base plate 1 with a thick copper foil 2c described later, and 3, 4 are insulated. A power semiconductor element soldered to the substrate 2 via a thick copper foil pattern 2b described later, 5 is a case made of insulating resin, 6 is an external electrode terminal for main current conduction, 6A is an external electrode terminal for control, 7 is an aluminum wire, external electrode terminals 6 and 6A are inserted into the case 5, and the base plate 1 is bonded to the bottom of the case 5, and the external electrode terminals 6 and 6A and the power semiconductor elements 3 and 4 Are connected by an aluminum wire 7.
[0004]
5A and 5B, 2a is a ceramic plate that is an insulator, and 2b is a thick copper foil pattern as a metal pattern formed on the front side of the ceramic plate 2a. The power semiconductor elements 3 and 4 as the semiconductor elements are soldered onto the patterned thick copper foil pattern 2b. 2c is a thick copper foil as a metal plate, which is joined to the back side of the ceramic plate 2a in the same manner as the thick copper foil pattern 2b, and is composed of a single plate joined to almost the entire back side of the ceramic plate 2a. . The insulating substrate 2 is composed of a ceramic plate 2a, a thick copper foil pattern 2b, and a thick copper foil 2c, and the thick copper foil 2c serves as a soldering surface to a base (not shown).
[0005]
Therefore, most of the heat generation in the power semiconductor elements 3 and 4 placed and soldered on the patterned thick copper foil pattern 2b on the insulating substrate 2 is the thick copper foil pattern 2b, the ceramic plate 2a, and the thick copper foil. Although heat is radiated from the base plate 1 through 2c, the power semiconductor elements 3, 4 and the base plate 1 are electrically insulated by the ceramic plate 2a.
[0006]
In the conventional semiconductor device, the insulating substrate 2 is configured as described above, and the ceramic plate 2a is less likely to cause large cracks even when thermal or mechanical stress is applied, and has a relatively large dielectric strength. It has become. However, a fine crack may be generated by applying mechanical stress in a processing process such as cutting from a wafer, and this fine crack has a predetermined dielectric strength. It may progress gradually and grow into a large crack, resulting in a decrease in dielectric strength and a failure.
[0007]
Therefore, it is necessary to detect at the stage of fine cracks. For detection of the fine cracks, a considerably high height is required between the thick copper foil pattern 2b on the front side and the thick copper foil 2c on the back side of the insulating substrate 2. It is necessary to apply a voltage.
[0008]
That is, in the semiconductor device, all the external terminals 6 and 6A electrically connected to the front-side thick copper foil pattern 2b in the insulating substrate 2 and the base plate 1 electrically connected to the back-side thick copper foil 2c. And a high voltage is applied between them. At this time, if any contact failure occurs, a voltage higher than the maximum rated voltage is applied to the power semiconductor elements 3 and 4 themselves, and the elements themselves are destroyed. In addition, when a voltage exceeding the creeping dielectric strength transmitted through the surface of the ceramic plate 2a is applied, the dielectric strength is reduced by creeping discharge.
[0009]
Thus, it is necessary to inspect the ceramic plate 2a by applying a high voltage to the allowable limit level of the dielectric strength between the thick copper foil pattern 2b and the thick copper foil 2c. For example, a high voltage is applied to the power semiconductor elements 3 and 4, which may break down or cause a creeping discharge exceeding the creeping strength of the insulating substrate 2 instead of cracking. Further, there is no means for detecting insulation deterioration during actual use, and it has not been possible to prevent insulation breakdown due to crack growth.
[0010]
[Problems to be solved by the invention]
Since the insulating substrate 2 constituting a part of the conventional semiconductor device is configured as described above, in order to detect the presence or absence of fine cracks in the insulating substrate 2, a high voltage is applied up to the allowable limit level of the dielectric strength. It is necessary to apply and inspect, but due to contact variations at the time of inspection, high voltage is applied to the power semiconductor elements 3 and 4, which breaks or exceeds the creeping strength of the insulating substrate 2 rather than cracks. There was a problem that electric discharge was generated and it was difficult to inspect the insulation deterioration of the insulating substrate 2. There is also a problem that there is no means for detecting insulation deterioration due to crack growth during actual use, and insulation breakdown cannot be prevented beforehand.
[0011]
The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device capable of detecting fine cracks in an insulating substrate composed of a ceramic plate or the like by applying a relatively low voltage. To do.
[0012]
[Means for Solving the Problems]
A semiconductor device according to a first aspect of the present invention includes an insulating substrate on which a metal pattern is formed to place a semiconductor element, and an open loop metal pattern independent of the metal pattern is formed in the vicinity of the outer peripheral portion of the insulating substrate. In the open loop metal pattern, loop portions in the vicinity of both end portions thereof are arranged in parallel and double on the same plane at a predetermined interval, and both end portions are respectively extended from one end portion to the other end portion. The pad has a current-carrying pad extending toward the top, and the pad overlaps each other when viewed from the longitudinal direction of the parallel and double portions of the loop portion .
[0015]
The semiconductor device according to the second invention is the semiconductor device according to the first invention , wherein the thickness of the open loop metal pattern is less than or equal to 1/10 of the thickness of the metal pattern on which the semiconductor element is placed. It is what.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a plan view of an insulating substrate constituting a part of the semiconductor device, FIG. 1B is an enlarged view of an end portion of an open loop copper foil pattern formed on the insulating substrate, and FIG. It is a top view which shows the whole structure. 3A is an explanatory diagram of a method for detecting fine cracks in the insulating substrate shown in FIG. 1, and FIGS. 3B and 3C are enlarged views of main parts of FIG. 3A. In the figure, the same reference numerals as those in the conventional example are the same as or equivalent to those in the conventional example.
[0018]
1 (A) and 1 (B), 2d is an open loop copper foil pattern as an open loop metal pattern, independent of a thick copper foil pattern 2b as a metal pattern on which a power semiconductor is placed on the front side of the ceramic plate 2a. And it is the very thin open pattern formed so that the outer peripheral part of the ceramic board 2a might be at least 1 round. Reference numerals 2e denote energization pads that are formed at both ends of the open loop copper foil pattern 2d and wire-bond the aluminum wires 7, respectively.
[0019]
In other words, the open loop copper foil pattern 2d can detect fine cracks generated in the ceramic plate 2a by applying a relatively low voltage between the pads 2e formed at both ends. The insulating substrate 2A is obtained by adding an open loop copper foil pattern 2d to the conventional insulating substrate 2 shown in FIG.
[0020]
In FIG. 2, 5A is a case, and 8 is an external monitor terminal provided in the case 5A by an insert. A pair of external monitor terminals 8 and a pair of pads 2e are connected by aluminum wires 7, respectively. .
[0021]
Next, a method for manufacturing the semiconductor device of the first embodiment will be described. First, a base plate 1, a case 5A provided with a plurality of external electrode terminals 6 and 6A and a pair of monitor external terminals 8, and a ceramic plate 2a having a structure in which a thick copper foil (not shown) is bonded to both surfaces. And prepare. Next, by patterning the thick copper foil bonded to the surface of the ceramic plate 2a, both ends of the thick copper foil pattern 2b and the outer periphery of the ceramic plate 2a are separated from the thick copper foil pattern 2b. At least one or more turns of the open loop copper foil pattern 2d having the pad 2e is formed. Next, the semiconductor elements 4 and 5 are soldered to the thick copper foil pattern 2b.
[0022]
Next, the insulating substrate 2A is placed and fixed on the base plate 1 by soldering a thick copper foil (not shown) bonded to the back surface of the ceramic plate 2a in the insulating substrate 2A to the base plate 1. Next, the base plate 1 on which the insulating substrate 2A is mounted and fixed is bonded to the case 5A. Finally, the external electrode terminals 6 and 6A and the thick copper foil pattern 2b and the semiconductor elements 4 and 5 soldered to the thick copper foil pattern 2b are connected by an aluminum wire 7 and a pair of monitor external terminals 8 are connected. The semiconductor device is completed by sequentially executing the step of connecting the pair of pads 2e with the aluminum wires 7 in order.
[0023]
In FIG. 3A, 9 is a tester for inspecting the continuity between the pads 2e, and a battery, a resistor, an ammeter and the like are connected in series. Next, a method for detecting insulation deterioration of a semiconductor device, that is, a method for detecting fine cracks generated in the ceramic plate 2a by applying a low voltage will be described with reference to the drawings.
[0024]
The insulating substrate 2A has one or more turns on the outer peripheral portion of the ceramic plate 2a when the fine cracks CA and CB as shown in FIGS. 3B and 3C occur in the A portion or the B portion in FIG. 3A. The open-loop copper foil pattern 2d formed in 1 is broken at the same time. At this time, if a continuity test between both ends of the pattern, that is, a continuity test between the pads 2e using the tester 9, is performed, the resistance value near zero is infinite in the normal state.
[0025]
In particular, the fine crack CB generated only on the ceramic surface such as part B in FIG. 3A cannot be detected by the conventional high voltage application method, and proceeds repeatedly when stress is applied, as in part A. There is a risk of growing into a fine crack CA and eventually leading to dielectric breakdown. However, in the first embodiment, by monitoring the continuity between the monitoring external terminals 8, this can be detected at the initial stage of fine cracks, and measures to prevent dielectric breakdown can be made possible.
[0026]
As described above, in the first embodiment, an extremely thin independent open-loop copper foil pattern 2d of at least one turn is formed in the vicinity of the outer peripheral portion of the ceramic plate 2a in the insulating substrate 2A on which the thick copper foil pattern 2b is formed. Since the pads 2e are provided at both ends thereof, the monitor external terminal 8 is provided on the case 5A, and the monitor external terminal 8 and the pad 2e are connected by the aluminum wire 7, so that the semiconductor device At the time of completion, fine cracks in the insulating substrate 2A can be detected by conducting a continuity test between the external terminals 8 for monitoring, and by periodically monitoring even at the actual use stage, dielectric breakdown caused by the growth of the fine cracks can be detected. It can be prevented in advance.
[0027]
Furthermore, it is possible to detect the presence or absence of fine cracks in the insulating substrate 2A alone before or after the power semiconductor elements 3 and 4 are soldered, so that a defective product in which the fine cracks are generated can be detected early.
[0028]
Further, as shown in detail in FIG. 1B, double loop portions are formed at both ends of the open loop copper foil pattern 2d in the insulating substrate 2A, and double pads 2e are formed at both ends. It is arranged opposite to the inside of the substantially parallel loop part, and the overlap part t is provided to eliminate the straight line part in the opening part, so that it always bypasses, so it is possible to reliably detect the detection of fine cracks that occur in a substantially straight line shape. Can be prevented.
[0029]
Further, the thickness of the thick copper foil pattern 2b is usually about 150 to 400 μm. When the open loop copper foil pattern 2d is formed simultaneously with the thick copper foil pattern 2b, the thickness of the open loop copper foil pattern 2d is also thick. It is formed to the same thickness as the copper foil pattern 2b. However, since the open loop copper foil pattern 2d is formed to have a narrow width of about 100 μm, it is cut following the occurrence of normal fine cracks, and there is no practical problem. However, by making the thickness of the open loop copper foil pattern 2d 1/10 or less of the thickness of the thick copper foil pattern 2b, that is, by forming it to about 10 to 30 μm, it follows the generation of finer cracks. Then, the open loop copper foil pattern 2d is cut, and the occurrence of fine cracks can be detected at an earlier stage.
[0030]
In addition, in order to form the thickness of the loop part in the open loop copper foil pattern 2d to 1/10 or less of the thickness of the thick copper foil pattern 2b, the thick copper foil pattern 2b and the open loop copper are formed on the surface of the ceramic plate 2a. After the step of forming the foil pattern 2d, a step of selectively etching the loop portion of the open loop copper foil pattern 2d is added.
[0031]
【The invention's effect】
According to the first aspect of the present invention, an independent open loop metal pattern having at least one turn and having pads at both ends is formed in the vicinity of the outer peripheral portion of the insulating substrate. The presence or absence of a crack that grows from the periphery of the substrate toward the center can be reliably inspected, and an effect that a dielectric breakdown can be prevented can be obtained.
Moreover, the vicinity of both ends of the open loop metal pattern is formed in a double on the same plane, and pads are formed on each of the both ends, and both the pads are formed in a substantially parallel loop. Since the overlapping portion is provided opposite to the inside of the opening, there is no straight portion inward from the outside of the loop in the opening, and there is also an effect that it is possible to reliably inspect cracks in any direction generated in a substantially straight line near the opening. can get.
[0034]
Further, according to the second invention, the open loop metal pattern thickness in the insulating substrate is formed relatively thin to 1/10 or less of the thickness of the metal plate patterned to mount the semiconductor element. The effect of being able to inspect fine cracks of the insulating substrate more reliably is obtained.
[Brief description of the drawings]
FIG. 1 is a plan view of an insulating substrate constituting a part of a semiconductor device as Embodiment 1 of the present invention (FIG. 1A) and an enlarged view of an end portion of an open loop copper foil pattern formed on the insulating substrate; It is a figure (FIG. 1 (B)).
FIG. 2 is a plan view of a semiconductor device on which the insulating substrate shown in FIG. 1 is mounted.
3 is an explanatory diagram of a method for detecting fine cracks in the insulating substrate shown in FIG. 1. FIG.
FIG. 4 is a plan view (FIG. 4A) and a cross-sectional view (FIG. 4B) showing a conventional semiconductor device.
5 is a plan view (FIG. 5A) and a cross-sectional view (FIG. 5B) of an insulating substrate which forms part of the semiconductor device shown in FIG. 4;
[Explanation of symbols]
1 base plate, 2A insulating substrate, 2a ceramic plate, 2b thick copper foil pattern, 2d open loop copper foil pattern, 2e pad, 3, 4 power semiconductor element, 5A case, 6, 6A external electrode terminal, 7 aluminum wire, 8 External terminal for monitor

Claims (2)

An insulating substrate on which a metal pattern is formed to place a semiconductor element,
The insulating substrate is formed with an open loop metal pattern independent of the metal pattern in the vicinity of the outer periphery thereof,
In the open loop metal pattern, loop portions in the vicinity of both end portions thereof are arranged in parallel and double on the same plane at a predetermined interval, and both end portions are respectively extended from one end portion to the other end portion. And a pad for energization extending toward the surface, wherein the pads overlap each other when viewed from the longitudinal direction of the parallel and double portions of the loop portion. Semiconductor device.   2. The semiconductor device according to claim 1, wherein the open loop metal pattern is formed to have a thickness of 1/10 or less of a thickness of a metal pattern on which a semiconductor element is placed.

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