JP3795648B2 - AC coupling buffer circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a so-called AC coupling buffer circuit, and more particularly to a circuit in which output characteristics are improved.
[0002]
[Prior art]
A so-called AC coupling buffer circuit is used, for example, when the output of a current / voltage conversion amplifier that amplifies and outputs a detection signal of an optical sensor by current / voltage conversion is amplified by a differential amplifier. A change in the output potential of the current / voltage conversion amplifier due to a DC component such as sunlight is absorbed by this AC coupling buffer circuit, and only the change in the AC component is transmitted to the differential amplifier. Used for etc.
[0003]
FIG. 2 shows an example of the circuit configuration of such a conventional AC coupling buffer circuit. The configuration and the like will be generally described below with reference to FIG.
This AC coupling buffer circuit receives an AC input signal from a preceding stage (not shown) via a so-called capacitor C1 for AC coupling, and the tenth and twelfth transistors (Q10), Q, Buffered and amplified by (Q12), and output signals are input to the next stage as outputs 1 and 2 from the respective emitters.
[0004]
The base of the tenth transistor (Q10) is supplied with a bias current _Ib10 by a sixth transistor (Q6) constituting a current mirror circuit via a so-called diode-connected ninth transistor (Q9). It is like that.
The currents of the fifth and sixth transistors (Q5) and (Q6) constituting the current mirror circuit are the same as the output current Is of the minute current source CS, and the first and second transistors (Q1) and (Q2). Is supplied as the emitter current of the fourth transistor (Q4) via the current mirror circuit of FIG. 2, and further, a current multiplied by (1 / h _fe ) times the emitter current is supplied.
[0005]
Further, the bias current I _b12 is supplied to the base of the twelfth transistor (Q12) by the sixth transistor (Q6) constituting the current mirror circuit via the so-called diode-connected eighth transistor (Q8). Has been made.
[0006]
In this configuration, the direct current potentials of the output 1 from the emitter of the tenth transistor (Q10) and the output 2 from the emitter of the twelfth transistor (Q12) are applied to the base of the twelfth transistor (Q12). The voltage of the connected DC bias power source DCb, the base-emitter voltages of the eighth and ninth transistors (Q8) and (Q9), and the bases of the tenth and twelfth transistors (Q10) and (Q12) It is to be determined by the emitter voltage, in particular, in the case where V _BE8 = V _BE9 and V _BE10 = V _BE12 is satisfied, the same potential with no so-called offset.
[0007]
[Problems to be solved by the invention]
However, in the case of the above-described conventional circuit, there is actually a problem that an offset occurs for the following reason.
That is, since the bias current Ibias flows into the DC bias power source DCb, the collector currents I _C8 and I _{C9 of} the eighth and ninth transistors (Q8) and (Q9) are not the same, and are about several nA. As a result, an offset expressed as ΔV _BE = Vt × ln (I _C9 / I _C8 ) is generated between the two outputs 1 and 2.
Here, Vt is a so-called thermal voltage, and ln is a natural logarithm.
[0008]
In the circuit described above, since I _b10 = I _b12 , I _C8 = I _b12 + Ibias and I _C8 = I _C9 are satisfied, the previous offset voltage ΔV _BE is ΔV _BE > 0.
For example, in the previous circuit embodiment, and C1 = 30 pF, for a 10KHz cutoff frequency, if you set the input impedance and 530KΩ, Vcc = 5V, when the 3v bias voltage by the DC bias power supply, the offset voltage [Delta] V _BE Is about 5 mv, which is a size that cannot be ignored depending on the signal handled.
[0009]
The present invention has been made in view of the above circumstances, and provides an AC coupling buffer circuit capable of obtaining an output signal with no offset.
[0010]
[Means for Solving the Problems]
An AC coupling buffer circuit according to the invention of claim 1 is:
A first final stage transistor constituting the final stage of the emitter follower, and a second final stage transistor constituting the final stage of the emitter follower, and a first output signal from the emitter side of the first final stage transistor And an AC coupling buffer circuit configured to obtain a second output signal from the emitter side of the second final stage transistor,
A first current mirror circuit for supplying a predetermined current is connected to the base of the first final stage transistor, the base potential is maintained at a predetermined DC voltage, and AC is connected to the base via a coupling capacitor. The emitter of the first input stage transistor whose collector is grounded so that the input signal is applied is connected,
The base of the second final stage transistor is connected to the first current mirror circuit for supplying a predetermined current, and the second input is grounded to the collector so that the base potential is held at a predetermined DC voltage. The emitter of the stage transistor is connected,
A second current mirror circuit for supplying the same current is connected to the emitters of the first and second final stage transistors,
The first and second current mirror circuits are configured such that current from the same constant current source flows into the first and second current mirror circuits.
[0011]
In such a configuration, the same base bias current is supplied to the bases of the first and second final stage transistors using a current mirror circuit, and the bases of the first final stage transistors are An AC signal is applied via a coupling capacitor, while the emitter of the first input stage transistor is connected. The first input stage transistor has a base at a predetermined voltage and a collector connected to the ground.
The base of the second final stage transistor is connected to the emitter of the second input stage transistor whose collector is grounded. The base potential of the second input stage transistor is the same as the first input stage transistor. Are held at the same predetermined potential.
Therefore, the base potentials of the first and second final stage transistors are the same, and therefore the emitters of the first and second stage transistors are also the same potential. Unlike the conventional case, the differential amplifier is connected to the next stage in an output state having no offset. DC coupling is possible.
[0012]
In particular, the emitter of the first bias setting transistor is connected to the base of the first input stage transistor, and the emitter of the second bias setting transistor is connected to the base of the second input stage transistor, respectively.
The collectors of the first and second bias setting transistors are grounded together, and the bases of the first and second bias setting transistors are connected to each other so that a predetermined DC voltage is applied thereto. It is preferable that the base of the input stage transistor is configured to be held at the same DC potential.
[0013]
In such a configuration, by using the first and second bias setting transistors having the same characteristics, it is possible to easily obtain the same base potential of the first and second input stage transistors. It can be done.
[0014]
The first current mirror circuit includes a diode-connected transistor, and the diode-connected transistor and two transistors whose bases are connected to each other.
The emitter of the diode-connected transistor is connected to a power supply line, and the collector is connected to one end of a constant current source, respectively.
Each of the two transistors has an emitter connected to a power supply line via a resistor, and the collector of one of the two transistors is connected to the base of the first final stage transistor and the other transistor has a collector. The collector is connected to the base of the second final stage transistor, respectively.
The second current mirror circuit includes a diode-connected transistor, and the diode-connected transistor and two transistors whose bases are connected to each other.
The collector of the diode-connected transistor of the second current mirror circuit is connected to the other end of the constant current source, and the emitter is connected to ground,
The two transistors of the second current mirror circuit have their emitters connected to ground, while the collector of one transistor is the emitter of the first final transistor and the collector of the other transistor is the second It is preferable that each of them is connected to the emitter of the final stage transistor.
[0015]
In such a configuration, it is particularly preferable to add a base current compensation transistor to the second current mirror circuit. That is, while connecting the emitter of the base current compensating transistor to the base of the diode-connected transistor of the second current mirror circuit, and connecting the base of the base current compensating transistor to the collector of the diode-connected transistor, It is preferable that the collector of the base current compensating transistor is connected to the power supply line.
As a result, a stable current can be supplied by the current mirror circuit, and the output characteristics can be further stabilized.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIG.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, the circuit configuration will be described. The AC coupling buffer circuit includes a first amplifier circuit unit 30 for obtaining a first output signal from the first output terminal 23, and a second output terminal 24 to the second output terminal 24. The second amplifying circuit unit 31 for obtaining two output signals is roughly divided, and both have the same basic configuration, that is, in other words, have a so-called complementary circuit configuration. ing.
[0017]
That is, the first amplifier circuit section 30 includes an npn-type third transistor (indicated as “Q3” in FIG. 1) 3 as a first final stage transistor, and its collector is the power supply voltage Vcc. Is connected to the first power supply line 23, and the emitter thereof is connected to the first output terminal 23 and a so-called second transistor 9 together with a ninth transistor (indicated as “Q9” in FIG. 1) 9 described later. Is connected to the collector of an npn-type twelfth transistor (denoted as “Q12” in FIG. 1) 12 constituting this current mirror circuit, and this third transistor 3 constitutes a so-called emitter follower. ing.
[0018]
The base of the third transistor 3 includes a pnp-type fourth transistor (FIG. 1) that forms a first current mirror circuit together with an eleventh transistor (described as “Q11” in FIG. 1) 11 described later. 4 is connected to the collector of 4 and is connected to the emitter of a pnp-type second transistor (denoted as “Q2” in FIG. 1) 2.
[0019]
The second transistor 2 as the first input stage transistor has its collector connected to a so-called circuit ground (indicated as “AGND” in FIG. 1), while its base has a coupling capacitor (in FIG. 1). An AC input signal is applied via 15 (denoted as “C1”).
The base of the second transistor 2 is connected to the emitter of a pnp-type first transistor (indicated as “Q1” in FIG. 1) 1 as a first bias setting transistor. The collector of the first transistor 1 is connected to the circuit ground, while the base is connected to the first and second resistors (in FIG. 1) connected in series between the power supply line and the circuit ground. (Respectively denoted as “R1” and “R2”) 16 and 17, respectively, whereby the base of the second transistor 2 is held at a predetermined DC bias voltage as will be described later. It is like that.
[0020]
On the other hand, the pnp-type eleventh transistor 11 constitutes a so-called first current mirror circuit together with the fourth transistor 4 and the pnp-type eighth transistor (indicated as “Q8” in FIG. 1) 8. It has become.
That is, the base and collector of the eleventh transistor 11 are connected to each other and to the bases of the fourth and eighth transistors 4 and 8, while the emitter of the eleventh transistor 11 is connected to the power supply line. It is connected to the.
The fourth transistor 4 has an emitter via a third resistor (indicated as “R3” in FIG. 1) 18, and an eighth transistor 8 has a fourth resistor (in FIG. 1, “R3”). Both are connected to the power supply line via 19).
[0021]
Further, the collector of the eleventh transistor 11 is connected to one end of a constant current source 22, and the other end of the constant current source 22 is connected to the npn-type ninth transistor 9 whose emitter is connected to circuit ground. Connected to the collector.
The ninth torsion star 9 constitutes a second current mirror circuit together with the twelfth transistor 12 and the npn thirteenth transistor (denoted as “Q13” in FIG. 1) 13. The base is connected to the bases of the twelfth and thirteenth transistors 12 and 13, and the emitters of the twelfth and thirteenth transistors 12 and 13 are both connected to circuit ground.
[0022]
The base of the ninth transistor 9 has an emitter of an npn-type tenth transistor (denoted as “Q10” in FIG. 1) 10 as a base current compensating transistor connected to the collector of the ninth transistor 9. The base of the tenth transistor 10 is connected to each other, and the collector of the tenth transistor 10 is connected to the power supply line so that the ninth, twelfth and thirteenth transistors 9, 12, 13 are so-called. The base current is compensated by the tenth transistor 10.
[0023]
On the other hand, the second amplifier circuit section 31 has an npn-type seventh transistor (indicated as “Q7” in FIG. 1) 7 as a second final stage transistor, and its collector is the power supply voltage Vcc. Is connected to the second output terminal 24 and is connected to the collector of the thirteenth transistor 13. The seventh transistor 7 is so-called It constitutes an emitter follower.
[0024]
The base of the seventh transistor 7 is connected to the collector of the pnp-type eighth transistor 8 and the emitter of the pnp-type sixth transistor (denoted as “Q6” in FIG. 1) 2 It is connected.
The sixth transistor 6 as the second input stage transistor has its collector connected to a so-called circuit ground, and has a pnp-type fifth transistor (FIG. 5) as the second bias setting transistor at its base. In FIG. 1, the emitter of 5 is connected, and the base of the fifth transistor 5 is connected to the first connection point between the first and second resistors 16, 17. While connected with the base of transistor 1, the collector is connected to circuit ground.
[0025]
A non-inverting amplifier circuit 32 is DC coupled downstream of the AC coupling buffer circuit having the above configuration. That is, the non-inverting amplifier circuit 32 uses the operational amplifier 25. The first output terminal 23 of the AC coupling buffer circuit is connected to the non-inverting input terminal, and the second output terminal 24 is connected to the inverting input terminal. A resistor (noted as “R5” in FIG. 1) 20 is connected to each other, and a sixth resistor (Feedback) for feedback is connected between the non-inverting input terminal and the output terminal of the operational amplifier 25. In FIG. 1, "R6") 21 is connected.
[0026]
In practice, the AC coupling buffer circuit having the above configuration is preferably formed as a so-called IC. For this reason, the coupling capacitor 15 needs to have a capacitance value that can be incorporated in the IC. For example, specifically, about 10 pF is preferable.
In addition, other components, such as transistors and resistors, are also realized by a known and well-known semiconductor technology for IC.
[0027]
Next, the operation in the above configuration will be described together with an analytical explanation in the main part.
First, the output potentials at the first and second output terminals 23 and 24 will be described as follows.
First, the potential of the first output terminal 23 is derived as follows.
Looking at the base potential of the second transistor 2, the base of the first transistor 1 is connected to the connection point between the first and second resistors 16, 17. Since a so-called divided voltage of the power supply voltage Vcc is generated by the first and second resistors 16 and 17, the base potential of the second transistor 2 is the base potential of the first transistor 1, that is, the above-described divided voltage. The potential becomes higher by the base-emitter voltage V _{BE1 of} the first transistor 1.
[0028]
Since the emitter of the second transistor 2 is connected to the third transistor 3, and the first output terminal 23 is connected to the emitter of the third transistor 3, the first output The potential at the terminal 23 is obtained by adding the base-emitter voltage V _BE2 of the second transistor 2 to the base potential of the second transistor 2, and further subtracting only the base-emitter voltage V _{BE3 of} the third transistor 3. It becomes.
[0029]
On the other hand, the potential of the second output terminal 24 is derived as follows.
First, considering the base potential of the sixth transistor 6, the emitter of the fifth transistor 5 is connected, while the base of the fifth transistor 5 is connected to the first and second transistors together with the first transistor 1. Since the base potential of the sixth transistor 6 is connected to the mutual connection point of the resistors 16 and 17, the base voltage of the sixth transistor 6 is the fifth transistor than the divided voltage by the first and second resistors 16 and 17. The base-emitter voltage V _{BE5 of} 5 is higher.
[0030]
The emitter of the sixth transistor 6 is connected to the base of the seventh transistor 7, and the second output terminal 24 is connected to the emitter of the seventh transistor 7. The potential is obtained by adding the base-emitter voltage V _BE6 of the sixth transistor 6 to the base potential of the sixth transistor 6 and further subtracting the base-emitter voltage V _BE7 of the seventh transistor 7.
[0031]
By the way, if this circuit is made into an IC and each transistor is sufficiently laid out in consideration of so-called pair characteristics, each base-emitter voltage V _BE can be made equal.
Further, in the current mirror circuit constituted by the fourth, eighth, and eleventh transistors 4, 8, 11 that receive current supply from the constant current source 22, the collector currents of the fourth and eighth transistors 4, 8 are equal. Furthermore, in the current mirror circuit composed of the ninth, twelfth and thirteenth transistors 9, 12 and 13 which are also supplied with current from the constant current source 22, the collectors of the twelfth and thirteenth transistors 12 and 13 If the current is equal, the following relationship is established.
[0032]
Base-emitter voltage V _{BE1 of} the first transistor 1 = Base-emitter voltage V _{BE6 of} the sixth transistor ₆
[0033]
Base-emitter voltage V _{BE2 of} the second transistor 2 = Base-emitter voltage V _{BE6 of} the sixth transistor ₆
[0034]
Base-emitter voltage V _{BE3 of} the third transistor 3 = Base-emitter voltage V _{BE7 of} the seventh transistor 7
[0035]
Therefore, the potential of the first output terminal 23 is equal to the potential of the second output terminal 24. Therefore, the AC coupling buffer circuit is offset from the non-inverting amplifier circuit 32 of the next stage. A signal that does not exist can be transmitted by DC coupling.
[0036]
Next, the input impedance of the AC coupling buffer circuit will be described.
First, considering the cut-off frequency fc in the high-pass filter constituted by the coupling capacitor 15 and the input impedance Zin of the AC coupling buffer circuit, the cut-off frequency fc is obtained as follows.
[0037]
fc = 1 / (2π × C1 × Zin)
[0038]
Here, C1 is a capacitance value of the coupling capacitor 15, and Zin is an input impedance when the circuit is viewed from the base side of the second transistor 2 (see FIG. 1).
[0039]
If the frequency band of the AC signal to be transmitted is 10 KHz or more and the capacitance value of the coupling capacitor 15 is a value that can be built in the IC, for example, 10 pF, the input impedance Zin is 1.6 MΩ or more from the above formula. Necessary.
[0040]
The input impedance Zin of the AC coupling buffer circuit, seen from the second base side of the transistor 2 used in the input impedance r ₀₁ and emitter follower as seen from the first emitter side of the transistor 1 used in a grounded-base It is calculated as a so-called parallel value in a state where the input impedance r ₀₂ is connected in parallel.
Here, the input impedance r ₀₁ is the first emitter resistor r _e of the transistor 1, which is below that is derived is based on the so-called small-signal hybrid π-type equivalent circuit for small signal analysis of transistor circuit It can obtain | require by the Formula 1 to do.
[0041]
r ₀₁ = r _e = rπ ₁ / (1 + gm × rπ ₁ ) (Expression 1)
[0042]
Here, gm is conductance, and rπ ₁ is an input resistance viewed from the input side in a small signal hybrid π-type equivalent circuit with a common base, and is expressed as a so-called Thevenin equivalent resistance. Is the value in the transistor 1.
Gm is obtained as gm = Ic / Vi, where Ic is the collector current and Vi is the input voltage. In general, the input resistance rπ is obtained as rπ = β / gm, where β is a small signal current gain.
[0043]
From these conditions, the above Equation 1 is rearranged to obtain the following Equation 2 as an equation for obtaining r ₀₁ .
[0044]
r ₀₁ = rπ ₁ / (1 + β _pnp ) (Formula 2)
[0045]
Here, β _pnp is a small signal current gain of the pnp transistor used in the AC coupling buffer circuit.
For example, when the input impedance r ₀₁ when β _pnp = 65 and I c = 14 nA is obtained from Equation 2, r ₀₁ = 1.807 MΩ.
[0046]
Next, the input impedance r ₀₂ is the input resistance Ri of the second transistor 2 constituting the emitter follower circuit, and is derived on the basis of a so-called small signal hybrid π-type equivalent circuit as in the case of r ₀₁ above. The following formula can be obtained.
[0047]
r ₀₂ = R i = rπ + R _L (1 + β) (Formula 3)
[0048]
Here, R _L is a load resistance. In this AC coupling buffer circuit, the input impedance r ₀₃ viewed from the base side of the third transistor 3 and the input impedance r ₀₄ viewed from the collector side of the fourth transistor 3 are used. It is expressed as a so-called parallel value.
When rπ is rewritten to rπ ₂ representing the input resistance of the second transistor 2 and the above equation 3 is rearranged in consideration of the above-described conditions, the following equation 4 is obtained.
[0049]
r ₀₂ = rπ ₂ + {(r ₀₃ × r ₀₄ ) / (r ₀₃ + r ₀₄ )} (1 + β _pnp ) (Formula 4)
[0050]
Here, r ₀₃ can be determined as approximately r ₀₃ ≈β (V _A / Ic 3), and V _A is a so-called Early voltage.
For example, the small signal current gain β _npn of the npn transistor in this AC coupled buffer circuit is set to β _npn = 110 and V _{A is set} to V _A = 42v. If the output current Is of the constant current source 22 is 8 μA, the collector current Ic3 of the third transistor 3 is substantially equal to the emitter current, and this emitter current is the twelfth transistor 12 constituting the current mirror circuit. Therefore, Ic3 = Is = 8 μA.
From these conditions, when r _{03 is obtained} by the above approximate expression, r ₀₃ = 590 MΩ is obtained.
[0051]
On the other hand, the input impedance r ₀₄ is obtained as the output resistance Ro at the emitter ground of the fourth transistor 4 in which the third resistor 18 as a negative feedback resistor is provided on the emitter side.
That is, it is obtained as Ro = V _A / Ic {1 + gm (rπ × R _E ) / (rπ + R _E )}.
Here, R _E is the value of the resistor connected to the emitter, and in the case of the fourth transistor 4, is the resistance value of the third resistor 18 (for example, 50 KΩ).
If the pnp transistor V _A = 10 V and the collector current Ic of the fourth transistor 4 is 1 μA, the input impedance r ₀₄ can be calculated as r ₀₄ = 29 MΩ by using the above-described expression for the output resistance Ro. It is done.
[0052]
Using these numerical values, when the input impedance r ₀₂ is obtained from Equation 4, r ₀₂ = 1.65 MΩ + {(590 MΩ × 29 MΩ) / (590 MΩ + 29 MΩ)} (1 + 65) = 1.83 MΩ.
Thus, as already mentioned, the input impedance Zin is the so-called parallel resistance value of r ₀₁ and r _02, are those obtained as _{Zin = (r 01 × r 02} ) / (r 01 + r 02), as described above If Zin is calculated by substituting the specific value obtained in this way, Zin = 1.805 MΩ.
[0053]
Here, when the cut-off frequency fc of the high-pass filter composed of the coupling capacitor 15 and Zin is obtained at Zin = 1.805 MΩ, fc = 8.84 KHz.
This sufficiently satisfies the previously assumed condition that the frequency band of the AC signal to be transmitted is 10 KHz or more.
That is, with this AC coupling buffer circuit, an AC signal of 10 KHz or higher is transmitted to the non-inverting amplifier circuit 32 at the next stage by DC coupling without offset.
[0054]
In the above-described circuit, a so-called bipolar transistor is used. However, other transistors, such as an FET, can be similarly applied.
[0055]
【The invention's effect】
As described above, according to the present invention, the collector current of the two transistors constituting the current mirror circuit for supplying the base bias current of the two final stage transistors is configured not to cause an error. Thus, unlike the conventional case, the base potentials of the two final stage transistors are kept the same, and the emitter potentials are the same, so that an AC coupling buffer circuit that does not cause an offset in the output from each final stage transistor is provided. Can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit configuration example according to an embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a conventional circuit configuration.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Coupling capacitor 23 ... 1st output terminal 24 ... 2nd output terminal 30 ... 1st amplifier circuit part 31 ... 2nd amplifier circuit part 32 ... Non-inverting amplifier circuit

Claims (3)

A first final stage transistor constituting the final stage of the emitter follower, and a second final stage transistor constituting the final stage of the emitter follower, and a first output signal from the emitter side of the first final stage transistor And an AC coupling buffer circuit configured to obtain a second output signal from the emitter side of the second final stage transistor,
A first current mirror circuit for supplying a predetermined current is connected to the base of the first final stage transistor, the base potential is maintained at a predetermined DC voltage, and AC is supplied to the base via a coupling capacitor. The emitter of the first input stage transistor whose collector is grounded so that the input signal is applied is connected,
The base of the second final stage transistor is connected to the first current mirror circuit for supplying a predetermined current, and the second input is grounded to the collector so that the base potential is held at a predetermined DC voltage. The emitter of the stage transistor is connected,
A second current mirror circuit for supplying the same current is connected to the emitters of the first and second final stage transistors,
The AC coupling buffer circuit is characterized in that the first and second current mirror circuits are configured such that currents from the same constant current source flow in. The emitter of the first bias setting transistor is connected to the base of the first input stage transistor, and the emitter of the second bias setting transistor is connected to the base of the second input stage transistor, respectively.
The collectors of the first and second bias setting transistors are grounded together, and the bases of the first and second bias setting transistors are connected to each other so that a predetermined DC voltage is applied thereto. 2. The AC coupling buffer circuit according to claim 1, wherein the base of the input stage transistor is configured to be held at the same DC potential. The first current mirror circuit includes a diode-connected transistor, and the diode-connected transistor and two transistors whose bases are connected to each other.
The emitter of the diode-connected transistor is connected to a power supply line, and the collector is connected to one end of a constant current source, respectively.
Each of the two transistors has an emitter connected to a power supply line via a resistor, and the collector of one of the two transistors is connected to the base of the first final stage transistor and the other transistor has a collector. The collector is connected to the base of the second final stage transistor, respectively.
The second current mirror circuit includes a diode-connected transistor, and the diode-connected transistor and two transistors whose bases are connected to each other.
The collector of the diode-connected transistor of the second current mirror circuit is connected to the other end of the constant current source, and the emitter is connected to ground,
The two transistors of the second current mirror circuit have their emitters connected to ground, while the collector of one transistor is the emitter of the first final transistor and the collector of the other transistor is the second 3. The AC coupling buffer circuit according to claim 1, wherein the AC coupling buffer circuit is connected to an emitter of each of said final stage transistors.

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