JP3758158B2 - Disk evaluation device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk evaluation apparatus for performing quality evaluation of a recording disk.
[0002]
[Prior art]
Currently, the quality of a manufactured recording disk is evaluated using jitter generated in a read signal read from the recording disk.
However, when the recording density of the recording information recorded on the recording disk is increased, the S / N ratio of the high frequency component in the read signal is lowered and it is easily affected by intersymbol interference. Therefore, a jitter larger than the original jitter is detected from the recording disk on which high density recording has been performed, and there has been a problem that the recording disk cannot be evaluated correctly.
[0003]
[Problems to be solved by the invention]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a disk evaluation apparatus capable of performing highly reliable disk evaluation on a recording disk recorded with high density. .
[0004]
[Means for Solving the Problems]
A disk evaluation apparatus according to the present invention is a disk evaluation apparatus for evaluating a recording disk on which a modulation signal obtained by performing predetermined modulation processing on information data according to a channel clock is recorded. Information reading means for reading the modulated signal to obtain a read signal, an A / D converter for sampling the read signal at a clock timing having the same frequency as the channel clock to obtain a read sample value series, and the reading Amplitude limiting means for obtaining an amplitude limited read sample value series in which each sample value of the sample value series is limited to a predetermined amplitude limit value or less, and an interval between the maximum sample value and the minimum sample value in the amplitude limit read sample value series Increase the maximum sample value and the minimum sample value when is equal to a predetermined high-frequency interval. A high-frequency emphasis filter that obtains a high-frequency emphasized read sample value sequence that has been high-frequency emphasized, and converts the high-frequency emphasized read sample value sequence into an analog high-frequency emphasized read signal at the same clock timing as the channel clock. A D / A converter that performs extraction, a low-pass filter that extracts only a component having a frequency equal to or lower than a predetermined cutoff frequency in the high-frequency emphasized read signal, and obtains this as an evaluation read signal; A binarization circuit for obtaining a binarized signal,
The jitter of the binarized signal is used as a disk evaluation value.
[0005]
DETAILED DESCRIPTION OF THE INVENTION
Examples of the present invention will be described below.
FIG. 1 is a diagram showing the configuration of a disk evaluation apparatus according to the present invention.
In Figure 1, the pickup 1, to obtain a photoelectric conversion to read signal R _RF reflected light when irradiated with the recording surface to read beam light evaluation subject to the recording disk 3 to rotate by a spindle motor 2. Note that a modulation signal obtained by subjecting the information data to RLL (1, 7) modulation processing according to a channel clock of 66 MHz, for example, is recorded in advance on the recording disk 3. The high pass filter 5 supplies the read signal R _{HC from} which the low frequency component of the read signal R _RF has been removed to the pre-low pass filter 6. The pre-low-pass filter 6 converts the read signal R _{LHC obtained} by removing a high frequency component of 1/2 or more of the sampling frequency from the read signal R _HC to A / D in order to prevent aliasing during the sampling process by the A / D converter 7. This is supplied to the converter 7. The A / D converter 7 supplies a read sample value series RS obtained by sampling the read signal _RLHC to the pre-equalizer 9 in accordance with a sampling clock SK supplied from a PLL (phase locked loop) circuit 8. The sampling clock SK has the same frequency as the channel clock. The pre-equalizer 9 supplies, to the limit equalizer 10, the read sample value series RS _{C from} which the intersymbol interference based on the transmission characteristics of the information reading system including the pickup 1 and the recording disk 3 is removed from the read sample value series RS. . The pre-equalizer 9 is a transversal filter having tap coefficients of [k, 1, 1, k], for example.
[0006]
The limit equalizer 10 converts the high-frequency emphasized read sample value series RS _H obtained by performing high-frequency emphasis processing on the read sample value series RS _C without increasing intersymbol interference, into the PLL circuit 8 and the D / D The A converter 11 is supplied.
FIG. 2 is a diagram showing an internal configuration of the limit equalizer 10.
As shown in FIG. 2, the limit equalizer 10 includes an interpolation filter 41, an amplitude limiting circuit 42, a high frequency emphasis filter 43, and an adder 44.
[0007]
The interpolation filter 41 obtains when the read signal read from the recording disk 3 is sampled at an intermediate timing of the clock timing by the sampling clock SK by performing an interpolation calculation process on the read sample value series RS _C. Find the sample value series that would be Then, the interpolation filter 41 obtains an interpolated read sample value series RS _P obtained by interpolating the obtained sample value series in the read sample value series RS _C and supplies it to the amplitude limiting circuit 42.
[0008]
Amplitude limiting circuit 42 supplies such interpolated read sample value sequence RS _P read amplitude limit obtained by the amplitude a predetermined amplitude limit value T _h and -T _h sample value series RS _LIM to high-frequency enhancement filter 43 To do. That is, the amplitude limiting circuit 42, when the read sample values in the interpolated read sample value sequence RS _P is within the range of the amplitude limit value -T _h through T _h is directly the interpolated read sample value sequence RS _P The amplitude limited read sample value series RS _LIM is supplied to the high frequency enhancement filter 43. Further, in the case where each of the read sample values of the interpolated read sample value sequence RS _P is greater than the amplitude limit value T _h is high frequency emphasis series of amplitude limitation value T _h as the amplitude limited read sample value sequence RS _LIM The filter 43 is supplied. On the other hand, when each read sample value of the interpolated read sample value series RS _P is smaller than the amplitude limit value −T _h , this amplitude limit value −T _h series is set as the amplitude limit read sample value series RS _LIM. This is supplied to the region enhancement filter 43. At this time, each of the amplitude limit values T _h and −T _h is used when the interval between the maximum sample value and the minimum sample value in the interpolated read sample value series RS _P corresponds to a predetermined high frequency interval, that is, RLL. When corresponding to the shortest run length 2T in (1, 7) modulation, each sample value is set to a value that does not cause the amplitude limitation as described above. That is, the interpolated read sample value series RS _P corresponding to the run length 2T passes through the amplitude limit circuit 42 as it is and is output as an amplitude limit read sample value series RS _LIM .
[0009]
The high-frequency emphasis filter 43 generates a high-frequency read sample value sequence in which only the sample sequence corresponding to the shortest run length 2T in the amplitude-limited read sample value sequence RS _LIM is increased, and this is supplied to the adder 44. Supply. The high frequency emphasis filter 43 is a transversal filter having tap coefficients [−k, k, k, −k], for example. With this configuration, the high-frequency emphasis filter 43 has the time points D _−1.5 , D _−0.5 , D _0.5 , D in the amplitude limited read sample value series RS _LIM as shown in FIG. 3 (a) or FIG. 3 (b), for example. and it obtains the value at the time D ₀ based on the value in D _1.5 respectively, and sequentially outputs this as a high-frequency read sample value RS _HIG. That means
RS _HIG = (− k) · Y _−1.5 + k · Y _−0.5 + k · Y _0.5 + (− k) · Y _1.5
Y _-1.5: RS amplitude limited read sample value at the time D _-1.5 in the _LIM Y _-0.5: RS amplitude at the time D _-0.5 in the _LIM limited read sample value Y _0.5: at the time D _0.5 in the RS _LIM Amplitude limited read sample value Y _1.5 : This is the amplitude limited read sample value at time point D _1.5 during RS _LIM .
[0010]
At this time, as shown in FIG. 3A, the amplitude limited read sample values at the time points D _-1.5 and D _-0.5 (or the time points D _0.5 and D _1.5 ) corresponding to the run length 2T are substantially the same. Become. On the other hand, the amplitude limited read sample value of run length at D _-1.5 and point D _-0.5 (or point D _0.5 and D _1.5) each in each case 3T and 4T as shown in FIG. 3 (b), the amplitude limit Both are set to the amplitude limit value −T _h (or T _h ) by the operation of the circuit 42. Therefore, even if the value of the tap coefficient k of the high-frequency emphasis filter 43 is increased so as to strongly apply high-frequency emphasis, the high-frequency read sample value obtained at the zero crossing point D ₀ is maintained at a constant value, so that intersymbol interference Does not occur.
[0011]
The adder 44 adds the high frequency read sample value series RS _HIG and the read sample value series RS _C supplied from the pre-equalizer 9 and outputs the addition result as a high frequency emphasized read sample value series RS _H. To do.
With the configuration as described above, the limit equalizer 10 is used when the interval between the maximum sample value and the minimum sample value in the read sample value series RS _C corresponds to a predetermined high-frequency interval, that is, RLL (1, 7). When corresponding to run length 2T in modulation, these sample values are increased to perform high frequency emphasis.
[0012]
FIG. 4 shows a spectrum (shown by a solid line) of the high frequency emphasized read sample value series RS _H obtained by performing high frequency emphasis processing by the limit equalizer 10 and an equalizer that does not perform such high frequency emphasis. FIG. 6 is a diagram showing a comparison of a spectrum (indicated by a broken line) of a read sample value series obtained. As shown in FIG. 4, the output of limit equalizer 10 (shown by a solid line) includes harmonic components that are not found in the output of an equalizer that does not perform high-frequency emphasis (shown by a broken line).
[0013]
The PLL circuit 8 generates a clock signal having the same frequency (66 MHz) as the channel clock by correcting the phase error generated in the high frequency emphasized read sample value series RS _H, and uses this as the sampling clock SK. The data is supplied to the A / D converter 7, the D / A converter 11, and the jitter measurement circuit 30. The D / A converter 11 converts the high-frequency emphasized read sample value series RS _H into an analog signal at a timing corresponding to the sampling clock SK, and supplies this to the post-low pass filter 12 as a high-frequency emphasized read signal RD. .
[0014]
The post-low-pass filter 12 extracts only the baseband component in the high frequency emphasized read sample value series RS _H by removing the aliasing component (described later) existing in the high frequency emphasized read signal RD. The evaluation read signal RR is supplied to the binarization circuit 13.
Hereinafter, detailed operation of the post-low pass filter 12 will be described.
[0015]
FIG. 5 is a diagram showing the frequency band of the high-frequency emphasized read signal RD input to the post-low pass filter 12.
The high-frequency emphasized read signal RD is obtained by converting the high-frequency emphasized read sample value series RS _H into an analog signal at the timing of the sampling clock SK. Therefore, in the high frequency emphasized read signal RD, as shown in FIG. 5, the baseband component of the high frequency emphasized read sample value series RS _H exists in a band of 1/2 or less of the sampling frequency fs (66 MHz), The folded component exists in the band of (1/2) · fs or more. Therefore, the post-low-pass filter 12 removes the aliasing component of (1/2) · fs or more in the high-frequency emphasized read sample value series RS _{H with a} cutoff characteristic as shown by the broken line in FIG. Accordingly, the post-low pass filter 12 extracts only the baseband component of the high frequency emphasized read sample value series RS _H from the high frequency emphasized read signal RD, and outputs this as the evaluation read signal RR.
[0016]
FIG. 6 is a diagram illustrating an example of waveforms of the high-frequency emphasized read signal RD input to the post-low pass filter 12 and the evaluation read signal RR output from the post-low pass filter 12.
As shown in FIG. 6, since the high-frequency emphasized read signal RD is obtained by the D / A converter 11, it becomes a stepped waveform due to its 0th-order hold characteristic and is not suitable for jitter measurement. . Therefore, the post-low pass filter 12 generates the evaluation read signal RR having a smooth waveform as shown in FIG. 6 from which the aliasing component of the high frequency emphasized read sample value series RS _H existing in the high frequency emphasized read signal RD is removed. To do.
[0017]
FIG. 7 is a diagram showing a correspondence relationship between the cutoff frequency of the post-low pass filter 12 and the jitter amount when the information data is RLL (1, 7) modulated by the channel clock 66 MHz and recorded on the recording disk 3. It is.
In the example shown in FIG. 7, the numerical aperture NA and the wavelength λ of the objective lens (not shown) mounted on the pickup 1 are as follows.
[0018]
NA = 0.85
Wavelength λ = 405 nm
At this time, when the limit equalizer 10 is not used (shown by a broken line), if the cutoff frequency of the post low pass filter 12 is set to ½ of the frequency of the channel clock, that is, less than 33 MHz, jitter There was no change. However, when the limit equalizer 10 as described above is employed, if the cutoff frequency of the post-low pass filter 12 is set to be higher than 30 MHz, the high-frequency emphasized read sample value series RS _H as shown in FIG. The aliasing component cannot be sufficiently attenuated, and the amount of jitter increases as shown in FIG. Furthermore, if the cut-off frequency of the post-low pass filter 12 is set to be smaller than 30 MHz, harmonic components in the high-frequency emphasized read sample value series RS _{H as} shown by the solid line in FIG. 4 are attenuated. As shown, the amount of jitter increases.
[0019]
That is, the jitter amount is minimized when the cutoff frequency of the post-low pass filter 12 is around 30 MHz. Furthermore, if the cutoff frequency of the post-low pass filter 12 is in the vicinity of 30 MHz, even if the cutoff frequency of the post-low pass filter 12 slightly fluctuates, the fluctuation amount of the jitter amount with respect to the fluctuation is small as shown in FIG. It is.
[0020]
As described above, when the limit equalizer 10 as described above is used in evaluating the recording disk 3 in which the information data is RLL (1, 7) modulated and recorded with the channel clock of 66 MHz, the cutoff frequency of the post-low pass filter 12 is used. Is preferably set in the vicinity of 30 MHz. Here, the vicinity of 30 MHz of the cut-off frequency includes ± 10% of the fluctuation amount of the cut-off frequency that is allowed when considering the fluctuation of the jitter amount within 0.2%. 33 MHz. When evaluating the disk at double speed (channel clock frequency 132 MHz), it is preferable to set the cut-off frequency of the post-low pass filter 12 in the vicinity of 60 MHz.
[0021]
In short, when the frequency of the channel clock is fclk [MHz] and the cutoff frequency of the post-low pass filter 12 is fc [MHz], the cutoff frequency of the post-low pass filter 12 is set so that fc / fclk is approximately 5/11. What is necessary is just to determine fc.
Furthermore, when considering the variation of the cut-off frequency ± 10%,
9/22 ≦ fc / fclk ≦ 1/2
The cut-off frequency fc of the post-low pass filter 12 may be determined within a range that satisfies the above.
[0022]
The binarization circuit 13 generates a binary signal having a predetermined high voltage when the evaluation read signal RR supplied from the post-low pass filter 12 is larger than a predetermined threshold value, and a predetermined low voltage when the evaluation read signal RR is smaller, This is supplied to the jitter measurement circuit 30. The jitter measurement circuit 30 measures the variation in the time difference between the edge timing of the binary signal and the clock timing of the reference clock signal, and outputs the measurement result as a disk evaluation value.
[0023]
As described above, the jitter measurement circuit 30 performs high-frequency emphasis only on the read sample value series corresponding to the shortest run length without causing intersymbol interference by the limit equalizer 10, and D / A conversion by the post-low pass filter 12. A read signal from which the aliasing component generated at times is removed is a jitter measurement target.
[0024]
【The invention's effect】
Therefore, according to the disk evaluation apparatus of the present invention, it is possible to perform highly reliable disk evaluation even if the recording density of the recording information recorded on the recording disk is high. In addition, when a limit equalizer is applied to a disk evaluation device, the jitter improvement effect of the limit equalizer can be sufficiently exhibited by setting the cutoff frequency of the post-low pass filter, which has not been considered in the past, as in the present invention. Is possible. Furthermore, even if the cut-off frequency of the post-low-pass filter varies somewhat, the jitter variation is very small, so that it is possible to perform highly reliable jitter evaluation without variations between the disk evaluation apparatuses.
[Brief description of the drawings]
FIG. 1 is a diagram showing the configuration of a disk evaluation apparatus according to the present invention.
FIG. 2 is a diagram showing an internal configuration of a limit equalizer 10;
FIG. 3 is a diagram illustrating an example of an interpolated read sample value series RS _P and an amplitude limited read sample value series RS _LIM ;
FIG. 4 is a diagram showing a comparison between an output of a limit equalizer 10 and an output of an equalizer that does not perform high-frequency emphasis.
FIG. 5 is a diagram illustrating a frequency band of a high-frequency emphasized read signal RD input to the post-low pass filter 12;
6 is a diagram illustrating an example of waveforms of a high-frequency emphasized read signal RD input to the post-low-pass filter 12 and an evaluation read signal RR output from the post-low-pass filter 12. FIG.
FIG. 7 is a diagram showing a correspondence relationship between the cutoff frequency of the post-low-pass filter 12 and the jitter amount when information data is RLL (1, 7) modulated with a channel clock of 66 MHz and recorded on the recording disk 3; It is.
[Explanation of main part codes]
3 Recording disk 10 Limit equalizer 11 D / A converter 12 Post low pass filter 30 Jitter measurement circuit

Claims (5)

A disk evaluation device for evaluating a recording disk on which a modulation signal obtained by performing a predetermined modulation process on information data according to a channel clock is recorded,
Information reading means for reading the modulated signal from the recording disk to obtain a read signal;
An A / D converter that samples the read signal at a clock timing of the same frequency as the channel clock to obtain a read sample value series;
Amplitude limiting means for obtaining an amplitude limited read sample value series in which each sample value of the read sample value series is limited to a predetermined amplitude limit value or less;
When the interval between the maximum sample value and the minimum sample value in the amplitude limited read sample value series corresponds to a predetermined high frequency interval, the maximum sample value and the minimum sample value are increased to emphasize the high frequency. A high frequency emphasis filter for obtaining a high frequency emphasis read sample value series;
A D / A converter that converts the high frequency emphasized read sample value series into an analog high frequency emphasized read signal at a clock timing of the same frequency as the channel clock;
A low-pass filter that extracts only a component below a predetermined cutoff frequency in the high-frequency emphasized read signal and obtains it as an evaluation read signal;
A binarization circuit that obtains a binarized signal obtained by binarizing the evaluation read signal with a predetermined threshold value,
A disk evaluation apparatus characterized in that jitter of the binarized signal is used as a disk evaluation value. When the frequency of the channel clock is fclk [MHz] and the cutoff frequency is fc [MHz],
9/22 ≦ fc / fclk ≦ 1/2
The disk evaluation apparatus according to claim 1, wherein: 2. The disk evaluation apparatus according to claim 1, wherein the modulation processing is RLL (1, 7) modulation processing. The amplitude limit value is larger than the maximum sample value when the interval between the maximum sample value and the minimum sample value in the amplitude limit read sample value series corresponds to a predetermined high frequency interval. The disk evaluation apparatus according to claim 1. 2. The disk evaluation apparatus according to claim 1, wherein the high-frequency emphasis filter is a transversal filter having tap coefficients of [−k, k, k, −k].

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