JP2002074844A - Information reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably reduce data errors at the time of reproducing binary data from an analog signal when information on a recording medium is reproduced. SOLUTION: When the information recorded on an optical disk 1 is reproduced in this information reproducing apparatus, an A/D converter 15 samples a reproduced signal in synchronization with a clock signal outputted from a PLL(phase-locked loop) 13 and converts it into digital values, a FIR(finite impulse response filter) performs the partial response equalization of the digital values to output a signal, a counter 22 counts the time length of the output signal, a Vref generating circuit 19 makes a value in which 1 is added to the count value to be the time length of the reproduced signal and increases or decreases a slice level Vref by a value in which the time length is multiplied by a prescribed coefficient, and a comparator 21 compares the Vref with the output signal of the FIR 16 and outputs the binary data on the basis of the comparison result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a CD-R / R
An optical disk recording / reproducing apparatus for recording and reproducing information by irradiating a recording medium such as W, DVD-RW and DVD-RAM with a light beam, CD-ROM, CD-R /
Information for converting an analog signal reproduced from a recording medium into a digital signal in a dedicated optical disk reproduction apparatus that only reproduces information by irradiating a recording medium such as RW, DVD-RW and DVD-RAM with a light beam. It relates to a playback device.

[0002]

2. Description of the Related Art An optical disk as a recording medium includes a ROM.
There is an optical disc dedicated to reproduction of information called "RAM" and a recordable optical disc called RAM or RW in which information can be written.

FIG. 12 is an explanatory diagram showing a state after data recording on a recordable optical disk on which information can be written. As shown in the figure, when the write data is "1" on the track 31 on the optical disk, the recording film undergoes a phase change due to the irradiation of the strong laser beam, and a low reflection area called a mark 32 is formed. An area without the mark 32 corresponding to data “0” is called a space 33 and is an area having a high reflectance.

At the time of data reproduction, the weak laser beam spot 30 moves along the track 31 and reads data depending on the amount of reflected light. The lengths of the mark 32 and the space 33 are encoded so as to take nine discrete values from 3T to 11T, where T is the period of the read clock.

On the other hand, the ROM is the same as the above-mentioned optical disc except that the mark described above is a depression called a pit and information cannot be written.

FIG. 13 is a diagram showing an example of the configuration of an optical disk reproducing apparatus provided with a conventional information reproducing apparatus. The spindle motor 6 rotates the optical disc 1 at a predetermined rotation speed.

[0007] Laser light L emitted from a semiconductor laser light source in the pickup 2 is reflected by the optical disk 1 and is converted into an electric signal by a four-division light receiving element (not shown) in the pickup 2 and is divided into four signals A to D. Two signals are output. Thereafter, after passing through the I / V amplifier 3, the analog arithmetic unit 4 performs analog addition of (A + B + C + D), and outputs the result as a reproduction signal: RF.

The analog arithmetic unit 4 outputs another two signals representing a track error signal: TE and a focus error signal: FE.
Two analog operation result signals are output to the servo control circuit 5.

[0009] After removing the DC component of the reproduction signal: RF output from the analog arithmetic unit 4 by the AC coupling 7 using the capacitor P, the analog waveform equalizer (analog EQ) 11
Then, the gain is adjusted with respect to the frequency, and then binarized by comparing with the reference voltage: Vref fixed by the slice circuit 12.

Thereafter, the PLL 13 extracts a synchronous clock component from the reproduced signal. Binarized data is extracted from the reproduced signal binarized by the sampling circuit 14 using the falling edge of the extracted synchronous clock.

Here, a single comparator is provided as the slice circuit 12, and a reference voltage of a fixed voltage level: Vre
A method of binarizing by comparing with f is usually used.

The binarized data output from the reproduction circuit 10 is subjected to 8/16 demodulation, error detection and error correction by an external 8/16 demodulation circuit and an error detection / correction circuit (not shown). It is.

The above error detection / correction means 37,856
A byte is taken as one block, and a 4,832 byte redundant code is recorded on the optical disk together with 33,024 bytes of data in the block. At the time of reproduction, an operation is performed by combining the reproduced data with the redundant code. Error detection and correction.

FIG. 14 is a diagram showing an example of a configuration different from the reproducing circuit shown in FIG. As shown in FIG. 14, after the reproduction signal: RF is waveform-equalized to some extent by the analog EQ 11, it is input to the A / D converter 15 and the slice circuit 12, and the slice circuit 12 binarizes it. P
In LL13, a synchronous clock component is extracted from the reproduction signal: RF. On the other hand, the A / D converter 15 samples the reproduction signal: RF based on the clock signal from the PLL 13, converts the RF signal into a digital value, and outputs the digital value.

Next, the signal output from the A / D converter 15 is input to a filter circuit (FIR) 16. FIR1
Reference numeral 6 denotes a finite impulse response type filter circuit for performing partial response (PR) equalization. Hereinafter, P
A description will be given by taking R (a1, a2, a3, a4) as an example.

FIG. 15 is a diagram showing the internal configuration of the FIR 16 which is a finite impulse response type filter circuit. The FIR 16 performs PR (a1, a2, a3, a4) equalization, and includes delay circuits 40a to 40d for delaying 1T time data, and delay circuits 40a to 40d.
Multiplication circuits 41a-41d for multiplying the outputs from the multiplication by coefficients a1-a4, respectively, and multiplication circuits 41a-41d
And an addition circuit 42 for adding and outputting the signals of the four multiplication results according to.

The impulse response h (t) corresponding to such a filter circuit of the FIR 16 can be expressed by the following equations (1) and (2). However, in Equation 1, k = -1,0,
1, 2, and in Equation 2, k ≠ −1, 0, 1, 2.

[0018]

(Equation 1)

[0019]

(Equation 2)

The above-mentioned a1, a2, a3 and a4 are multiplication coefficients of each tap of this filter, and their values are set so that the amplitude of the output signal is equalized as much as possible with respect to the input signal in the predetermined frequency band. Is selected. Then, the digital comparator 17 in FIG. 14 performs binarization by comparing with a reference value.

In still another conventional example, a Viterbi decoding circuit is provided in place of the digital comparator 17 to perform binarization. What is Viterbi decoding?
As disclosed in Japanese Patent Laid-Open Publication No. 0, assuming an amplitude expectation value of a reproduction signal and a plurality of states corresponding thereto, fixed binary data is assigned to each state, and a reproduction signal is assumed for each assumed state transition. This method accumulates the difference between the amplitude value and the expected amplitude value, and reproduces data as a state transition sequence (path) having the smallest absolute value of the accumulated value as the most likely path.

[0022]

However, in the above-mentioned conventional information reproducing apparatus, even if the waveform equalization by the FIR 16 is performed, since the amplitude of the space and mark of 3T and 4T length is small, for example, the high density In an optical disk capable of writing data of 4 GB or more, the signal amplitude fluctuates due to fluctuations in various conditions at the time of recording (for example, conditions such as a laser power and a heat diffusion speed associated with mark generation). And the amplitude fluctuation of the mark is disadvantageous.

FIG. 16 is a diagram showing a sampled reproduced signal after partial response equalization. Here, the amplitude fluctuation of a space having a length of 3T is shown.
Spaces are indicated by black circles.

As described above, since the amplitude that should be positive with respect to the slice level (the black circle below the slice level) is negative, erroneous reproduction is performed if binarization is performed at a fixed slice level. There was a problem of becoming. The point where the reproduced signal crosses the slice level is called an edge, and the above-described problem is particularly called an edge shift.

The reproducing method using the Viterbi decoding circuit is effective in reducing the error rate when white noise is present in the reproduced signal. There was a problem that it was not effective.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to remarkably reduce data errors in reproducing binary data from an analog signal when reproducing information on a recording medium. I do.

[0027]

According to the present invention, there is provided an information reproducing apparatus for reproducing information recorded on a recording medium, comprising a clock having an arbitrary frequency based on an external signal. Clock signal output means for outputting a signal, analog-to-digital conversion means for converting a reproduced signal of an analog value synchronized with the clock signal output from the means into a digital signal and outputting the digital signal, and a digital signal output from the means Digital finite impulse response type filter means for equalizing the waveform and outputting the result, counting means for counting the time length of the digital signal output from the means, and 1 for the count value counted by the means.
Is used as the time length of the reproduced signal, and a slice level generating means for generating a slice level signal which is increased or decreased by a value obtained by multiplying the time length by a predetermined coefficient; and a slice level signal generated by the means. Provided is an information reproducing apparatus including comparison means for comparing a digital signal output from a digital finite impulse response type filter means and binary data output means for outputting binary data based on a comparison result by the means. I do.

An information reproducing apparatus for reproducing information recorded on a recording medium, comprising: clock signal output means for outputting a clock signal of an arbitrary frequency based on an external signal; Analog-to-digital converting means for converting a reproduced signal of an analog value synchronized with the clock signal into a digital signal and outputting the digital signal, counting means for counting the time length of the digital signal output from the means, and counting by the means. A slice level generating means for generating a slice level signal obtained by adding or subtracting 1 to the counted value as a time length of the reproduced signal, and increasing or decreasing the sum of the digital signals for each time length by a predetermined coefficient. , The slice level signal generated by the means and the digital signal output from the analog / digital conversion means. Comparing means for comparing, also provides the information reproducing apparatus provided with a binary data output means for outputting binary data based on the comparison result by the means.

Further, in the information reproducing apparatus as described above, a detecting means for detecting a mark and a space having a length less than a specified length from the binary data output from the binary data output means is provided. More preferably, when the detection means detects one or more errors during a predetermined period, the predetermined coefficient is increased by a predetermined constant.

Further, an information reproducing apparatus for reproducing information recorded on a recording medium, comprising: a clock signal output means for outputting a clock signal of an arbitrary frequency based on an external signal; Analog finite impulse response type filter means for equalizing and outputting a signal, and counting the time length of the analog signal output from the analog finite impulse response type filter means based on the clock signal output from the clock signal output means. And a slice level for generating a slice level signal obtained by increasing or decreasing a value obtained by adding 1 to a count value counted by the means as a time length of the reproduction signal and multiplying the time length by a predetermined coefficient. Generating means; a slice level signal generated by the generating means; Comparing means for comparing the analog signal output from the pulse response filter means, 2 for outputting binary data based on the comparison result by the means
An information reproducing apparatus provided with a quantified data output unit is also provided.

[0031]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a reproducing circuit of an optical disc reproducing apparatus according to an embodiment of the present invention. This reproducing circuit realizes a decoding method that is effective against edge shifts, noting that one of the main causes of the edge shift of the reproduced signal is a change in the DC level.

In FIG. 1, a filter circuit (FIR) 1
6 is the same as the above-mentioned conventional reproducing circuit up to the point where the partial response is equalized. However, the digital value of the reproducing signal of the FIR 16 and the sampling clock extracted from the reproducing signal by the PLL 13 are converted into a binarizing circuit 18 and a Vref generating circuit. 19 are input to both.

In the Vref generation circuit 19, the length of the space and the mark is measured by the counter 22, the DC fluctuation amount of the reproduction signal is estimated, and the slice level: Vref is updated in accordance with the DC fluctuation amount.

The binarizing circuit 18 outputs a reproduced signal amplitude value: Y
(T) and Vref output from the Vref generation circuit 19
And binarization is performed. In the reproducing circuit of this embodiment, an expected amplitude value is assumed for the reproduced signal after the partial response equalization by the FIR 16.

FIG. 2 is a diagram showing a relationship between a reproduced signal after partial response equalization and an expected amplitude, and shows a state transition and binarized data of an operation result of the reproducing circuit shown in FIG. . In the figure, numerals (0, 3, 7, 10) represent the expected amplitude value E (t), and numeral 5 represents the conventional slice level: Vr.
The level corresponding to ef0 is shown.

Next, the operation of the reproducing circuit will be described with reference to the state transition diagram of FIG. In the reproducing circuit of this embodiment, six states S corresponding to the expected amplitude value E (t) are set.
Assume 0, S1, S2, S3, S4, S5.

The output of the FIR 16 is represented by the reproduced signal amplitude value Y
(T), and the state determination circuit 2 in the Vref generation circuit 19
3, the result of subtraction from the value 1T before every clock (Y (t))
−Y (t−1)) is compared with the expected variable at the time of transition between states other than between S1 and S2 and between S4 and S5 to determine transition between states.

The transition between S1 and S2 and the transition between S4 and S5 are determined by comparing with the slice level: Vref updated corresponding to the change in the DC level. The above six states output the determined values as the binarized output b (t).

In FIG. 3, E of (E, b) next to the symbol Sn indicating each state indicates a corresponding expected amplitude value, and b indicates binary data. The states S1 and S2 correspond to the rise of the signal waveform, and S4 and S5 correspond to the fall of the signal waveform.

In FIG. 2, B (t) and S (t) represent binary data and a state number, respectively. The DC level of the AC signal is defined as a voltage level at which the sum of the product of the amplitude and the time of the plus signal portion and the sum of the product of the amplitude and the time of the minus signal portion are equal to the DC level.

FIG. 4 is a diagram showing an example of the rectangular wave used in the above description. As shown in FIG. 4, the area of the oblique line above the DC level is equal to the area of the oblique line below.

As shown in FIG. 2, DC at time t0
Assuming that the level is equal to Vref0, the DC level rises to the plus side by the next 5T space over 5T as shown by the dotted line in the figure. The amount of the change is greatly affected by the capacity of the signal line and the like.

In the reproducing circuit of this embodiment, the DC level fluctuation amount is approximated to be proportional to the product of the peak amplitude in the case of a space of 3T to 11T or the product of the bottom amplitude and the length in the case of a mark.

When the time length of a space and a mark is counted using a sampling clock extracted from a reproduction signal, the space is between states S2 and S3, the mark is between states S5 and S0, 22 is activated and counting is performed, and a value obtained by adding 1 to this count value is defined as a time length.

When the count value is C, the space and mark coefficients for N = C + 1 are S (N) and M, respectively.
As (N), the slice level: Vref of the next reproduced signal is determined by the following equations (3) and (4). Equation 3 is selected for a space, and Equation 4 is selected for a mark. However, N = 3 to 11.

[0046]

(Equation 3)

[0047]

(Equation 4)

Therefore, for example, in the case of a 4T mark,
Vref is reduced by M4 × 4 to prepare for the detection of the next space. As described above, since the slice level follows the DC level fluctuation, the binarization can be accurately performed even in the case of the 3T space.

Therefore, the data error rate at the time of reproduction can be reduced as compared with the fixed slice level. Since the amplitudes of 5T to 11T are almost the same, the coefficients S5 to S11 and M5 to M11 may have the same value.

As described above, in the reproducing circuit according to the first embodiment of the present invention, the slice level signal generated by the Vref generating circuit 19 and the digital signal output from the FIR 16 which is a digital finite impulse response type filter. By using the result of the comparison as binary data, accurate data reproduction can be performed.

Further, the time length of the reproduced signal subjected to the partial response equalization is counted, and the count value is incremented by +1.
The value thus obtained is set as the time length of the reproduction signal: N, and the slice level: Vref is made to follow the DC level fluctuation of the reproduction signal by increasing or decreasing the slice level: Vref by a value obtained by multiplying the time length: N by a predetermined coefficient. , Accurate binarization is possible.

FIG. 5 is a diagram showing a configuration of a reproducing circuit according to a third embodiment of the present invention. As shown in FIG. 5, in the reproduction circuit in this case, the error detection circuit 20
Detects whether the binarized data contains a mark or space having a length of 1T or 2T, and detects 1T or 2T
If a space or mark is detected, this is regarded as an error.

The counter 24 is a counter for counting the number of space errors: SE and the number of mark errors: ME every predetermined period, for example, every several hundred clock periods. When the number of mark errors of the counter 22: ME exceeds a predetermined value, the Vref generation circuit 19 calculates the coefficient S (N) according to the following Expression 5, and when the number SE of space errors exceeds a predetermined value. Increases the coefficient M (N) by a predetermined value according to the following equation (6). However, N = 3 to 11
It is.

[0054]

(Equation 5)

[0055]

(Equation 6)

For example, when the number of space errors: SE exceeds a predetermined value, the coefficient M (N) becomes B
(N) increases, so that Vref becomes B (N) ×
The number is further reduced by N, and the slice level for space detection is reduced. Thereby, the detection error rate of the 3T space can be further reduced.

As described above, in the reproducing circuit according to the third embodiment of the present invention, the error detection circuit is provided, and when a predetermined number or more errors occur in a predetermined period, the increase / decrease of the slice level: Vref is increased. Therefore, more accurate binarization is possible, and more accurate data reproduction can be performed.

FIG. 6 is a diagram showing a configuration of a reproducing circuit according to an embodiment of the present invention. In the reproducing circuit of this embodiment, partial response equalization is not performed.

In this reproducing circuit, six states S0, S1, S2, S3, S4, and S5 are assumed in the same manner as in the above-described reproducing circuit, but the amplitude is longer than that in the case where partial response equalization is performed. , The peak level and the bottom level increase as the length increases. In addition, even if the lengths are the same, there is a fluctuation in the amplitude, so that it is impossible to set the expected amplitude value for each state.

Next, a description will be given, with reference to FIG. 7, of a condition for judging a state transition in the reproducing circuit. The value in parentheses next to the symbol Sn indicating each state in FIG. 7 represents binarized data. First, when the reproduction signal exceeds Vref, the state S2 is entered. Then, when the signal amplitude increases by a predetermined D,
3 is assumed. Further, it is assumed that a transition to the state S4 occurs when the signal amplitude decreases by the predetermined D next. Further, the same determination is made for the fall of the reproduction signal.

In the case of a space, the counter 22 is activated and counting is performed between the states S2 and S3, and the value obtained by adding 1 to the count value C of the counter 22 is defined as the time length of the space.

In this reproducing circuit, in order to estimate the DC level fluctuation, the sum of the difference between the reproduced signal amplitude value: Y (t) and Vref is obtained for each space or mark, and S and M are set as predetermined coefficients to obtain the following. The slice level of the next mark or space is determined by Expressions 7 and 8. Equation 7 is selected for a space, and Equation 8 is selected for a mark.

[0063]

(Equation 7)

[0064]

(Equation 8)

As described above, since the slice level follows the DC level fluctuation in accordance with the above equations (7) and (8), even in the case of a reproducing circuit which does not perform partial response equalization, it is possible to accurately binarize the reproduced signal. it can. Therefore, the data error rate at the time of reproduction can be reduced as compared with the fixed slice level.

FIG. 8 is a diagram showing a configuration when an error detection circuit 20 is provided in the reproduction circuit shown in FIG. This error detection circuit 20 performs error detection in the same manner as the above-described error detection circuit. The counter 24 calculates the number of space errors: SE and the number of mark errors: M every predetermined period.
Count E.

When the number of mark errors of the counter 22: ME exceeds a predetermined value, the Vref generating circuit 19 calculates the coefficient S according to the following equation (9), and when the number of space errors: SE exceeds a predetermined value. , And increases the coefficient M by a predetermined value according to the following Expression 10.

[0068]

(Equation 9)

[0069]

(Equation 10)

[0070]

[Equation 11]

For example, when the number of space errors: SE exceeds a predetermined value, the coefficient: M increases by B according to equation (10), and further decreases by equation (11) according to equation (4). Lower the level. This gives 3
The detection error rate of T space can be further reduced,
Accurate data reproduction can be performed.

As described above, in the reproducing circuit according to the second or third embodiment of the present invention, even if the optical disc does not have the FIR or the optical disc cannot sufficiently equalize the reproduced signal, the reproduction signal amplitude value and Slice level: Vre
Slice level: Vre by an amount proportional to the sum of the differences f
By increasing / decreasing f, the slice level: Vref follows the DC level fluctuation of the reproduction signal.
Value conversion becomes possible.

FIG. 9 is a diagram showing a configuration of a first example of the reproducing circuit according to the fourth embodiment of the present invention. The FIR 25 of this reproducing circuit is an analog finite impulse response type filter circuit unlike the above-described FIR 16.

FIG. 10 shows PR (a1, a2, a3, a
4) is a diagram showing the internal configuration of the FIR 25 that performs equalization. The FIR 25 includes delay circuits 50a to 50d for delaying an analog value for 1T time, and each delay circuit 50a
Analog multiplying circuits 51a to 51d for multiplying the outputs from .SIGMA. To 50d and the coefficients a1 to a4, respectively, and an analog adding circuit 52 for adding and outputting the signals of four multiplication results by the analog multiplying circuits 51a to 51d. Become.

The Vref generating circuit 19 sets the output signal of the FIR 25 to the reproduced signal amplitude value: Y (t), and subtracts the result (Y (t) from the value 1T before every clock in the same manner as the circuit shown in FIG. t) -Y (t-1)) is compared with the expected variable at the time of transition between states other than between S1 and S2 and between S4 and S5 to determine transition between states.

The transition between S1 and S2 and the transition between S4 and S5 are determined by comparing with the slice level: Vref updated corresponding to the change in the DC level.

Thereafter, Vref is updated in accordance with equations (3) and (4) by performing the same operation as that of the above-described reproducing circuit. Therefore, although the same effect as that of the above-described reproducing circuit is obtained, the chip can be made smaller when an LSI is formed because an A / D converter is not used, and the current consumption can be reduced as compared with the case of the above-described circuit. .

FIG. 11 is a diagram showing the configuration of a second embodiment of the reproducing circuit according to the fourth embodiment of the present invention.
The Vref generating circuit 19 of this reproducing circuit performs the same operation as the above-described reproducing circuit. Also, the error detection circuit 20 performs the same operation as the error detection circuit of the above-described reproduction circuit, and updates the coefficients: S (N) and M (N) according to Equations 5 and 6.

Therefore, although the same effects as those of the above-described reproducing circuit are obtained, since the A / D converter is not used, the chip can be made smaller when an LSI is formed, and the current consumption can be reduced.

[0080]

As described above, according to the information reproducing apparatus of the present invention, the data error when reproducing the binary data from the analog signal at the time of reproducing the information on the recording medium can be remarkably reduced. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a reproducing circuit of an optical disc reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a reproduced signal shown in FIG. 16 or a reproduced signal after partial response equalization in the reproducing circuit shown in FIG. 1 and an expected amplitude value;

FIG. 3 is a state transition diagram of an operation in the reproducing circuit according to the first and third embodiments of the present invention.

FIG. 4 is a waveform diagram illustrating a DC level.

FIG. 5 is a diagram showing a configuration of a reproducing circuit according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a reproducing circuit according to an embodiment of the present invention;

FIG. 7 is a state transition diagram of an operation in the reproduction circuit according to the second and third embodiments of the present invention.

FIG. 8 is a diagram showing a configuration when an error detection circuit 20 is provided in the reproduction circuit shown in FIG. 6;

FIG. 9 is a diagram showing a configuration of a first example of a reproducing circuit according to an embodiment of the present invention;

10 is a diagram showing an internal configuration of an analog finite impulse response type filter circuit (FIR) 25 shown in FIG.

FIG. 11 is a diagram showing a configuration of a second example of the reproduction circuit according to the embodiment of the present invention;

FIG. 12 is an explanatory diagram showing a state after data recording on a recordable optical disc on which information can be written.

FIG. 13 is a diagram illustrating a configuration example of an optical disk reproducing device including a conventional information reproducing device.

FIG. 14 is a diagram showing a configuration example different from the conventional reproduction circuit shown in FIG.

FIG. 15 shows a finite impulse response type filter circuit F
FIG. 3 is a diagram illustrating an internal configuration of an IR.

FIG. 16 is a diagram showing a reproduced signal sampled after partial response equalization.

[Explanation of symbols]

 1: optical disk 2: pickup 3: I / V amplifier 4: analog computing unit 5: servo control circuit 6: spindle motor 7: AC coupling 10: reproduction circuit 11: analog EQ 12: slice circuit 13: PLL 14: sampling circuit 15: A / D converter 16, 25: FIR 17: Digital comparator 18: Binarization circuit 19: Vref generation circuit 20: Error detection circuit 21: Comparators 22, 24: Counter 23: State determination circuit 30: Laser Beam spot 31: Track 32: Mark 33: Space 40a to 40d, 50a to 50d: Delay circuit 41a to 41d, 51a to 51d: Multiplication circuit 42, 52: Addition circuit

Claims (4)

[Claims] 1. An information reproducing apparatus for reproducing information recorded on a recording medium, comprising: clock signal output means for outputting a clock signal of an arbitrary frequency based on an external signal; Analog-to-digital conversion means for converting a reproduced signal of an analog value synchronized with the clock signal into a digital signal and outputting the digital signal, and digital finite impulse response type filter means for waveform-equalizing and outputting the digital signal output from the means. Counting means for counting the time length of the digital signal output from the means,
A slice level generating means for generating a slice level signal obtained by adding or subtracting 1 to the count value counted by the means as a time length of the reproduction signal and increasing or decreasing the time length by a value obtained by multiplying the time length by a predetermined coefficient; Comparing means for comparing the slice level signal generated by the means with the digital signal output from the digital finite impulse response filter means, and binary data for outputting binary data based on the comparison result by the means An information reproducing apparatus, comprising: an output unit. 2. An information reproducing apparatus for reproducing information recorded on a recording medium, comprising: clock signal output means for outputting a clock signal of an arbitrary frequency based on an external signal; Analog-to-digital conversion means for converting a reproduced signal having an analog value synchronized with the clock signal into a digital signal and outputting the digital signal; counting means for counting the time length of the digital signal output from the means;
A value obtained by adding 1 to the count value counted by the means is set as a time length of the reproduction signal, and a slice level signal is generated by increasing or decreasing the sum of the digital signals for each time length by a predetermined coefficient. Slice level generating means, comparing means for comparing the slice level signal generated by the means with the digital signal output from the analog-to-digital converting means, and outputting binary data based on the comparison result by the means An information reproducing apparatus, comprising: 3. A detecting means for detecting a mark and a space having a length less than a specified value from the binarized data output from the binarized data output means, wherein the detecting means detects a mark and a space in a predetermined period. 3. The information reproducing apparatus according to claim 1, wherein when one or more errors are detected, the predetermined coefficient is increased by a predetermined constant. 4. An information reproducing apparatus for reproducing information recorded on a recording medium, comprising: a clock signal output means for outputting a clock signal of an arbitrary frequency based on an external signal; and a reproduced signal of an analog value. Finite impulse response type filter means for equalizing the waveform and outputting the same, and counting the time length of the analog signal output from the analog finite impulse response type filter means based on the clock signal output from the clock signal output means. Counting means, and a slice level generating means for generating a slice level signal obtained by adding or subtracting 1 to the count value counted by the means as a time length of the reproduction signal and increasing or decreasing the time length by a predetermined coefficient. Means, a slice level signal generated by the means, and the analog finite impulse response type fill. An information reproducing apparatus comprising: comparison means for comparing an analog signal output from data means; and binary data output means for outputting binary data based on a result of the comparison.