JP2002304817A - Amplitude limited waveform equalizer with narrowed amplitude limit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplitude limited waveform equalizer capable of performing waveform equalization processing by making an amplitude limitation width narrower than that of the prior art while keeping a noise suppression effect attendant on waveform equalization of a reproduced signal. SOLUTION: By shifting the phase of a clock CLK for sampling the reproduced signal RF in synchronization with the reproduced signal by a half cycle of the clock relative to the phase permitting to sample zero-crossing, the reproduced signal RF is limited by an upper limit and a lower limit having a narrower width than the conventional width which is set by signal values at two points in time approximately a half clock before and after the zero-crossing time. The upper and lower limits are obtained from two signal values of the digitized reproduced signal before and after the zero-crossing point.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform equalizer.

[0002]

2. Description of the Related Art A reproducer for reproducing information recorded on an information recording medium such as an optical disk reads information recorded on the rotationally driven information recording medium by a pickup and detects a reproduced signal. A waveform equalization process is performed on the detected reproduction signal using a waveform equalizer, and a waveform equalization signal that has been subjected to the waveform equalization process is input from the waveform equalizer and binary-coded. It is configured to reproduce data by converting the data. The detection and the waveform equalization of the reproduction signal are synchronized with a clock signal generated based on the reproduction signal, that is, the detection and the waveform equalization of the reproduction signal are treated as digital signal processing. Conventionally, the waveform equalizer has performed a filtering process for enhancing a high-frequency component of the reproduction signal in order to remove noise such as inter-symbol interference. There was a problem that the whole noise was amplified in the opposite way. Therefore, an amplitude-limited waveform equalizer that suppresses the occurrence of the noise by limiting the amplitude of the reproduction signal before performing the waveform equalization of the reproduction signal in the waveform equalizer has been proposed. . (JP 11
-259895). The amplitude-limited waveform equalizer is based on a time at an intersection of the reproduction signal and a slice level, which is a threshold value for binarizing the reproduction signal, at a time one clock before the intersection. The lower limit value and the upper limit value of the amplitude limit value are set based on the signal value and the signal value at a time one clock after the intersection.

[0003]

However, in the above-described conventional waveform equalizer for limiting the amplitude of a reproduced signal, the width of the amplitude limit value (the width between the upper limit value and the lower limit value) is the limit. If the width of the amplitude limit value is further narrowed, the signal value of the reproduced signal and the signal value of the amplitude limit signal at a time about one clock before or after the intersection become different values, so that the noise amplification occurs again. The width of the amplitude limit value could not be further reduced. Therefore, it was not possible to obtain a greater effect by limiting the amplitude of the reproduced signal to a smaller value. Further, since the amplitude of the reproduction signal cannot be further limited, the asymmetry (so-called asymmetry) between the amplitude level of the signal higher than the slice level of the reproduction signal and the amplitude level of the signal lower than the slice level has It was not possible to limit the amplitude to eliminate the influence of the above. The present invention has been made to solve the problems of the related art, and has as its object to maintain the effect of suppressing the amplification of noise including intersymbol interference generated by the waveform equalization. It is still another object of the present invention to provide a waveform equalizer that can perform waveform equalization with the width of the amplitude limit value narrowed compared to the related art.

[0004]

According to the present invention, there is provided an amplitude limiting means for limiting an amplitude of a reproduced signal reproduced from recording information recorded on a recording medium based on an amplitude limiting value, and an output signal from the amplitude limiting means. Waveform equalization means for performing waveform equalization on the reproduced signal after the amplitude limiting process, wherein the amplitude limit value is a lower limit set across a slice level which is a threshold value for binarizing the reproduced signal. In a waveform equalizer comprising a value and an upper limit, the amplitude limiting means sets a period of a clock signal generated from the reproduction signal and synchronized with the reproduction signal to T, and the reproduction signal crosses the slice level. Assuming that the time is t, the upper limit value and the lower limit value are set based on the signal value of the reproduction signal corresponding to time (t-0.5T) and the signal value corresponding to time (t + 0.5T). Composed into And wherein the are.

Therefore, according to the present invention, the signal value at the time 0.5 clocks before the reproduction signal and the signal value at the time 0.5 clocks after the reproduction signal are referred to the time when the reproduction signal crosses the slice level. Since the lower limit value and the upper limit value of the amplitude limit value are respectively set based on the upper limit value and the lower limit value of the amplitude limit value, the signal of the digitized reproduction signal before and after the reproduction signal crosses the slice level is set. The width of the amplitude limit (the upper limit and the lower limit) is not greatly different from each other, so that the effect of suppressing the amplification of the entire noise including the noise such as the intersymbol interference generated by the waveform equalization is maintained. ) Can be made narrower than in the prior art to perform waveform equalization.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a reproducing system of an optical disk device to which a waveform equalizer of the present invention is applied. As shown in FIG. 1, the reproduction system of the optical disk device reproduces information recorded on an information recording medium 1 such as an optical disk.
A spindle motor 2 for rotationally driving the optical disc, a pickup 3 for detecting information recorded on the information recording medium 1 rotated by the spindle motor 2 as a reflected light signal, and an electric signal for detecting the detected reflected light signal. A signal detection circuit 4 for detecting a reproduced signal by converting the signal to a phase-locked loop; a phase synchronizing circuit 5 for inputting the reproduced signal and generating a clock signal synchronized with the reproduced signal; A waveform equalizer 6 for generating a waveform equalized signal, and a binarizing circuit 7 for receiving the synchronized clock signal and the waveform equalized signal and binarizing the waveform equalized signal to reproduce the binarized signal
And

FIG. 2 is a block diagram showing the configuration of the waveform equalizer 6. As shown in FIG.
Comprises a low-pass filter 8 (LPF 8 in the figure), an AD converter 9, a waveform equalizing part 12, a DA converter 10, a low-pass filter 11 (LPF 11 in the figure), and a delay element 13. I have. The low-pass filter 8 includes:
The analog reproduction signal R detected by the pickup 2
It is configured to input F (t). The AD converter 9 converts the analog reproduced signal RF (t) passed through the low-pass filter 8 into a digitized reproduced signal RF (t).
(N). The waveform equalizing section 12 is configured to perform waveform equalization on a reproduction signal output from the AD converter 9. The DA converter 10 converts the digital waveform equalized signal EQ (n) after waveform equalization output from the waveform equalizing section 12 into an analog waveform equalized signal EQ (t) and outputs the converted signal. Is configured. The low-pass filter 11 is provided with the DA
Analog waveform equalized signal EQ output from converter 10
(T) is input. The delay element 13 inputs a clock signal CLK (0) for sampling a zero cross generated from the analog reproduced signal RF (t) by the phase synchronization circuit 5 that generates a clock synchronized with the clock of the reproduced signal, A clock signal CLK (π) which is delayed by a half cycle of the clock and does not sample the zero cross is generated, and the clock signal CLK (π) is supplied to the AD converter 9 and the waveform equalizing section 12. ing. The AD converter 9 and the waveform equalizer 12 are configured to process the digitized reproduction signal RF (n) sampled based on the clock signal CLK (π) that does not sample the zero cross as digital data. Have been. Clock signal CLK for sampling the zero cross
(0) detects a zero-cross timing which is an intersection of the slice level and the reproduction signal RF (t). That is, it has a phase for sampling the zero cross. On the other hand, the clock signal CLK (π) which does not sample the zero cross has a phase for sampling the value of the reproduction signal RF (t) at a timing shifted by a half cycle of the clock with respect to the timing of the zero cross. . It is assumed that the digitized reproduction signal RF (n) output from the AD converter 9 has a signal value ranging from positive to negative, adjusted so that the slice level s becomes zero.

FIG. 3 is a block diagram showing an internal configuration of the waveform equalizing section 12. As shown in FIG. As shown in FIG. 3, the waveform equalizer 12 includes an amplitude limiter 14 for inputting the digitized reproduction signal RF (n) output from the AD converter 9 to limit the amplitude, and a flip-flop. 15 to 1
8, multipliers 19 to 23, adders 24 and 27, and flip-flops 25 and 26. The amplitude limiter 14 is configured to output the digitized reproduction signal RF
The amplitude of (n) is limited and output as an amplitude limited signal LRF (n), the configuration of which will be described later.
The flip-flops 15 to 18 are connected in series in this order. That is, the input terminal of the flip-flop 15 is connected to the output terminal of the amplitude limiter 14, the input terminal of the flip-flop 16 is connected to the output terminal of the flip-flop 15, and the output terminal of the flip-flop 16 is connected to the output terminal of the flip-flop 16. The input terminal of the flip-flop 17 is connected, and the input terminal of the flip-flop 18 is connected to the output terminal of the flip-flop 17.

The flip-flops 15 to 18 are provided with a clock CLK which does not sample the zero cross.
(Π), so that the amplitude limit signal LRF (n) is delayed by one clock each time it passes through each of the flip-flops 15 to 18. The multiplier 19 has an input terminal connected to an output terminal of the amplitude limiter 14 and an input amplitude limit signal LR.
It is configured to multiply F (n) by a coefficient K2.
The input terminal of the multiplier 20 is the flip-flop 1
5 and is configured to multiply the input amplitude-limited signal LRF (n-1) delayed by one clock by a coefficient K1. The input terminal of the multiplier 21 is connected to the output terminal of the flip-flop 16 and the input amplitude-limited signal LRF (n−
It is configured to multiply 2) by a coefficient K0. The multiplier 22 has an input terminal connected to the output terminal of the flip-flop 17 and is configured to multiply the inputted amplitude-limited signal LRF (n-3) delayed by three clocks by a coefficient K1. The multiplier 23 has its input terminal connected to the output terminal of the flip-flop 18 and
The amplitude limiting signal LRF (n−4) delayed by the clock is multiplied by a coefficient K2. The adder 24 is configured to receive and add the outputs of the multipliers 19 to 23 and add them. The flip-flop 2
Reference numerals 5 and 26 are operated by the clock signal CLK (π) which does not sample the zero cross, and the digitized reproduction signal RF (n) is delayed by one clock every time it passes through the flip-flop by one stage. It is configured as follows. The adder 27 is connected to the output of the flip-flop 26 which is not subject to the amplitude limitation and the adder 2.
4 is added to output the result as a waveform-equalized digital waveform equalized signal EQ (n). The respective signals obtained by multiplying the respective amplitude limiting signals delayed by the respective flip-flops 15 to 18 by the respective coefficients by the respective multipliers 19 to 23;
The reproduction signal delayed at 26 is added by the adders 24 and 27 so that the digital waveform equalized signal EQ (n) in which the high-frequency component is emphasized is output from the adder 27. Have been.

FIG. 4 is a block diagram showing the configuration of the amplitude limiter 14. As shown in FIG. 4, the amplitude limiter 14 includes an absolute value circuit 28, a binarization circuit 29, flip-flops 30 to 32, an XOR gate circuit 33,
Sample hold circuit 34 and low-pass filter 35
And a limiter 36. Absolute value circuit 28
Is configured to output an absolute value signal | RF (n) | of a difference between the digitized reproduction signal RF (n) output from the AD converter 9 and the slice level s = 0. The flip-flop 30 is connected to the absolute value circuit 2.
8 is configured to output an absolute value signal | RF (n-1) | that is obtained by delaying the absolute value signal from E.8 by one clock. The sample and hold circuit 34 is configured to sample and hold the absolute value signal | RF (n-1) | output from the flip-flop 30 and delayed by one clock. The binarization circuit 29 outputs the digitized reproduction signal R output from the AD converter 9.
It is configured to output a binarized signal b (n) by comparing F (n) with a slice level s = 0 which is a threshold. The flip-flops 31 and 32 are connected in series, and a binarized signal b output from the binarization circuit 29 is output.
It is configured to output a binary signal b (n−2) obtained by delaying (n) by one clock and two clocks in total. The XOR gate circuit 33 outputs the binarized signal b (n) output from the binarization circuit 29 and the binarized signal b (n−2) output from the flip-flop 32 and delayed by two clocks. ) And the signal x which is an exclusive OR with
(N-1) is output as a control signal for the sample and hold circuit 34.

[0011] The low-pass filter 35 is provided with the absolute value signal |
It is configured to input a value of RF (n-1) |. The limiter 36 determines the upper limit value Vl based on the absolute value Vl averaged through the low-pass filter 35.
And the lower limit value -Vl are set, thereby limiting the amplitude of the digitized reproduction signal RF (n), and controlling the amplitude of the amplitude-limited signal LR.
It is configured to output F (n).

FIG. 5 is a characteristic diagram showing an example of input / output characteristics of the limiter 36. The horizontal axis indicates the input signal level Vx.
The output signal level Vy is shown on the vertical axis. FIG. 5 (A)
The input signal level Vx has an upper limit Vl and a lower limit −
Vl, the output signal level Vy is proportional to the input signal level Vx, and if the input signal level Vx is a value exceeding the upper limit value Vl and the lower limit value -Vl, the output signal level Vy Vy takes a signal value Vl if the input signal level Vx is larger than the slice level s = 0, and takes a signal value -Vl if the input signal level Vx is smaller than the slice level s = 0. A diagram is shown that is configured to show the input / output characteristics such as: In the input / output characteristics of FIG. 5A, the output signal level Vy is completely suppressed to an amplitude set by the upper limit value Vl and the lower limit value -Vl. FIG.
(B) shows that the input signal level Vx has the upper limit value Vl and the lower limit value −
When the value is between Vl, the output signal level Vy is proportional to the input signal level Vx, and the input / output characteristic is such that the change rate (absolute value) decreases as approaching the upper limit value Vl or the lower limit value -Vl. In addition, when the input signal level Vx is a value in a region exceeding the upper limit value Vl and the lower limit value -Vl,
The output signal level Vy is about the signal value V1 when the input signal level Vx is higher than the slice level s = 0, and is about the signal value −V1 when the input signal level Vx is lower than the slice level s = 0. Take the value of
A diagram is shown that is configured to show input / output characteristics that make a slight gradient with the horizontal axis. Also in the input / output characteristics of FIG. 5B, the output signal level Vy is completely suppressed within the amplitude set by the upper limit value Vl and the lower limit value -Vl. As the limiter 36, for example, FIG.
A limiter having the input / output characteristics shown in (A) and (B) can be used. The limiter 36, the absolute value circuit 2
8. The sample hold circuit 34, the binarization circuit 29, and the flip-flops 30, 31, 32 are configured to operate based on the clock signal CLK (π) that does not sample the zero cross. In the present embodiment, the amplitude limiter 14 corresponds to the amplitude limiter in the claims, and the flip-flops 15 to 18, the multipliers 19 to 23, the additions 24 and 27, and the flip-flop 25 , 26 correspond to an example of the waveform equalizing means in the claims. Further, the delay element 13 corresponds to a delay unit in the claims.

Next, the operation of the amplitude limiting section 14 configured as described above will be described with reference to FIG. 4 and FIG. 6 which is a timing chart showing signals of each section in the amplitude limiting section 14. FIGS. 6A to 6F show a signal CLK (π) that does not sample the zero cross, the digitized reproduction signal RF (n), and the absolute value signal | RF.
(N-1) |, the binary signals b (n), b (n-
2), the control signal x (n-1) is shown. The clock signal CLK that does not sample the zero crossing
(Π) performs sampling of the analog reproduction signal RF (t) at the rising timing. FIG.
(A) and (B), an intersection P0 at which the digitized reproduction signal RF (n) input to the limiter 36 intersects the slice level s = 0, and a clock signal CLK that does not sample the zero cross. The rise of (π) is shifted by half a clock period (0.5T). As shown in FIG. 6C, the absolute value circuit 2
9 and the absolute value signal | RF (n-1) | generated by the flip-flop 30 are the absolute value signal | RF (n) | of the digitized reproduction signal RF (n) for one cycle of the clock signal. (1T) The signal is delayed. As shown in FIG. 6D, the binarized signal b (n) output from the binarizing circuit 29 is invalid at the rising timing of the clock signal CLK (π) that does not sample the zero cross. From the L level) to the effective state (H
Level). As shown in FIG. 6E, the signal b (n) output from the flip-flop 32
-2) indicates that the binary signal b (n) is equivalent to two clocks (2
T) The signal is delayed. As shown in FIG. 6 (F), the control signal x (n-1) output from the XOR gate circuit 33 includes the binary signals b (n-2), b
(N) A signal indicating the exclusive OR, that is, a signal that rises 2.5 clocks later at a time half a clock delayed from the time of the intersection of the digitized reproduction signal RF (n) with the slice level s = 0 It has become. When the control signal x (n-1) is in a valid state (H level), the sample and hold operation of the sample and hold circuit 34 becomes possible. Therefore, as shown in FIG. 6C, the sample and hold circuit 34 controls the control signal x.
Since the rising edge of the clock signal CLK (π) that does not sample the zero cross is input twice while (n−1) is in the valid state, the absolute value signal | RF (n−1) is input.
The points Q1 and Q2 of | are sampled and this value is held. These points Q1 and Q2 correspond to the points P1 and P2, which are moved forward and backward by half a clock with respect to the point of intersection P0 at which the digitized reproduction signal RF (n) crosses zero. The point Q0 is a point corresponding to the intersection P0.
The sample hold circuit 34 controls the control signal x (n
Each time -1) becomes valid, sample-and-hold is performed at the points Q1 and Q2, and the sampled and held signal value of the point Q1 (first signal value) and the signal value of Q2 (second signal value) are It is averaged by the low-pass filter 35. The averaged value Vl is input to the limiter 36. In the limiter 36, Vl is set to an upper limit value as an amplitude limit value, and -Vl is set to a lower limit value as an amplitude limit value. In other words, the signal value at the time (t-0.5T) earlier by 0.5 clock and the time (t-0.5T) earlier by 0.5 clock with reference to the time t at the intersection P0 of the analog reproduction signal RF (t). The amplitude limit value can be set based on the signal value of 0.5T). The amplitude limit value set in the present embodiment, compared with the case of the conventional amplitude-limited waveform equalizer, the upper limit and lower limit of the amplitude limit,
The signal value of the reproduced signal before and after the reproduced signal crosses the slice level does not become significantly different from the signal value of the reproduced signal. While maintaining this, the width of the amplitude limitation can be narrowed compared to the conventional case, and the waveform can be equalized. This will be described below.

As shown in FIG. 7B, in a conventional amplitude-limited waveform equalizer, a reproduced signal RF of an analog signal is used.
A signal value at a time one clock before and a signal value at a time after one clock are sampled by a clock signal (0) for sampling a zero cross, with reference to the time of the intersection where (t) crosses the slice level s = 0. The lower limit and upper limit of the amplitude limit value are set based on these two signal values. As shown in FIG. 7A, in the amplitude-limited waveform equalizer of the present embodiment, the analog reproduction signal RF (t) is based on the time of the intersection at which the slice level s = 0 is crossed. The signal value at the time before 0.5 clock and the signal value at the time after 0.5 clock are sampled by the clock signal CLK (π) which does not sample the zero cross, and the amplitude limit values are respectively determined based on these two signal values. FIG. 8 (A) in which a lower limit and an upper limit are set.
5 shows the eye pattern of the amplitude limit signal LRF (n) by the amplitude limiter in the waveform equalizer of the present embodiment and the slice level s = 0. FIG. 8 (B) shows an eye pattern of the amplitude limited signal LRF (n) by the amplitude limiting means in the conventional amplitude limited type waveform equalizer. As can be seen by comparing FIGS. 7A and 7B and FIGS. 8A and 8B, in the present embodiment, the analog reproduced signal RF (t) crosses the slice level s = 0. The signal value at the time before 0.5 clock and the signal value at the time after 0.5 clock are sampled on the basis of the time of the intersection, and based on the average value of the absolute values of these two signal values. An upper limit value and a lower limit value of the amplitude limit value are set, respectively. Therefore, the upper limit value and the lower limit value of the amplitude limit do not become significantly different from the signal values of the digitized reproduction signal before and after the reproduction signal crosses the slice level, and thus the waveform While maintaining the effect of suppressing noise amplification such as intersymbol interference due to equalization, the width of the amplitude limitation can be made narrower than in the prior art to equalize the waveform.

The setting of the amplitude limit value is performed by setting the signal value P1 of the digitized reproduction signal RF (n) corresponding to the time (t-0.5T) and the time (t + 0.5T).
T) the digitized reproduction signal RF corresponding to T)
The signal value P2 of (n) may be sampled, and the sampled signal values P1 and P2 may be set by holding and averaging the larger signal value as the upper limit value and the smaller signal value as the lower limit value. Good. In the present embodiment,
Although the amplitude limit value set in the limiter 15 is automatically set, the amplitude limit value is set by operating circuit elements such as a dip switch, a rotary switch and a volume. You may.

[0016]

As described above, according to the present invention, the signal value at the time of 0.5 clock before the reproduction signal is set to 0.
Since the lower limit value and the upper limit value of the amplitude limit value are set based on the signal value at the time after 5 clocks, respectively, the upper limit value and the lower limit value of the amplitude limit are set to be smaller than those of the prior art. Does not become significantly different from the signal value of the digitized reproduction signal before and after crossing the slice level, and therefore, the suppression effect by amplitude limitation on noise amplification such as code interference caused by waveform equalization is maintained. The waveform equalization can be performed with the width of the amplitude limitation narrower than before. As a result, the effect obtained by limiting the amplitude of the reproduction signal can be expected to be larger by restricting the amplitude more narrowly, and by further restricting the amplitude of the reproduction signal, Waveform equalization processing can be performed by amplitude limiting means that further eliminates the effect of asymmetry between the amplitude level of the signal higher than the slice level and the amplitude level of the signal lower than the slice level. In addition, since the conventional waveform equalizer that limits the amplitude of the reproduced signal is based on the premise that a clock for sampling the zero cross is used, when binarizing the waveform equalized signal obtained by waveform equalizing the reproduced signal, The method of determining binary by directly comparing the signal value of the equalized signal with the slice level cannot be used, and a method used when converting the waveform equalized signal into a binary signal cannot be used. Although the influence on the waveform equalized signal had to be considered, in the present invention, when binarizing the reproduced signal after waveform equalization, the signal value of the reproduced signal is directly compared in magnitude with the slice level. Thus, the binary can be determined.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a reproduction system of an optical disc device to which a waveform equalizer of the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of a waveform equalizer according to the present embodiment.

FIG. 3 is a block diagram illustrating an internal configuration of a waveform equalizer of the waveform equalizer according to the present embodiment.

FIG. 4 is a block diagram illustrating a configuration of an amplitude limiting unit of the waveform equalizer according to the present embodiment.

FIG. 5A is a block diagram illustrating an example of input / output characteristics of a limiter of the waveform equalizer according to the present embodiment;
(B) is a block diagram showing another example of the input / output characteristics of the limiter of the waveform equalizer according to the present embodiment.

FIG. 6 is a timing chart of each signal in an example of the amplitude limiter in the waveform equalizer of the present embodiment.

FIG. 7A is an explanatory diagram for explaining a sampling timing and a limit value of a reproduction signal in a waveform equalizer according to the present embodiment using an eye pattern, and FIG. FIG. 4 is an explanatory diagram for explaining the timing and the limit value of sampling of a reproduction signal in an amplitude-limited waveform equalizer using an eye pattern.

FIG. 8A is an explanatory diagram showing an eye pattern of an amplitude-limited signal in which the amplitude of a reproduced signal is limited in the waveform equalizer of the present embodiment, and FIG. FIG. 6 is an explanatory diagram showing an eye pattern of an amplitude limited signal obtained by limiting the amplitude of a reproduced signal in the waveform equalizer of FIG.

[Description of Signs] 6 ... Waveform equalizer, 12 ... Waveform equalizer, 13 ... Delay element, 14 ... Amplitude limiter, 15 to 18 ... Flip-flop, 19 to 23 ... Multiplier, 24, 27 ...
Adder, 25, 26 ... flip-flop, RF (n)
...... digitized reproduction signal, EQ (n) ... digital waveform equalized signal after waveform equalization.

Claims (6)

[Claims] 1. An amplitude limiting means for limiting an amplitude of a reproduced signal reproduced from recording information recorded on a recording medium based on an amplitude limiting value, and a reproduced signal output from the amplitude limiting means after the amplitude limiting processing. Waveform equalization means for performing waveform equalization, wherein the amplitude limit value is a waveform including a lower limit value and an upper limit value set across a slice level that is a threshold value for binarizing the reproduction signal. In the transformer, the amplitude limiting means sets a period of a clock signal generated from the reproduction signal and synchronized with the reproduction signal to T, and a time at which the reproduction signal crosses the slice level is t. The upper limit value and the lower limit value are set based on the signal value of the reproduced signal corresponding to (t−0.5T) and the signal value corresponding to time (t + 0.5T). Features and Waveform equalizer that. 2. The method according to claim 1, wherein the setting of the lower limit value and the upper limit value by the amplitude limiting means includes a first signal value which is a signal value of the reproduction signal corresponding to the time (t-0.5T) and the time (t + 0.5T).
0.5T) corresponding to the second signal value of the reproduction signal.
Sampling the signal value and the sampled first
The waveform equalizer according to claim 1, wherein the waveform equalizer is set based on an average value of absolute values of a difference between a signal value and a slice level of the second signal value. 3. The setting of the lower limit value and the upper limit value by the amplitude limiting means includes the first signal value which is the signal value of the reproduction signal corresponding to the time (t-0.5T) and the time (t + 0.5T).
0.5T) corresponding to the second signal value of the reproduction signal.
A signal value is sampled and set based on an average value of a larger one of the sampled first and second signal values and an average value of a smaller one of the sampled first and second signal values. The waveform equalizer according to claim 1, wherein: 4. A reproduced signal output from the amplitude limiter and having undergone the amplitude limit processing has signal values at the times (t-0.5T) and (t + 0.5T) of the first signal value and the second signal value. 4. The waveform equalizer according to claim 2, wherein a signal value matches the signal value, and a signal value at other times is suppressed within a range from the first signal value to the second signal value. 5. A delay means for delaying and outputting a clock signal having a phase for sampling the reproduced signal at a time crossing the slice level by 0.5 clock, wherein the first signal value and the second signal value are provided. 4. The waveform equalizer according to claim 2, wherein the sampling is performed based on the delayed clock signal output from the delay unit. 6. The waveform equalizer according to claim 5, wherein said delay means comprises a delay element.