JP3702694B2 - Digital signal processing circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital data processing circuit, and more particularly to a digital data processing circuit in which error correction processing is performed after digital data is temporarily stored in a memory.
[0002]
[Prior art]
As an example of a digital data processing circuit for data read from a recording medium,
Kenji Hayashi “CD-Audio to PC-”, Corona, pp. 56-71 (1990). This describes the contents of processing and the circuit configuration of the CD playback device and the digital data processing unit included in the device.
[0003]
In Japanese Patent Laid-Open No. 10-107648, the number of accesses to the memory required for CIRC error correction processing is equalized by parallel processing of C1 code and C2 code syndrome operations including read data, and error correction is performed. There is a description of a method and a circuit for realizing high-speed processing. Further, JP-A-8-167857 describes a method for reducing the time required for the syndrome calculation by simultaneously processing a plurality of words of the RS code syndrome calculation and a circuit for realizing the method.
[0004]
[Problems to be solved by the invention]
However, in the conventional method, error correction is performed by changing the data reading direction for each code, a method of reducing the number of accesses from the error correction circuit to the memory, and a syndrome calculation of RS codes are simultaneously processed by a plurality of words. Although there is a description of a method for reducing the processing time required for the syndrome calculation, error correction codes are formed in a plurality of directions like product codes, and a plurality of error correction processes can be performed in one direction. A method that can reduce the number of times the error correction circuit accesses the memory, a method that can speed up the syndrome operation even when the number of words that need to be processed at one time changes according to the direction of the error correction code, There is no description about the circuit.
[0005]
It is an object of the present invention to reduce the number of memory accesses of an error correction circuit, increase the speed of error correction processing, and to perform digital data processing having this circuit even when the number of words that require simultaneous syndrome calculation processing changes. It is to speed up the data processing of the circuit.
[0006]
[Means for Solving the Problems]
The present invention for attaining the above-described problems includes the following (1) to ( 3 ). (1) An input unit that inputs a first data sequence that forms an RS code and a second data sequence that is different from the first data sequence, and a first data sequence and a second data that are input by the input unit An error correction circuit comprising: an error correction circuit that performs an error correction process on a data string; and an output unit that outputs the first data string and the second data string subjected to the error correction process. The circuit performs a process on the first data string and a process on the second data string in parallel for the syndrome calculation process of the error correction process, and the calculation process except for the syndrome calculation process of the error correction process After processing the first data string, the second data string is processed, and the output means outputs the first data string subjected to the error correction processing. After the digital signal processing circuit, characterized in that an output means for outputting the second data string in which the processing has been performed . (2 ) In the digital signal processing circuit according to (1), as a calculation process excluding the syndrome calculation process of the error correction process, a circuit that generates a position polynomial and an error evaluation polynomial of the data string based on the syndrome of the data string; And a circuit for obtaining an error position and an error value of each data string based on the position polynomial and error evaluation polynomial of the data string, and outputting the first data string, and then performing the processing. The digital signal processing circuit characterized in that the output means for outputting the data string outputs the error position and error value of the data string. ( 3 ) A demodulating circuit for demodulating data read from a recording medium, a memory circuit for temporarily storing data demodulated by the demodulating circuit, and data stored in the memory circuit are inputted and inputted (1) performing error correction processing on data Or ( 2 And a digital signal processing circuit according to any one of claims 1 to 4, wherein the data subjected to the error correction processing is reproduced.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0008]
FIG. 1 is a block diagram showing the configuration of a digital data processing circuit according to the first embodiment of the present invention.
[0009]
In this figure, 101 is a 2-series simultaneous processing syndrome arithmetic circuit, 102 is a syndrome arithmetic circuit, 103 is a Sn arithmetic circuit, 104 is a Sn-1 arithmetic circuit, 105 is a S0 arithmetic circuit, 106 is an 8-bit data input terminal, and 107 is Addition circuit on GF (2 ^ 8), 108 is reset, 8-bit register with enable, 109 is a multiplication circuit of α ^ n, 110 is a multiplication circuit of α ^ n−1, 111 is a multiplication circuit of α ^ 0, 112 is an enable 8-bit register, 113 is an enable signal input terminal, 114 is a reset signal input terminal, 115 is a select signal input terminal, 116 is an AND circuit, 117 is a select circuit, and 118 is an 8 × (n + 1) bit output terminal. is there.
[0010]
However, 8-bit digital data input from the 8-bit data input terminal 106 is generated by a generator polynomial: G (x) = (x−α ^ n) (x−α ^ n−1) (x−α ^ 0). ) (Where α ^ n represents α to the nth power, and α ^ n, α ^ n-1, ..., α ^ 0 are elements of GF (2 ^ 8)), respectively. The code length is l, n + 1).
[0011]
The digital data input from the two 8-bit data input terminals 106 are different RS codes, and within each syndrome arithmetic circuit 102, the Sn arithmetic circuit 103, the Sn-1 arithmetic circuit 104,. Input to each circuit. This data is added to the data obtained by multiplying the output of the reset and enable 8-bit register 108 included in the circuit by α ^ i in each of the Si arithmetic circuits 103, 104, and 105, and then the enable signal input terminal 113. When the enable signal input from H is H, the 8-bit register 108 with reset and enable is taken in at the rising edge of the clock.
[0012]
The data output from the 8-bit register 108 is input to the select circuit 117 together with the output of another Sj arithmetic circuit, or input to the 8-bit register 112 with enable. Output data from the 8-bit register 108 with reset and enable input to the 8-bit register 112 is obtained when both the reset signal input from the reset signal input terminal 114 and the select signal input from the select signal input terminal 115 are H. Is taken into the 8-bit register 108 with enable at the rising edge of the clock and input to the select circuit 117.
[0013]
One of the two types of data input to the select circuit 117 is selected according to the H and L values of the select signal input from the select signal input terminal 115, and is output from the 8 × (n + 1) bit output terminal 118. It is output as output data (syndrome (Sn, Sn-1,..., S0)) of the two-series simultaneous processing syndrome calculation circuit 101.
[0014]
FIG. 2 is an example of a block diagram showing a configuration of an error correction circuit including the two-sequence simultaneous processing syndrome arithmetic circuit 101 of FIG.
[0015]
In this figure, 201 is an error correction circuit, 101 is a two-sequence simultaneous processing syndrome arithmetic circuit, 113 is an enable signal input terminal, 106 is an 8-bit data input terminal, 202 is a second arithmetic circuit, 203 is a third arithmetic circuit, 204 Is an error correction circuit, 206 is an error correction acceptance signal input terminal, 207 is an error position output terminal, 208 is an error value output terminal, 114 is a reset signal input terminal, and 115 is a select signal input terminal.
[0016]
The two-series simultaneous processing syndrome calculation circuit 101 is reset at a rate of once every two reset signals input to all the blocks from the reset signal input terminal 114 using the select signal described above. Two digital data inputted from the 8-bit data input terminal 106 are taken in by two enable signals synchronized with each of them, and a syndrome for each data string is calculated before the next reset occurs. The syndrome value thus obtained is output from the two-sequence simultaneous syndrome calculation circuit 101 in accordance with the value of the select signal input from the select signal input terminal 115.
[0017]
The second arithmetic circuit takes in the syndrome output from the two-series simultaneous syndrome arithmetic circuit 101 at the timing of the reset signal input from the reset signal input terminal 114, and generates an error position polynomial and an error evaluation polynomial based on this value. To do. The error locator polynomial and error evaluation polynomial generated by the second arithmetic circuit 202 are input to the third arithmetic circuit 203 at the timing of the next processing start signal, and based on the error locator polynomial and error evaluation polynomial in this circuit. After the error position and error value are obtained, the error correction circuit 204 takes in the next reset signal.
[0018]
Finally, several error positions and error values input to the error correction circuit 204 are controlled by the error correction reception signal input from the error correction reception signal input terminal 206, while the error position output terminal 207, error Are successively output from the value output terminal 208 to the outside of the error correction circuit 201.
[0019]
Next, it will be described with reference to FIGS. 3 and 4 that the present invention is effective in reducing the error correction processing time.
[0020]
FIG. 3 is a diagram showing the relationship between the time and the frame number on which the calculation is performed in each circuit of the error correction circuit having a syndrome calculation circuit that calculates only one series of syndromes at the same time.
[0021]
In FIG. 3, the vertical axis is the frame number, the horizontal axis is time, 301 is the syndrome calculation, 302 is the second calculation (error location polynomial, error evaluation polynomial generation), 303 is The third calculation (error position, error value calculation) is being performed, and 304 represents that the error is being corrected.
[0022]
This figure also shows that the error correction processing operation for each frame is shifted to the next frame at time T + i · Δt. In other words, the processing in the error correction circuit having the syndrome calculation circuit that calculates only one series of syndromes at the same time is performed by four-stage pipeline processing in which the processing time of one pipeline is Δt of a fixed time. Yes. Further, FIG. 3 shows that the processing time Δt of one pipeline of the error correction circuit is determined from the syndrome calculation processing time.
[0023]
Therefore, in a system that requires a long time to input digital data to the error correction circuit, such as when the code length l of the error correction code to be input is long, this error correction process can be performed at high speed. The phenomenon becomes a problem.
[0024]
That is, in such a system, speeding up the syndrome calculation and speeding up of data input are indispensable for shortening the error correction processing time.
[0025]
FIG. 4 is a diagram showing the relationship between the time and the frame number on which the calculation is performed in each circuit of the error correction circuit 201 of FIG.
[0026]
In FIG. 4, as in FIG. 3, the vertical axis indicates the frame number to be subjected to error correction processing, the horizontal axis indicates time, 301 indicates that the syndrome calculation is being performed, and 302 indicates the second calculation (error position polynomial, error evaluation). (Polynomial generation) is being performed, 303 is a third calculation (error position, error value calculation) is being performed, and 304 is an error correction being being performed.
[0027]
In this figure, error correction is performed by four-stage pipeline processing as in the error correction circuit described in FIG. 3, and only the syndrome operation is performed at time T + i · Δt and the other operations are performed at time T + 1/2 · i · Δt. However, in the error correction circuit 201 of FIG. 2, since the syndrome calculation can be performed simultaneously in two series, by outputting the obtained syndrome while switching at time 1/2 · i · Δt, processing of one pipeline is performed. This indicates that the time can be set to ½ · Δt.
[0028]
Thus, in this system, as compared with the system of FIG. 3, the syndrome calculation is substantially performed without changing the code length of the input RS code and the time required to input the digital data to the error correction circuit. It can be seen that the same effect as the speed increase can be obtained, and that the error correction processing time for the two sequences can be shortened by 2 · Δt.
[0029]
Further, in this process, two types of control signals (reset signal and select signal) are input at the timing shown in FIG. 4 in the error correction circuit 201 shown in FIG. 2 and output from the syndrome calculation circuit 101 to the second calculation circuit 202. When the reset signal of (T + i · Δt) = H, the 8 × (n + 1) -bit syndrome value is the output from the 8-bit register with reset and enable in FIG. 1, and (T + (1/2 + i) · Δt) This is realized by outputting the value of the syndrome held for (1/2 · Δt) once in the reset and enable 8-bit register 108 when the reset signal = H.
[0030]
Further, in the error correction circuit 201 in FIG. 2, the select signal input from the select signal input terminal 115 is fixed to H in the syndrome arithmetic circuit 101 in FIG. 1, and the 8-bit data is input only from the 8-bit data input terminal 106. It is of course possible to perform the same operation as that of the error correction circuit for performing the syndrome calculation of only one series as shown in FIG.
[0031]
Although the two-series simultaneous syndrome calculation circuit has been described above, the same effect can be obtained by using a circuit that can simultaneously perform three-series, four-series,...
[0032]
FIG. 5 is a block diagram showing a configuration of a digital signal processing circuit according to the second embodiment of the present invention.
[0033]
In this figure, 501 is a 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit, 508 is a syndrome arithmetic circuit with xα ^ i output, 509 is a syndrome arithmetic circuit, 103 is a Sn arithmetic circuit, and 502 is × α ^. m or × α ^ 2m Sm arithmetic circuit with a selector, 105 is an S0 arithmetic circuit, 506 is an 8-bit data input terminal for upper byte data, 507 is an 8-bit data input terminal for lower byte data, and 107 is GF (2 ^ 8) Upper addition circuit, 108 is an 8-bit register with reset, enable, 109 is a multiplication circuit of α ^ n, 503 is a multiplication circuit of α ^ m, 111 is a multiplication circuit of α ^ 0, 112 is an 8-bit register with enable, 113 is an enable signal input terminal, 114 is a reset signal input terminal, 115 is a select signal input terminal, 5 5 the mode signal input terminal, 116 is an AND circuit, OR circuit 504, the select circuit 117, 8 × (n + 1) bit output terminal 118.
[0034]
However, the 8-bit data input from the upper byte 8-bit data input terminal 506 and the lower byte 8-bit data input terminal 507 handled here is:
Generator polynomial: G1 (x) = (x−α ^ n) (x−α ^ n−1)... (X−α ^ 0), or two sets of RS codes (l, n + 1)
Generator polynomial: G2 (x) = (x−α ^ m) (x−α ^ m−1)... (X−α ^ 0) 2-byte set data (D2i + 1, D2i). (The data string of the RS (k, m + 1) code is (Dk-1, Dk-2, ..., Dm + 1, Dm, ..., D0).)
In this one-sequence two-byte simultaneous processing or two-sequence simultaneous processing syndrome arithmetic circuit 501, the value of the mode signal input from the mode signal input terminal 505 is L, and two RS codes having the same code length at the same timing are higher. When input from the 8-bit data input terminal 506 for bytes and the 8-bit data input terminal 507 for lower bytes, the operation is the same as that of the 2-series simultaneous syndrome calculation circuit 101 of FIG. When the value of the mode signal is H, from the upper byte 8-bit data input terminal 506 and the lower byte 8-bit data input terminal 507 (Dk-1, Dk-2,..., Dm + 1, Dm,..., D0). When 2-byte set data of the represented RS code is input in the order of (Dk-1, Dk-2), (Dk-3, Dk-4), ..., (D1, D0), xα ^ i is output Different data strings (Dk-1, Dk-3,..., D1) and (Dk-2, Dk-4,..., D0) are input to the syndrome calculation circuit 508 and the syndrome calculation circuit 509, respectively.
[0035]
..., Sm arithmetic circuit 502,..., S0 arithmetic circuit 105 in the syndrome arithmetic circuit 508 with .alpha. ^ I output, D2i + 1 is simultaneously input to Si (i = n,... , M + 1) arithmetic circuit, Sj (j = m,..., 0) arithmetic circuit is obtained by adding the data output from the 8-bit register 108 with reset and enable included in the circuit and the data obtained by multiplying α ^ i. , The reset signal included in the circuit, the data output from the enable 8-bit register 108 is added to the data obtained by multiplying α ^ j twice, and the enable signal input from the enable signal input terminal 113 is When it is H, the 8-bit register 108 with reset and enable is taken in at the rising timing of the clock.
[0036]
Similarly, D2i is simultaneously input to n + 1 circuits of the Sn operation circuit 103,..., Sm operation circuit 502,..., S0 operation circuit 105 in the syndrome operation circuit 509, and Si (i = n,..., M + 1). In the arithmetic circuit, the data included in the reset and enable 8-bit register 108 included in the circuit is added to the data obtained by multiplying α ^ i, and in the Sj (j = m,..., 0) arithmetic circuit, After adding the data output from the 8-bit register 108 with reset and enable included in the circuit to the data obtained by multiplying α ^ j twice, the enable signal input from the enable signal input terminal 113 is H. At the rising edge of the clock, the 8-bit register 108 with reset and enable is fetched.
[0037]
The signal taken into the 8-bit register 108 with reset and enable becomes an output from the Si (i = n,..., 0) arithmetic circuit, and the syndrome arithmetic circuit 508 with xα ^ i output receives j (≦ For m), a value obtained by multiplying the value of the 8-bit register 108 with reset and enable by xα ^ j is also output.
[0038]
After all RS codes have been input, that is, after k / 2 pieces of data have been input to each syndrome calculation circuit, the output after xα ^ j of the syndrome calculation circuit 508 with xα ^ i output and The output value for j (≦ m) of the syndrome arithmetic circuit 509 is
Sj — 508 = Dk−1 · α ^ (j (k−1)) + Dk−3 · α ^ (j (k−3)) +... + D1 · α ^ j,
Sj — 509 = Dk−2 · α ^ (j (k−2)) + Dk−4 · α ^ (j (k−4)) +.
[0039]
Thus, when the mode signal input from the mode signal input terminal 505 is H, the (Sm_1, Sm-1_1,..., S0_1) and (Sm_2, Sm-1_2) are output from the 8 × (n + 1) -bit output terminal 118. .., S0_2), and the syndrome (Sm, Sm-1,..., S0) obtained by adding them together is output.
[0040]
As described above, the one-sequence two-byte simultaneous processing or the two-sequence simultaneous processing syndrome calculation circuit 501 simultaneously processes the one-sequence RS code for two bytes when the mode signal input from the mode signal input terminal 505 is H, and the mode signal is When L, it can be seen that two series of RS codes are processed simultaneously.
[0041]
FIG. 10 is a block diagram showing the configuration of a digital disk reproducing apparatus having an error correction circuit 1005 including the 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit 501 of FIG.
[0042]
First, the format of digital data written on the disk 1001 in FIG. 10 will be described. A signal recorded on the disk 1001 is generated by sequentially configuring “data sector 601”, “ECC block 701”, “recording sector 802”, and “physical sector 901” from the main data.
[0043]
FIG. 6 is a diagram showing the configuration of one data sector 601.
[0044]
The flow from the main data until one data sector 601 is created will be described with reference to FIG.
[0045]
First, 2048-byte main data 602 divided in time series is added to 4-byte identification data (ID) 603, 2-byte ID error detection code (IED) 604, and 6-byte copyright management information (CPR_MAI) 605. Is added to the head of the main data. Further, one data sector 601 is generated by adding a 4-byte error detection code (EDC) 606 to the 2060-byte data at the end of the data 203.
[0046]
FIG. 7 is a diagram showing the configuration of one ECC block 701.
[0047]
The flow from the 16 data sectors 601 to the creation of one ECC block 701 will be described with reference to FIG.
[0048]
First, a 16-byte outer code (PO 702) is added to each 172-byte column of the 16 data sectors 601. Next, a 10-byte inner code (PI 703) is added to each of the generated 208 rows. The data field composed of 208 rows × 182 bytes generated in this way is referred to as 1 ECC block 701.
[0049]
However, the PI code is
Generator polynomial GPI (x) = (x−α ^ 9) (x−α ^ 8) (x−α ^ 0)
RS (182, 172, 11) code consisting of
The PO code is
Generator polynomial GPO (x) = (x−α ^ 15) (x−α ^ 14)... (X−α ^ 0),
RS (208, 192, 17) code consisting of
[0050]
FIG. 8 is a diagram showing the configuration of the recording sector 802.
[0051]
One recording sector 801 is a data field of 182 bytes × 13 rows in which one row of PO 702 added when one ECC block 701 is generated is combined under one data sector of 12 rows including PI 703.
[0052]
FIG. 9 is a diagram showing the configuration of one physical sector 901.
[0053]
A flow from one recording sector 801 to one physical sector being created will be described with reference to FIG.
[0054]
One recording sector 801 is first divided vertically into two (one divided block is 91 bytes × 13 rows), and as shown in FIG. 9, a 32-bit SYNC code 902 (SY0 to SY7) is placed at the head of each row. Is added. Then, the data divided into two is recombined, and the 8/16 modulation (8-bit data is stored on the basis of a data table) for suppressing the DC component of the 182 × 13-byte data excluding the SYNC code 902. To a 16-channel bit). The 2976 × 13-bit data created in this way is one physical sector 901, and this signal becomes a disk recording signal and is written on the disk 1001 in FIG.
[0055]
A digital disk reproducing apparatus having an error correction circuit 1005 including a one-sequence two-byte simultaneous processing or two-sequence simultaneous processing syndrome arithmetic circuit 501 shown in FIG. 10 will be described.
[0056]
In FIG. 10, 1001 is a disk, 1002 is a pick, 1003 is a demodulation circuit, 1004 is a RAM, 105 is an error correction circuit having 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit, 1006 is an output circuit, and 1007 is control. A circuit, 1008 is a data request signal input terminal, and 1009 is a main data output terminal.
[0057]
Note that the RAM 1004 included in the digital disk reproducing apparatus reads and writes data in units of 2 bytes.
[0058]
In this figure, the digital signal read from the disc 1001 by the pick 1002 is first input to the demodulation circuit 1003. The demodulating circuit 1003 detects the SYNC code 902, performs 8/16 demodulation, transmits a data write request signal to the RAM 1004 to the control circuit 1007, and transmits the SYNC code 902 to the address sent from the control circuit 1007 to the RAM 1004. Write two bytes of data at once. When the demodulation circuit 1003 writes the data of the 1 ECC block 701 to the RAM 1004, the control circuit 1007 causes the error correction circuit 1005 to perform error correction processing in the order of PI correction for 208 series and PO correction for 172 series.
[0059]
The control circuit 1007 sets the mode signal of the error correction circuit 1005 to H during error correction for the 208 series PI code, and performs error correction from the RAM 1004 when data is not written from the demodulation circuit 1003 to the RAM 1004. By causing the circuit 1005 to output 2 bytes of data and simultaneously setting the enable signal input to the error correction circuit 1005 to H, the syndrome arithmetic circuit can capture the 2 bytes of data included in the PI code at one time, and the PI code Syndrome calculation processing is performed for.
[0060]
During the PO correction, the control circuit 1007 sets the value of the mode signal of the error correction circuit 1005 to L, and inputs 2-byte data in the PI direction from the RAM 1004 to the error correction circuit 1005 in the same way as during PI correction. At the same time, the enable signal is set to H to cause the syndrome arithmetic circuit to perform two series of PO corrections simultaneously. In addition, the control circuit 1007 in this figure corrects an error on the RAM 1004 based on a reset signal that tells the error correction circuit 1005 the switching timing of pipeline processing and the error position obtained by the error correction circuit 1005. A control signal for generating a control signal for the RAM 1004 and a data request for an ECC block subjected to error correction processing in response to an external data request input from a data request signal input terminal 1008. Control is performed such as outputting to the output circuit 1006 when the RAM 1004 is not accessed from 1005.
[0061]
Even in a device in which a data temporary storage circuit such as the RAM 1004 is accessed from a plurality of circuits as shown in this figure, if the 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit 501 of FIG. Since 1005 can halve the number of accesses necessary for reading data from the RAM 1004, the error correction processing time can be shortened as shown in FIGS.
[0062]
Further, when the data reading from the disk 1001 is speeded up and the data processing speed in the apparatus is increased, the speeding up method of each processing circuit, the increase in the number of RAM accesses from each processing circuit, and the like become problems. By using this circuit, the number of accesses from the error correction circuit 1005 to the RAM 1004 can be reduced, so that the error correction process can be speeded up as described with reference to FIG. Therefore, the present invention is very effective for increasing the speed of the system having the circuit configuration as shown in FIG.
[0063]
In this embodiment, a digital signal circuit having a syndrome arithmetic circuit capable of performing two-sequence simultaneous calculation and one-sequence two-byte simultaneous calculation has been mainly described. However, all multiple-sequence simultaneous calculations such as 3, 4, 5,. The same effect can be obtained by having a syndrome calculation circuit capable of simultaneous calculation of multiple series and multiple bytes.
[0064]
The effect of the syndrome circuit described can also be obtained with a circuit configuration other than the digital data reproducing apparatus of FIG.
[0065]
【The invention's effect】
As described above, according to the present invention, in a data reproduction processing apparatus that receives data that is subjected to error correction in a plurality of directions, a syndrome arithmetic circuit included in the error correction circuit can receive a plurality of data strings or a plurality of data on the same data string. Even when the number of data that needs to be processed changes by selecting the syndrome to be used in the next calculation from the obtained multiple syndromes and outputting it from the syndrome calculation circuit, the memory access of the error correction circuit It is possible to reduce the number of times, speed up the error correction processing, and speed up the processing of the digital signal processing circuit having this circuit.
[Brief description of the drawings]
FIG. 1 is a diagram of a two-sequence simultaneous syndrome calculation circuit.
FIG. 2 is a diagram of an error correction circuit having a two-series simultaneous syndrome calculation circuit.
FIG. 3 is a diagram showing a relationship between a sequence number and time in an error correction circuit having an existing syndrome arithmetic circuit.
FIG. 4 is a diagram showing a relationship between a sequence number and time in an error correction circuit having a two-sequence simultaneous syndrome calculation circuit.
FIG. 5 is a diagram of a 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit.
FIG. 6 is a diagram of one data sector.
FIG. 7 is a diagram of one ECC block.
FIG. 8 is a diagram of a recording sector.
FIG. 9 is a diagram of one physical sector.
FIG. 10 is a diagram of a disk playback device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Two series simultaneous syndrome arithmetic circuit, 102 ... Syndrome arithmetic circuit, 103 ... Sn arithmetic circuit, 104 ... Sn-1 arithmetic circuit, 105 ... S0 arithmetic circuit, 106 ... 8-bit data input terminal, 107 ... GF (2 ^ 8 ) Upper addition circuit, 108... Reset, 8-bit register with enable, 109... Αn multiplication circuit, 110... Αn-1 multiplication circuit, 111 .alpha.0 multiplication circuit, 112. Bit register 113 ... Enable signal input terminal 114 ... Reset signal input terminal 115 ... Select signal input terminal 116 ... AND circuit 117 ... Select circuit 118 ... 8 × (n + 1) bit output terminal 201 ... Error correction circuit 202 ... second arithmetic circuit, 203 ... third arithmetic circuit, 204 ... error correction circuit, 206 ... error correction acceptance No. input terminal, 207... Error position output terminal, 208... Error value output terminal, 501... 1 series 2 byte simultaneous processing or 2 series simultaneous processing syndrome arithmetic circuit, 502... With xα ^ m or xα ^ 2m selector Sm arithmetic circuit, 503... Αm multiplication circuit, 504... OR circuit, 505... Mode signal input terminal, 506... 8 bit data input terminal for upper byte data, 507. … × α ^ i syndrome output circuit, 509… syndrome operation circuit.

Claims (3)

An input means for inputting a first data string forming an RS code and a second data string different from the first data string;
An error correction circuit for performing an error correction process on the first data string and the second data string input by the input means;
In a digital signal processing circuit having output means for outputting the first data string and the second data string subjected to the error correction processing,
The error correction circuit performs a process for the first data string and a process for the second data string in parallel for the syndrome calculation process of the error correction process, and the calculation process excluding the syndrome calculation process of the error correction process Performs processing on the second data string after processing on the first data string,
The digital signal processing circuit, wherein the output means includes an output means for outputting the second data string subjected to the processing after outputting the first data string subjected to the error correction processing.   2. The digital signal processing circuit according to claim 1, wherein a circuit that generates a position polynomial and an error evaluation polynomial of a data sequence based on a syndrome of the data sequence, as the arithmetic processing excluding the syndrome arithmetic processing of the error correction processing, and the data A circuit for obtaining an error position and an error value of each data string based on a column position polynomial and an error evaluation polynomial, and outputting the first data string and then performing the processing An output means for outputting a sequence outputs an error position and an error value of a data sequence.   A demodulating circuit for demodulating data read from a recording medium, a memory circuit for temporarily storing data demodulated by the demodulating circuit, and data stored in the memory circuit are inputted, and the inputted data And a digital signal processing circuit according to claim 1 for performing error correction processing on the disk, and reproducing the data subjected to the error correction processing.

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