JP3700561B2 - Buffer control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a buffer control device suitable for a buffer circuit for absorbing a data transfer speed difference between a microcomputer and a peripheral circuit, particularly when applied to a double buffer configuration.
[0002]
[Prior art]
An apparatus using a flash memory card or the like requires an interface circuit for transferring data between the card and the microcomputer. In general, microcomputers that execute applications are often faster than memory cards with smaller bus widths and slower transfer speeds. The interface circuit is usually provided with a buffer for absorbing the transfer speed difference so that the performance of the entire device is not reduced by data transfer with a low-speed memory card.
[0003]
First, a conventional interface circuit having a single buffer configuration will be described. FIG. 5 is a block diagram showing a buffer control unit having a single buffer configuration. In FIG. 5, a system bus 1 is an external bus of a host microcomputer composed of addresses, data, read / write signals, interrupt signals, etc., and a host interface (Host I / F) 2 is an address decode of the system bus 1 , A logic circuit that performs read / write timing adjustment and accesses the memory 4 according to writing and reading of a host microcomputer (not shown) as a first control circuit, and the peripheral circuit interface 3 transmits and receives data to and from a memory card or the like The memory 4 is a buffer for absorbing the transfer rate, and the monitoring unit 5 is a host microcomputer side access and second control circuit which is the first control circuit. Monitors access via peripheral circuit interface 3 and temporarily stores data in memory 4 Monitor, a logic circuit for outputting a full (Full) / empty (Empty) signal.
[0004]
FIG. 6 shows the state transition of the buffer when data transfer is performed with the above configuration. First, the host microcomputer instructs the hardware to initialize the buffer, sets the buffer to an empty state (1), and then instructs the peripheral circuit interface 3 to transfer data. As a result, the peripheral circuit interface 3 starts writing data to the buffer as shown in state (2), and interrupts the writing when the buffer is full as in state (3). At this time, the monitoring unit 5 detects that the memory is full, outputs a Full signal, and generates an interrupt signal IRQ. As a result, the host microcomputer confirms that the buffer is full, and the host microcomputer starts reading data via the host interface 2 as in the state (4), and the buffer becomes empty as in the state (5). Continue reading. When the memory 4 becomes empty, the peripheral circuit interface 3 resumes the next data writing.
[0005]
By repeating the above operation, data from the peripheral circuit is sequentially transferred to the host microcomputer side. In other words, writing to and reading from the memory is divided in terms of time, and after the peripheral circuit writes slowly, the host microcomputer reads it quickly and continuously to absorb the speed difference. When data is sequentially sent from the host microcomputer side to the peripheral circuit side, the operation is reversed, and the peripheral circuit only needs to read the peripheral circuit slowly after the host microcomputer writes it quickly and continuously. Such state transition can be easily realized by detecting the amount of data stored in the buffer memory by the host microcomputer and the peripheral circuit which are external control circuits. In the case of transfer from the peripheral circuit to the host microcomputer, the peripheral circuit writes when the memory 4 is empty, and reads when the host microcomputer is full. In the case of transfer from the host microcomputer to the peripheral circuit, the host microcomputer performs writing when the memory 4 is empty, and the peripheral circuit performs reading when the memory 4 is full.
[0006]
There is also an interface circuit having a double buffer configuration in which buffer memories are duplicated for the purpose of further improving transfer efficiency with respect to the single buffer configuration as described above. FIG. 7 shows a block diagram of an interface circuit having a double buffer structure. In FIG. 7, the system bus 1, the host interface 2, and the peripheral circuit 3 are the same as in the case of the single buffer configuration, the memories 41 and 42 are two-plane buffers for absorbing the transfer rate, and the monitoring units 51 and 52 are the first ones. This is a logic circuit that monitors the access on the host microcomputer side which is the control circuit and the access of the peripheral circuit which is the second control circuit, and monitors the amount of data temporarily stored in the memories 41 and 42, respectively.
Switching units 6 and 7 are switching units for switching connection between the access on the host microcomputer side and the access on the peripheral circuit side to the memories 41 and 42, respectively.
[0007]
A description will be given of buffer switching when data transfer is performed with the above configuration. First, after confirming that the two buffer memories are empty, the host microcomputer instructs the peripheral circuit 3 to transfer data. In the write mode, the peripheral circuit 3 detects the storage amounts of the two memories and, if there is an empty memory, controls the switch 7 to connect to the empty memory and write data until it is full. On the other hand, the host interface 2 detects the storage amounts of the two memories, and generates an interrupt signal as in the single buffer configuration when one of the memories becomes full. In response to this interrupt, the host microcomputer controls the switch 6 to connect to a full memory and reads data from the memory.
[0008]
By repeating the above operation, data from the peripheral circuit is sequentially transferred to the host microcomputer side. That is, the double buffering allows the host read operation and the peripheral circuit 3 write operation to be performed at the same time, thereby improving the transfer efficiency as compared with the single buffer configuration. Such state transition is realized by the host microcomputer and the peripheral circuit detecting the amount of data stored in the two buffer memories.
In the case of transfer from the peripheral circuit to the host microcomputer, the peripheral circuit 3 writes when one of the two memories becomes empty, and the host microcomputer performs reading when either becomes full. In the case of transfer from the host microcomputer to the peripheral circuit, the host microcomputer performs writing when one of the memories becomes empty, and the peripheral circuit 3 reads when either becomes full.
[0009]
[Problems to be solved by the invention]
However, the double buffer configuration has a problem that the host microcomputer has to perform memory control that is clearly different from the single buffer configuration, as represented by memory switching control. Similarly, the peripheral circuit requires a circuit configuration dedicated to the double buffer configuration. That is, there is a problem that an external control circuit (including a host microcomputer) that accesses the buffer memory needs to be prepared separately for the single buffer and the double buffer.
[0010]
The single buffer configuration and the double buffer configuration are in a trade-off relationship between performance and cost. Since the cost increases if the double buffer is made with emphasis on performance, the configuration should be selected according to the purpose of use of the device. If a circuit and software other than the buffer are prepared separately, it becomes a factor of higher cost, so the external control circuit including the host microcomputer software remains completely the same, and only the buffer part is used according to the purpose of use of the device. It is desirable to be able to construct an optimal system configuration simply by changing.
[0011]
An object of the present invention is to provide a buffer control circuit that does not require any distinction between a single buffer configuration and a double buffer configuration for an external control circuit that accesses a buffer.
[0012]
[Means for Solving the Problems]
In order to solve this problem, the buffer control device of the present invention replaces the connection destination when one memory is already filled with data and the other memory becomes empty, or one of the memories already has Connection switching means for switching the connection destination when the other memory is filled with data in an empty state, or for switching the connection destination when the other memory is empty at the same time that one memory is filled with data And information selection means for selecting one memory state signal from among the signals indicating the storage state such as full or empty.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
The first aspect of the present invention, the control circuit of the write side writes the data into the buffer memory in response to the state signal indicating that the memory state while detecting the stored data amount in the buffer memory is empty, the read side of the control circuit, the read buffer memory or La Defense over data in response to the state signal indicating that the memory state is full while detecting stored data amount in the buffer memory, the buffer control for transmitting block data by repeating it The buffer memory connected to the control circuit on the write side and the read corresponding to the storage state of each of the double buffer memories for temporary storage composed of two buffer memories being full or empty a connection switching means for switching the buffer memory connected to the control circuit side, the storage state is fully to the control circuit of the write side And a status signal for notifying the read-side control circuit whether the storage state is full or empty for the switching operation of the connection switching means. In addition, there is provided information selection means for switching from the status signal of one buffer memory to the status signal of the other buffer memory , and either one of the buffers for the control circuit on the write side and the control circuit on the read side The control circuit on the write side and the read side are connected by notifying a state signal indicating whether the storage state of the memory is full or empty, and connecting only one of the buffer memories. the control circuit of the storage state of the buffer memory in response to the state signal indicating either empty or full, the write side writes emptied write , By exactly the same transmission rules as a single buffer memory of the read side becomes full it reads, but also capable of writing or reading from the double buffer memory.
[0014]
The second invention of the present invention is a double buffer memory comprising two memories in addition to the first invention, wherein the connection switching means is in a state where one memory is already filled with data and When the other memory becomes empty, the connection destination is changed, or when one memory is already empty and the other memory is filled with data, the connection destination is changed, or data is stored in one memory. At the same time, the connection destination is switched when the other memory becomes empty.
[0015]
The third invention of the present invention is a double buffer memory composed of two memories in addition to the first invention, wherein the connection switching means fills up the connected memory at the time of writing. When switching, the other memory is switched, and at the time of reading, switching to the other memory is performed when the connected memory becomes empty.
[0016]
According to a fourth aspect of the present invention, in addition to the first aspect, the information selecting means selects a status signal of the connected memory in a transfer state where the residual transfer amount exceeds the memory capacity, and the residual transfer amount In the transfer state in which is less than the memory capacity, the state signal of the read memory can be selected.
[0017]
According to a fifth aspect of the present invention, in addition to the first aspect, an event signal such as an interrupt request signal is generated in the external control circuit at the timing when the connection is switched by the connection switching means.
[0019]
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0020]
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a buffer control apparatus according to Embodiment 1 of the present invention. Components having the same configuration as the conventional example are denoted by the same reference numerals and description thereof is omitted.
[0021]
In FIG. 1, a switching detector 8 is a circuit that generates a buffer memory switching signal from the storage states of two buffer memories, and switching devices 9 and 10 select one of the storage state signals of two buffer memories and This is a switch circuit that delivers the control circuit to the host microcomputer side and the peripheral circuit side.
[0022]
The switching control of the buffer memory with the above configuration will be described using the state transition of the buffer memory in FIG. First, the host microcomputer instructs the hardware to initialize the buffers, and sets both buffers to an empty state (1). In this initialization, for example, as shown in the state (1) in FIG. 2, the access on the peripheral circuit side is connected to the memory 41, and the access on the host microcomputer side is connected to the memory 42.
[0023]
Next, the host microcomputer instructs the peripheral circuit 3 to transfer data, and when the peripheral circuit 3 starts writing data to the memory as shown in the state (2), the buffer is full as in the state (3). Circuit 3 interrupts the writing. At this time, the switching detector 8 detects that the memory 41 is full when the memory 42 is empty, and reverses the memory connection relationship. That is, as shown in the transition from the state (3) to the state (4) in FIG. 2, the connection on the peripheral circuit side is switched from the memory 41 to the memory 42, and the state signal is also changed from the full state of the memory 41 to the memory by the switch 10. 42 switches to the empty state. Therefore, the peripheral circuit 3 recognizes that the memory is empty, resumes data writing, and writes data to the memory 42 as in the state (5).
[0024]
On the other hand, in the transition from the state (3) to the state (4), the memory connected to the host microcomputer side is also switched from the memory 42 to the memory 41, and the signal indicating the storage state of the memory is also sent to the empty state of the memory 42 by the switch 9. To the memory 41 full state. The change to the full state generates an interrupt signal IRQ. Note that the interrupt signal may be directly generated by the switching signal.
[0025]
In response to this interrupt, the host microcomputer confirms that the buffer is full, and the host microcomputer starts reading data via the host interface 2 as shown in state (5). Thus, in the state (5), writing from the peripheral circuit and reading from the host microcomputer can be executed simultaneously.
[0026]
The next state (6) shows a case where the writing from the peripheral circuit 3 is completed first and the memory 42 is full. In this case, since the memory 41 is not yet empty, the memory connection is not changed, and the peripheral circuit 3 is in a state where writing is interrupted, and the memory 41 becomes empty as shown in the transition from the state (7) to the state (8). At that point, the memory connection is switched. As a result of the replacement, the peripheral circuit determines that the memory is empty, and the host microcomputer determines that the memory is full, and continues data transfer.
[0027]
By repeating the above operation, data from the peripheral circuit is sequentially transferred to the host microcomputer side. When data is sequentially sent from the host microcomputer side to the peripheral circuit side, only the reverse operation is performed.
[0028]
Such a state transition is such that the host microcomputer, which is an external control circuit, and the peripheral circuit detect the amount of data stored in the buffer memory in exactly the same way as in the single buffer configuration, and write when it is empty and read when it is full. There is no special judgment as a double buffer.
[0029]
As described above, according to the present embodiment, the connection of the buffer memory is switched under an appropriate condition, and at the same time, the signal indicating the memory storage state necessary for the buffer access control is switched in accordance with the switching and is interfaced to the external control circuit. By doing so, a double buffer configuration can be realized with the same external control circuit as the single buffer configuration.
[0030]
In the present embodiment, the method of switching the two switches on the host microcomputer side and the peripheral circuit side simultaneously and mutually has been described. However, it is also possible to switch the connection when each becomes independently full or empty. The effect is obtained.
[0031]
In this embodiment, the operation at the end of data transfer of an external control circuit such as a host microcomputer is not particularly mentioned. However, depending on the configuration of the host microcomputer and peripheral circuits, it is necessary to recognize that the transfer has ended. It is also assumed. For example, it can be considered that the end of the transfer is detected by detecting that the recipient has read the last data written in the buffer memory, and that the next operation is started. When the external control circuit has such a configuration but has a single buffer configuration, the memory to be connected is fixed. Therefore, if an empty state is detected on the writing side, all data is transferred. However, in the double buffer configuration, if the same determination as the single buffer is made with the configuration of the present embodiment, the connection of the buffer memory is switched, so whether or not the reading side has read the last data is determined by the connection on the writing side. Cannot be determined by looking at the remaining memory. Accordingly, as shown in FIG. 3, the problem is solved by providing a final control unit 11 that controls the switch circuits 9 and 10 that select the storage state signal so as not to be inverted during the final transfer. Other configurations are the same as those shown in FIG.
[0032]
As a result, although the memory connection destination is changed in the state transitions shown in FIGS. 4 (7) to (8), the memory state signal connected to the read operation side is selected as the storage state signal as shown by the dotted line in the figure. The Thereby, the host microcomputer as the external control circuit and the peripheral circuit can recognize the state (10) in FIG. 4 in which the last written data is read and the two buffer memories are all empty.
[0033]
【The invention's effect】
As described above, according to the present invention, buffer memory connection switching is performed under appropriate conditions, and at the same time, a signal indicating a memory storage state necessary for buffer access control is switched to interface with the external control circuit. This makes it possible to perform correct memory access control without being conscious of whether it is a single buffer configuration or a double buffer configuration, and a buffer configuration suitable for the required specifications of the entire system can be easily realized by changing only the memory section. The effect is great.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a buffer control device according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing transition of a buffer state of the buffer control device. FIG. 4 is a schematic diagram showing a transition of a buffer state when a transfer end determination is made. FIG. 5 is a block diagram showing a buffer controller of a conventional single buffer configuration. FIG. 6 is a conventional single buffer. FIG. 7 is a block diagram showing a conventional buffer control device with a double buffer configuration.
DESCRIPTION OF SYMBOLS 1 System bus 2 Host interface 3 Peripheral circuit interface 4, 41, 42 Buffer memory 5, 51, 52 Monitoring part 6, 7 Switch 8 Switching detector 9, 10 Switch circuit 11 Final transfer control part

Claims (5)

The control circuit of the write side writes the data into the buffer memory in response to the state signal indicating that the memory state while detecting the stored data amount in the buffer memory is empty, the control circuit of the read side, a buffer memory storage state while detecting the stored amount of data read buffer memory or La Defense over data in response to the state signal indicating that the full, the buffer control for transmitting block data by repeating it,
A buffer memory connected to the control circuit on the writing side and a memory on the reading side corresponding to the storage state of whether each of the double buffer memories for temporary storage composed of two buffer memories is full or empty Connection switching means for replacing the buffer memory connected to the control circuit ;
A status signal for notifying the write-side control circuit whether the storage state is full or empty, and a notification for notifying the read-side control circuit whether the storage state is full or empty. And an information selection means for switching the status signal from the status signal of one buffer memory to the status signal of the other buffer memory in accordance with the switching operation of the connection switching means ,
A status signal indicating whether the storage state of one of the buffer memories is full or empty is notified to the control circuit on the write side and the control circuit on the read side, and the one of the buffers By connecting so that only memory is accessible,
The control circuit on the write side and the control circuit on the read side write according to a state signal indicating whether the storage state of the buffer memory is full or empty, the write side writes when it becomes empty, and the read side reads when it becomes full A buffer controller that can write to or read from a double buffer memory according to the same transmission rule as a single buffer memory. A double buffer memory comprising two memories, wherein the connection switching means switches the connection destination when the data is already filled in one memory and the other memory becomes empty, or When the other memory is filled with data while the other memory is already empty, the connection destination is replaced, or when one memory is filled with data and the other memory is empty, the connection destination is changed. The buffer control device according to claim 1 to be replaced. A double buffer memory composed of two memories, wherein the connection switching means switches to the other memory when the connected memory is full at the time of writing, and connects at the time of reading. 2. The buffer control device according to claim 1, wherein when the memory being used becomes empty, switching to the other memory is performed.   The information selection means can select the status signal of the connected memory when the residual transfer amount exceeds the memory capacity, and can select the status signal of the read memory when the residual transfer amount is less than the memory capacity. The buffer control device according to claim 1.   2. The buffer control device according to claim 1, wherein an event signal such as an interrupt request signal is generated in the external control circuit at a timing when the connection is switched by the connection switching means.

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