JP3679425B2 - Recording device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a recording apparatus that performs recording on a recording medium by time division driving.
[0002]
[Prior art]
As a system for recording on a recording medium using a recording head having a plurality of recording elements, there are a dot impact recording system, a thermal recording system, an ink jet recording system, and the like. In these methods, as the number of recording elements increases, instantaneous power consumption for driving increases, leading to an increase in the size of the power supply device and an increase in the current capacity of the power supply power supply line.
[0003]
In addition, in the ink jet recording method, when a large number of nozzles (recording elements) are driven at the same time, the shock wave generated by each nozzle causes a large interference in the common liquid chamber on the ink supply side in the recording head, resulting in unstable ejection. .
[0004]
As a method for solving this problem, there is a method that is conventionally used in many cases. The recording element is divided into a plurality of groups and divided and driven within a driving cycle. In this method, power consumption for driving is dispersed within the driving cycle, and the problem of the power supply system is reduced, and in the ink jet recording method, shock wave interference is reduced.
[0005]
[Problems to be solved by the invention]
However, what is originally recorded at the normal pixel position of the recording medium only after the simultaneous driving is performed, the image is disturbed because the recording position is different from the normal pixel position as shown in FIG. The example of FIG. 15 is a case where the number of divisions is four and equal division driving is performed. The broken line intersection is the normal recording position, ● is the position where ink droplets landed by the recording head according to the image information, ○ is originally not appeared on the recording paper, but ink droplets did not land according to the image information Indicates the position. This example is an example in which vertical ruled lines are printed, and it can be seen that image disturbance is large if the divided drive timing is widely dispersed within the drive cycle.
[0006]
For this reason, the divided drive timing cannot be widely dispersed, and FIG. 16 shows an example in which the divided drive is equally divided within a half of the drive cycle. Although the image disturbance is reduced, it still exists, and the effect of suppressing the interference in the common liquid chamber is reduced by half.
[0007]
The present invention further reduces the problem of the power supply system and the shock wave interference in the case of the ink jet recording method by widely dividing the divided drive timing within the drive cycle, and a recording apparatus that does not disturb the image even when the divided drive is performed. The purpose is to provide.
[0008]
[Means for Solving the Problems]
The recording apparatus of the present invention includes a print buffer that holds recording data to be transferred to the recording head as a unit of address, and a plurality of recordings corresponding to a plurality of ink colors that are recorded by a plurality of recording elements. An element group is arranged in a straight line with an interval of a predetermined number of dots equal to the predetermined number of data, and each recording element group is composed of a number of recording elements that is a natural number multiple of the predetermined number of dots. The recording element group arranged so as to obliquely intersect a plurality of recording rows on which recording is to be performed, relative to the recording medium in the arrangement direction of the recording rows. A recording device for recording an image by moving the recording device,
A first address designating circuit for sequentially designating a read address of the recording data in a direction along the recording sequence; a second address designating circuit for shifting the designation of the address to an address of an adjacent recording sequence; and the first address designating The total of the number of recording elements of one recording element group and the number of predetermined dots adjacent to each other is the predetermined number of times of addressing of the circuit. The predetermined number of data corresponding to the address unit The address is shifted by the second addressing circuit every time the addressing is performed a predetermined number of times that is a natural number multiple of the recording element, so that the plurality of recording columns intersecting the column of the recording elements can be handled. An address switching circuit for transferring data, and a recording means for recording data in an adjacent recording row for each data specified by the predetermined number of times by the first address specifying circuit.
[0009]
[Action]
According to the above configuration, the address reading corresponding to the head structure is specified by the first address specifying circuit, the second address specifying circuit, and the address switching circuit, whereby a predetermined interval is set between the recording element groups corresponding to the ink colors. Even if the head is vacant, it is possible to reduce the load on the CPU and transfer data corresponding to the plurality of intersecting recording rows to the rows of the recording element group.
[0010]
【Example】
Embodiments of the present invention will be specifically described below with reference to the drawings.
[0011]
FIG. 1 is a block diagram showing a circuit configuration applicable to the recording apparatus of the present invention. In FIG. 1, 1 is a CPU, 2 is a data transfer circuit, 3 is a RAM, and 4 is a print head.
[0012]
The CPU 1 creates print data and stores it in a print buffer in the RAM 3. Data transfer between the CPU 1 and the RAM 3 is performed via the data transfer circuit 2. The print data stored in the print buffer is read by the data transfer circuit 2 and transferred to the print head 4. Data transfer between the data transfer circuit 2 and the RAM 3 is controlled by an address signal ADDRESS, a data signal DATA, a read signal READ−, and a write signal WRITE−. Here,-indicates that the signal is low active.
[0013]
The data transfer circuit 2 reads the data in the print buffer in byte units, converts it into serial data, and transfers it to the head 4. The head 4 is an inkjet head in which 128 ink ejection nozzles (ejection ports) are arranged in a row, and has a 128-bit shift register. The serial data transferred from the data transfer circuit 2 is sequentially stored in the shift register, and whether or not each nozzle is driven is selected by this data. By driving the head once, a maximum of 128 dots (for example, black dots) arranged in a vertical line on the recording paper are formed. In this printer, the print head is mounted on a carriage and scanned in the horizontal direction with respect to the recording paper, and the recording paper is conveyed in the vertical direction.
[0014]
FIG. 2 shows a block diagram of an address generation circuit for reading the print buffer in the data transfer circuit 2.
[0015]
In FIG. 2, 11 is a black address (K) register, 12 is a black horizontal offset (KH) register, 13 is a save register, 14 is a selector, 15 is a mask circuit, 16 is an inverting / non-inverting circuit, and 17 is an addition. And 18 is a carry control circuit. Data signals D0 to 15 transfer data written by the CPU1. The address register 11 and the horizontal offset register 12 are connected to the data signals D0 to D15, the address register 11 stores the start address value, and the horizontal offset register 12 stores the horizontal offset value. The CPU 1 manages the setting of the start address and the horizontal offset. Here, black (K) is taken as an example of the print color, but cyan (C), magenta (M), yellow (Y), or the like may be used.
[0016]
The output signals PBA0-18 of the address register 11 are connected to the address signal ADDRESS of the RAM 3 through the output buffer. The save register 13 temporarily stores the value output from the address register 11 and outputs it to the signals LA0-18. The selector 14 selects either PBA0-18 or LA0-18 and outputs it to the signals SA0-18. The mask circuit 15 controls the mask of the output of the horizontal offset register 12. The output value of the mask circuit 15 is 0 in the mask state, and when not in the mask state, the output value of the horizontal offset register 12 is output as it is.
[0017]
The inversion / non-inversion circuit 16 controls inversion / non-inversion of the output of the mask circuit 15. The adder 17 adds the output value of the selector 14 and the output value of the inverting / non-inverting circuit 16 and outputs the result to the signals NPA0 to NPA18. The carry control circuit 18 controls the carry input signal of the adder 17. The signals NPA0 to 18 are input to the address register 11 and used for resetting the address value.
[0018]
FIG. 3 shows the data structure of the print buffer. In FIG. 3, each rectangle indicates 1-byte print data, and an expression in the rectangle indicates an address where each print data is stored. In the equation, K is a start address and KH is a horizontal offset value. The 16-byte data from addresses K to K + 15 is 128-dot print data continuous in the vertical direction, and is printed by driving the print head once. Further, the address of the print data changes by KH per dot in the horizontal direction.
[0019]
FIG. 4 is a timing chart showing the operation of the data transfer circuit 2. The operation of the address generation circuit shown in FIG. 2 will be specifically described with reference to FIG.
[0020]
First, the forward printing, that is, the case where the carriage is scanned from left to right with respect to the recording paper will be described. In FIG. 4, CLK is a clock signal for synchronously moving the address generation circuit, and each part of the address generation circuit changes in synchronization with the rise of CLK. The value of the address register 11 is preset to K, and the value of the horizontal offset register 12 is preset to KH.
[0021]
When the data transfer circuit 2 starts reading the print buffer, the value K of the signals PBA0-18 is output to the address signal ADDRESS of the RAM 3, and a read pulse is output to the read signal READ-. Therefore, the print data is read from the start address K and transferred to the print head 4. At the time of this first reading, the start address K is stored in the save register 13, and the values of the signals LA0 to LA18 become K.
[0022]
Since selector 14 selects signals PBA0-18, the values of signals SA0-18 are equal to PBA0-18. The mask circuit 15 is in a mask state, and the output value is zero. Since the inversion / non-inversion circuit 16 is in the non-inversion state, the output value 0 of the mask circuit 15 is output as it is. Since carry control circuit 18 sets carry, it has the same effect as adding (incrementing) 1 to adder 17.
[0023]
In FIG. 4, the signal with the name of the adder is obtained by adding the output value of the inverting / non-inverting circuit 16 and the output of the carry control circuit 18, and the sum of the signals SA0-18 and this added value is the signal NPA0- 18 is output. Since the addition value is +1, the values of NPA 0 to 18 are K + 1, and this value is fed back to the address register 11. Therefore, the value of the address register 11 is set to K + 1 at the next clock, and the print data is read from the address K + 1 and transferred to the print head 4.
[0024]
Similarly, the value of the address register 11 is sequentially added up to K + 15. Accordingly, the address of the print buffer is continuously read from K to K + 15, and convenient 16-byte print data is transferred to the print head.
[0025]
Since the selector 14 selects the signals LA0-18 at the last clock, the values of the signals SA0-18 are the values K stored in the save register 13. Further, the mask circuit 15 is in an unmasked state and outputs the value KH of the horizontal offset register 12, and the carry control circuit 18 resets the carry, so that the added value becomes KH. Therefore, the values of NPA0 to 18 are K + KH, and this value is set in the address register 11 by the last clock.
[0026]
As shown in FIG. 3, the address K + KH is the print data on the right side of the address K, and the value in the address register 11 is automatically reset to the address on the right side after the print data for one print head drive is transferred. Will be set. Therefore, once the CPU sets the start address before scanning the carriage, it is not necessary to reset the address while scanning the carriage.
[0027]
Next, the case of reverse printing will be described. During reverse printing, as in forward printing, the print buffer address is continuously read from K to K + 15, and 16-byte print data is transferred to the print head. However, at the last clock, the inversion / non-inversion circuit 16 is in the inversion state, and the carry control circuit 18 sets the carry, so that the added value becomes -KH. Therefore, after the transfer of the print data is completed, the value of the address register 11 is set to K-KH, indicating the address on the left side of the address K.
[0028]
The selection state, mask state, and inversion state of the selector 14, mask circuit 15, and inversion / non-inversion circuit 16 are controlled by a timing control circuit (not shown) based on the clock signal CLK.
[0029]
As described above, the data transfer circuit according to the present example automatically reads out the data in the print buffer. Therefore, if the CPU 1 sets the start address once before scanning the carriage, the print is performed while scanning the carriage. There is no need to be involved in reading the buffer. Therefore, the load on the CPU 1 is reduced.
[0030]
Also, by setting the horizontal address change of the print buffer with the horizontal offset register, it is possible to arbitrarily set the continuous address amount in the vertical direction. For example, the CPU 1 can create a print buffer composed of 32 bytes in length, and can print using only print data for 16 bytes in the print buffer at the time of printing. Therefore, the CPU 1 can determine the structure of the print buffer regardless of the number of dots of the print head, and the print buffer can be easily created.
[0031]
Next, another example as a premise of the present invention will be described. The main circuit configuration of the printer provided with the data transfer circuit in this example is the same as that in FIG. 1, and includes a CPU 1, a data transfer circuit 2, a RAM 3, and a print head 4.
[0032]
FIG. 5 shows the dot configuration of the print head in this example. The print head is an inkjet head in which 136 ink ejection nozzles (ejection ports) are arranged in a line, and yellow ink is supplied to 24 nozzles from the top to form yellow dots on the recording paper. Similarly, magenta dots are formed in the next 24 nozzles, cyan dots are formed in the lower 24 nozzles, and black dots are formed in the lowest 64 nozzles. A gap of 8 dots is provided between each color.
[0033]
The print head is provided with a 136-bit shift register, and whether or not to drive each nozzle is determined by data stored in the shift register. Since the shift register is connected with 136-bit data, when transferring data to the print head, print data of yellow 24 dots, magenta 24 dots, cyan 24 dots, and black 64 dots are arranged and sent in this order.
[0034]
FIG. 6 shows a block diagram of an address generation circuit for reading the print buffer in the data transfer circuit 2. In FIG. 6, 101a is a black address (K) register, 101b is a yellow address (Y) register, 101c is a magenta address (M) register, 101d is a cyan address (C) register, 102a is a black horizontal offset (KH) register, 102b Is a yellow horizontal offset (YH) register, 102c is a magenta horizontal offset (MH) register, 102d is a cyan horizontal offset (CH) register, 103 is a selector, 104 is a save register, 105 is a selector, 106 is a selector, 107 is a mask circuit 108 is an inverting / non-inverting circuit, 109 is an adder, and 110 is a carry control circuit.
[0035]
Data signals D0 to 15 transfer data written by the CPU1. Address registers 101a-d and horizontal offset registers 102a-d are connected to data signals D0-15, address registers 101a-d store start address values for each color, and horizontal offset registers 102a-d store horizontal offset values for each color. . The CPU 1 manages the setting of the start address and the horizontal offset. Outputs of the address registers 101a to 101d are selected by the selector 103 and output as signals PBA0 to PBA18. Signals PBA0-18 are connected to address signal ADDRESS of RAM3 through an output buffer. The save register 104 temporarily stores the value output from the selector 103 and outputs it to the signals LA0-18. Selector 105 selects either PBA0-18 or LA0-18 and outputs it to signals SA0-18. The selector 106 selects the outputs of the horizontal offset registers 102a to 102d.
[0036]
The mask circuit 107 controls the mask of the output of the selector 106. The output value of the mask circuit 107 is 0 in the mask state, and when not in the mask state, the output value of the selector 106 is output as it is. The inversion / non-inversion circuit 108 controls inversion / non-inversion of the output of the mask circuit 107. Adder 109 adds the output value of selector 105 and the output value of inversion / non-inversion circuit 108 and outputs the result to signals NPA0-18. The carry control circuit 1110 controls the carry input signal of the adder 17. The signals NPA0 to 18 are input to the address registers 101a to 101d and used for resetting the address value.
[0037]
The data structure of the print buffer is shown in FIG. FIG. 7 is divided into four regions, and each region shows a print buffer for yellow, magenta, cyan, and black in order from the top. A rectangle in each area indicates 1-byte print data, and an expression in the rectangle indicates an address where the print data is stored. In the equation, Y is a yellow start address, YH is a yellow horizontal offset value, M is a magenta start address, MH is a magenta horizontal offset value, C is a cyan start address, CH is a cyan horizontal offset value, K is a black start address, and KH is This is the black horizontal offset value.
[0038]
3 bytes from address Y to Y + 2, 3 bytes from address M to M + 2, 3 bytes from address C to C + 2, and 8 bytes from address K to K + 7 are print data arranged in the vertical direction. The printing is performed by one driving. In addition, the address of the print data is changed by YH for yellow, MH for magenta, CH for cyan, and KH for black for each dot in the horizontal direction.
[0039]
FIG. 8 is a timing chart showing the operation of the address generation circuit of FIG. 6, and shows the case of forward printing. The operation of the address generation circuit shown in FIG. 6 will be specifically described with reference to FIG.
[0040]
In FIG. 8, CLK is a clock signal for synchronously moving the address generation circuit, and each part of the address generation circuit changes in synchronization with the rise of CLK. The values of the address registers 101a to 101d are preset to K, Y, M, and C, and the values of the horizontal offset register 12 are preset to KH, YH, MH, and CH. When the data transfer circuit 2 starts reading the print buffer, the value Y of the address register 101b is first selected by the selector 103 and output to the signals PBA0-18. The values of the signals PBA0-18 are output to the address signal ADDRESS of the RAM 3, and a read pulse is output to the read signal READ-. Therefore, print data is read from the start address Y and transferred to the print head 4. At the time of reading, the start address Y is stored in the save register 104, and the values of the signals LA0-18 are Y.
[0041]
Since selector 105 selects signals PBA0-18, the values of signals SA0-18 are equal to PBA0-18. The selector 106 selects the value YH of the horizontal offset register 102b, but the output value is 0 because the mask circuit 107 is in the mask state. Since the inversion / non-inversion circuit 108 is in the non-inversion state, the output value 0 of the mask circuit 107 is output as it is. Since carry control circuit 110 sets carry, it has the same effect as adding 1 to adder 109.
[0042]
In FIG. 8, the signal with the name of the addition value is obtained by adding the output value of the inverting / non-inverting circuit 108 and the output of the carry control circuit 110, and the sum of the signals SA0-18 and this addition value is the signal NPA0. 18 is output. Since the added value is +1, the values of NPA0-18 are Y + 1, and this value is fed back to the address register 101b.
[0043]
Therefore, the value of the address register 101b is set to Y + 1 at the next clock, and the print data is read from the address Y + 1 and transferred to the print head 4. Similarly, the value of the address register 101b is added up to Y + 2, the address of the print buffer is read out from Y to Y + 2, and 3-byte yellow print data is transferred to the print head.
[0044]
When the address Y + 2 is read, the selector 105 selects the signals LA0-18, so that the values of the signals SA0-18 are the value Y stored in the save register 104. Further, the mask circuit 15 is in an unmasked state and outputs the value YH of the horizontal offset register 102b, and the carry control circuit 18 resets the carry, so the added value becomes YH. Therefore, the values of NPA0-18 are Y + YH, and this value is set in the address register 101b by the last clock.
[0045]
As shown in FIG. 7, the address Y + YH is the print data immediately adjacent to the address Y in the yellow print buffer, and the value of the address register 101b is automatically reset to the address immediately adjacent to the right after the yellow print data is transferred. Will be. Similarly, magenta, cyan, and black print data are sequentially read out. However, for black only, 8-byte print data is transferred to the print head.
[0046]
Each time the transfer of the print data for each color is completed, the value of the address register 101a-d is reset to the address on the right side in each print buffer. Therefore, the CPU 1 sets the start address once before scanning the carriage. There is no need to reset the address while scanning the carriage. When printing in the reverse direction, as in the first embodiment, it is possible to set the values of the address registers 101a to 101d to the address on the left using the inversion / non-inversion circuit 108.
[0047]
Note that the selection state, mask state, and inversion state of the selectors 103, 105, 106, mask circuit 107, and inversion / non-inversion circuit 108 are controlled by a timing control circuit (not shown) based on the clock signal CLK as in the previous example. ing.
[0048]
As described above, since the data transfer circuit according to this example manages the print buffers for each of yellow, magenta, cyan, and black independently, the data transfer to the print head is performed by combining the print data for each color in a predetermined order. In spite of having to send it, the CPU 1 can create the print buffer for each color independently, and the load of creating the print buffer is reduced.
[0049]
Further, by setting the horizontal address change of the print buffer for each color by the horizontal offset register, it is possible to arbitrarily set the continuous address amount in the vertical direction. Therefore, the structure of the print buffer can be determined regardless of the number of dots of the print head, and the optimum print buffer structure can be adopted according to the processing of the CPU 1 and the memory capacity.
[0050]
In the above description, it is assumed that a four-color print head is used. In this example, for example, the above-described timing control circuit controls the use of only the black address register and the horizontal offset register. Since the same processing as in the example can be performed, it is naturally possible to use a monochromatic head. As a result, the printer employing this example can be mounted with print heads having different numbers of colors and nozzles. In this case, it is possible to support various print head data transfer methods by simply changing the data transfer circuit settings (mode settings), so the print buffer configuration can be shared by different types of heads. Thus, the load on the CPU 1 can be reduced and the program size for the print buffer creation process can be reduced.
[0051]
Furthermore, if the print head has information for identifying the number of colors, the number of nozzles, etc., it is possible to automatically perform printing according to the type of the print head by detecting it on the printer side.
[0052]
As described above, in this example, since the data transfer circuit controls the address of the print buffer for each color independently, the data transfer to the print head is required to send the print data for each color in combination. Can create a print buffer for each color separately, reducing the load of creating the print buffer. In addition, it is possible to easily use print heads with different numbers of colors and dots, and the print buffer configuration can be made common to different types of heads, reducing the load on the CPU.
[0053]
(Example 1)
Next, examples of the present invention will be described. The main circuit configuration of the printer provided with the data transfer circuit in this embodiment is the same as that in FIG. 1, and includes a CPU 1, a data transfer circuit 2, a RAM 3, and a print head 4. Further, the dot configuration of the print head in this embodiment is the same as that shown in FIG. 5, and 136 ink ejection nozzles are arranged in a row, and in the order from the top, yellow 24 dots, magenta 24 dots, cyan 24 dots, and black 64 dots. Composed.
[0054]
FIG. 9 is a timing chart showing the print head drive sequence in this embodiment. In FIG. 9, the print head is driven in a time-sharing manner, and 136 nozzles are driven by being divided into 16 times. Adjacent nozzles are sequentially driven at different timings (for example, Y16, Y15,...), And simultaneously driven nozzles are every 16 dots (including a gap of 8 dots between nozzle groups, that is, a distance unit corresponding to 16 dots) ) By time-sharing driving, the peak value of the current required for driving the print head can be reduced to reduce the power load. Furthermore, by driving adjacent nozzles at different timings, it is possible to reduce the vibration of ink in the head due to the ejection of ink droplets, and to improve the ink ejection characteristics of the head and the ink refill time (refill time). it can.
[0055]
However, since the serial printer is driven while the print head is running with respect to the recording paper, the deviation of the driving timing is the deviation of the dot position on the recording paper. In the driving method as shown in FIG. 9, dot rows are formed in a saw-like shape with a time difference due to time division. Therefore, when the print head is driven in a time-sharing manner, it is necessary to take some measures so that a print deviation does not occur due to a time difference in drive timing.
[0056]
A method for preventing printing misalignment due to time-division driving in this embodiment will be described with reference to FIG. In FIG. 10, the diagram on the left side shows the nozzle arrangement from the first (Y1) to the twentieth (Y20) of yellow, which is the upper part of the print head. The print head is 3.58 with respect to the vertical line on the recording paper. It is attached to the carriage in a tilted state. That is, the print head has an inclination of 1 dot in the horizontal direction per 16 dots in the vertical direction. The carriage is scanned in the horizontal direction with respect to the recording paper. In the figure, L indicates a 1-dot pitch, which is 70.6 μm (360 DPI) in this embodiment.
[0057]
In this state, the dot array formed on the recording paper by the drive sequence of FIG. 9 is shown on the right side of FIG. Since the shift in drive timing due to time-division driving is offset by the tilt of the head, the dots from the first nozzle to the 16th nozzle are arranged vertically, and no print error occurs. Since the 17th and subsequent nozzles are arranged vertically apart by one dot to the right, dots in the right adjacent row are formed, and no print misalignment occurs. That is, when viewed from the entire print head, dots in the adjacent row are formed every 16 nozzles as shown in FIG. 11, and the dots on the recording sheet are stepped (one dot interval) by one drive of the print head. Rows are formed over 10 rows.
[0058]
That is, in this embodiment, the angle between the arrangement direction of the recording elements and the relative scanning direction of the recording head and the recording medium is θ = 3.58 degrees, and the pixels are perpendicular to the relative scanning direction of the recording head and the recording medium. When the pitch is a = 70.6 μm and the pixel pitch in the relative scanning direction of the recording head and the recording medium is b = 70.6 μm,
tan θ = (P × b) / (M × a) = 1/16, (P = 1, M = 16)
The 16 groups are divided into 16 equal parts within the drive cycle of the recording head and driven.
[0059]
FIG. 12 is a block diagram of an address generation circuit for reading the print buffer in the data transfer circuit 2. 12, address (K to C) registers 101a to 101d, horizontal offset (KH to CH) registers 102a to 102d, selector 103, save register 104, selector 105, selector 106, mask circuit 107, and inverting / non-inverting circuit 108. The functions of the adder 109 and carry control circuit 110 are the same as in FIG.
[0060]
Reference numeral 111 denotes a staircase pattern (ZP) register and 112 denotes a selector. In this embodiment, these circuits are characteristic to the previous example.
[0061]
The staircase pattern register 111 is connected to the data signals D0 to D15 and stores the staircase pattern of the print head. The staircase pattern is data indicating the shape of a dot row formed by a single drive of the print head. The selector 112 selects staircase pattern data. The output of the selector 112 is input to the mask circuit 107 to control the mask state.
[0062]
The data structure of the print buffer is shown in FIG. The structure of the print buffer itself is exactly the same as in FIG. 7, but the data printed by one drive of the print head is the hatched portion in FIG. 13, that is, the address Y, Y + 1, Y + 2, YH 3 bytes, address 3 bytes of M, M + 1, M + 2 + MH, 3 bytes of addresses C, C + 1, C + 2 + CH and 8 bytes from address K to K + 7 + 3KH. Therefore, when print data is transferred to the print head, the print buffer is read obliquely as shown by the colored portion in FIG.
[0063]
FIG. 14 is a timing chart showing the operation of the address generation circuit of FIG. 12, and shows the case of forward printing. The operation of the address generation circuit shown in FIG. 12 will be specifically described with reference to FIG.
[0064]
In FIG. 14, CLK is a clock signal for synchronously moving the address generation circuit, and each part of the address generation circuit changes in synchronization with the rise of CLK. The values of the address registers 101a to 101d are preset to K, Y, M, and C, and the values of the horizontal offset register 12 are preset to KH, YH, MH, and CH. The value of the staircase pattern register 111 is set to be set once per 16 dots of print data, that is, once every 2 bytes. When the data transfer circuit 2 starts reading the print buffer, the value Y of the address register 101b is first selected by the selector 103 and output to the signals PBA0-18. The values of the signals PBA0-18 are output to the address signal ADDRESS of the RAM 3, and a read pulse is output to the read signal READ-. Therefore, print data is read from the start address Y and transferred to the print head 4. At the time of reading, the start address Y is stored in the save register 104, and the values of the signals LA0-18 are Y.
[0065]
Since selector 105 selects signals PBA0-18, the values of signals SA0-18 are equal to PBA0-18. The selector 106 selects the value YH of the horizontal offset register 102b, but the output value is 0 because the mask circuit 107 is in the mask state. Since the inversion / non-inversion circuit 108 is in the non-inversion state, the output value 0 of the mask circuit 107 is output as it is. Since carry control circuit 110 sets carry, it has the same effect as adding 1 to adder 109.
[0066]
In FIG. 14, the signal with the name of the added value is obtained by adding the output value of the inverting / non-inverting circuit 108 and the output of the carry control circuit 110, and the sum of the signals SA0-18 and the added value is the signal NPA0. 18 is output. Since the added value is +1, the values of NPA0-18 are Y + 1, and this value is fed back to the address register 101b. Therefore, the value of the address register 101b is set to Y + 1 at the next clock, and the print data is read from the address Y + 1 and transferred to the print head 4.
[0067]
At this time, since the output of the selector 112 is set according to the setting of the staircase pattern register 111, the mask circuit 107 is not masked and outputs the value YH of the horizontal offset register 102b. Therefore, the added value becomes + 1 + YH, and the value of the address register 101b is added up to Y + 2 + YH in the next clock. Therefore, for the yellow print buffer, the print data read from the 3 bytes of the addresses Y, Y + 1, Y + 2 + YH is transferred to the print head.
[0068]
When the address Y + 2 + YH is read, the selector 105 selects the signals LA0-18, so that the values of the signals SA0-18 are the value Y stored in the save register 104. Further, the mask circuit 15 is in a non-mask state and outputs YH, and the carry control circuit 18 resets the carry, so that the added value becomes YH. Therefore, the values of NPA0-18 are Y + YH, and this value is set in the address register 101b. Similarly, magenta, cyan, and black print data are sequentially read out. However, for black only, 8-byte print data is transferred to the print head.
[0069]
Each time the transfer of the print data for each color is completed, the value of the address register 101a-d is reset to the address on the right side of each print buffer, so the CPU 1 sets the start address once before scanning the carriage. For example, it is not necessary to reset the address while scanning the carriage. When printing in the reverse direction, it is possible to set the values of the address registers 101a to 101d to the address on the left side using the inversion / non-inversion circuit 108.
[0070]
The selection state, mask state, and inversion state of the selectors 103, 105, 106, 112, the mask circuit 107, and the inversion / non-inversion circuit 108 are controlled by a timing control circuit (not shown) based on the clock signal CLK as in the embodiment. doing.
[0071]
As described above, the data transfer circuit according to the present embodiment has a function of reading the print buffer obliquely in correspondence with the step-like dot arrangement shape formed by the print head. Therefore, the CPU 1 is not aware of the dot arrangement shape. Print data in the print buffer can be created, and the load on the CPU can be reduced.
[0072]
In this embodiment, the case where the head is switched every 16 dots has been described. However, if the switching dot length is a print data transfer unit, that is, a multiple of 8 dots, it is possible to cope with this by simply changing the setting value of the staircase pattern register. It is. Of course, it is also possible to use a monochromatic head.
[0073]
As described above, since the data transfer circuit has a function of reading the print buffer in accordance with the dot arrangement shape of the print head, the CPU can create print data without being aware of the dot arrangement shape of the print head.
[0074]
Further, when used in the ink jet recording method, it is possible to reduce the interference of shock waves in the common liquid chamber.
[0075]
(Example 2)
FIG. 17 schematically shows the second embodiment of the present invention. The recording head 4 is of a bubble jet type, has 32 nozzles, and has a 4-split drive configuration as shown in the circuit diagram of FIG. Here, 41 is a 64-bit shift register, 42 is a latch register, 43 is an AND gate for selecting a block, and 44 is a heating element.
[0076]
The angle θ formed by the nozzle arrangement direction of the recording head 4 and the vertical direction of the scanning direction (arrow A) with respect to the recording paper 5 of the recording head 4 is
tan θ = 1/4
Have the relationship. In this embodiment, M = 4 and P = 1, and the vertical and horizontal pixel pitches are equal. The vertical and horizontal pixel pitch is 360 dpi, so the nozzle pitch is
360 x cos (tan ^-1 (1/4))
That is, it is about 349 dpi.
[0077]
The drive frequency of the recording head 4 is 3 kHz, and a carriage (not shown) that scans the recording head 4 scans the recording paper 5 in the direction of arrow A at a speed of 211.7 mm / sec. The group numbers of the 32 nozzles included in the recording head 4 are BLOCK1, BLOCK2, BLOCK3, BLOCK4, BLOCK1, BLOCK2, BLOCK3, BLOCK4,. The driving order of each group is an expression of (m × P / M + C). In this example, if C = −0.25, the order of values after the decimal point becomes the driving order, and becomes BLOCK1, BLOCK2, BLOCK3, and BLOCK4.
[0078]
The drive circuit shown in FIG. 18 is driven in equal divisions as shown in FIG. Since the driving frequency of the recording head 4 is 3 kHz (333 μs) as described above, the driving period of each group is 83.3 μs. The pixel pitch deviation in the direction of arrow A between adjacent nozzles is ¼ pixel, and the carriage advances by ¼ pixel during the period of 83.3 μs. Therefore, as shown in FIG. 20, the ejected liquid droplets from each nozzle land on the correct pixel position accurately.
[0079]
As data for the nozzles in each group, the data in the corresponding column may be read and given using the data transfer circuit shown in the first embodiment.
[0080]
(Example 3)
Example 3 is shown in FIG. In this example, a 600 dpi recording apparatus is realized without image distortion using a 360 dpi recording head. The angle θ is configured to satisfy the following formula.
[0081]
tan θ = 4/3
M is 3, and three-division driving is performed. The circuit configuration is shown in FIG. Here, the parts corresponding to those in FIG.
[0082]
The driving order of the three groups is (m × P / M + C), that is, (m × 4/3 + C) in ascending order after the decimal point. C is an element that determines the initial value of the cyclically driven group order, and in this example, it is −1/3. The group numbers are BLOCK1, BLOCK2, BLOCK3, BLOCK1, BLOCK2, BLOCK3,... In order from the top of the recording head 4 as in the second embodiment. From the above, the driving order of each group is BLOCK1, BLOCK2, BLOCK3, BLOCK1, BLOCK2, BLOCK3,..., And the driving waveforms are shown in FIG.
[0083]
(Other)
The present invention brings about an excellent effect in a recording apparatus using an ink jet recording head that performs recording by forming thermal liquid using thermal energy among ink jet recording methods.
[0084]
As its typical configuration and principle, for example, those performed using the basic principle disclosed in US Pat. Nos. 4,723,129 and 4,740,796 are preferable. This method can be applied to both the so-called on-demand type and the continuous type. In particular, in the case of the on-demand type, it is arranged corresponding to the sheet or liquid path holding the liquid (ink). By applying at least one drive signal corresponding to the recording information and giving a rapid temperature rise exceeding the nucleate boiling to the electrothermal transducer, the thermal energy is generated in the electrothermal transducer, and the recording head This is effective because film boiling occurs on the heat acting surface, and as a result, bubbles in the liquid (ink) corresponding to this drive signal can be formed. By the growth and contraction of the bubbles, liquid (ink) is ejected through the ejection opening to form at least one droplet. It is more preferable that the drive signal has a pulse shape, since the bubble growth and contraction is performed immediately and appropriately, and thus it is possible to achieve discharge of a liquid (ink) having particularly excellent responsiveness. As this pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further excellent recording can be performed by employing the conditions described in US Pat. No. 4,313,124 of the invention relating to the temperature rise rate of the heat acting surface.
[0085]
As the configuration of the recording head, in addition to the combination configuration (straight liquid channel or right-angle liquid channel) of the discharge port, the liquid channel, and the electrothermal transducer as disclosed in each of the above-mentioned specifications, Configurations using US Pat. No. 4,558,333 and US Pat. No. 4,459,600, which disclose a configuration in which the action portion is disposed in the bent region, are also included in the present invention. In addition, for a plurality of electrothermal transducers, Japanese Patent Application Laid-Open No. Sho 59-123670 that discloses a configuration in which a common slit is used as a discharge portion of the electrothermal transducer or an aperture that absorbs pressure waves of thermal energy is provided. The effect of the present invention is also effective as a configuration based on Japanese Patent Application Laid-Open No. 59-138461 which discloses a configuration corresponding to the discharge unit. That is, whatever the form of the recording head is, according to the present invention, recording can be performed reliably and efficiently.
[0086]
Furthermore, the present invention can be effectively applied to a full-line type recording head having a length corresponding to the maximum width of a recording medium that can be recorded by the recording apparatus. As such a recording head, either a configuration satisfying the length by a combination of a plurality of recording heads or a configuration as a single recording head formed integrally may be used.
[0087]
In addition, even the serial type as shown in the above example can be connected to the main body of the recording head or attached to the main body of the device so that electrical connection with the main body of the device and ink supply from the main body are possible. The present invention is also effective when a replaceable chip type recording head or a cartridge type recording head in which an ink tank is integrally provided in the recording head itself is used.
[0088]
Further, it is preferable to add a recording head ejection recovery means, a preliminary auxiliary means, etc. as the configuration of the recording apparatus of the present invention, since the effects of the present invention can be further stabilized. Specifically, heating is performed using a capping unit, a cleaning unit, a pressurizing or suction unit, an electrothermal transducer, a heating element different from this, or a combination thereof. Examples thereof include a preliminary heating unit for performing the discharge and a preliminary discharge unit for performing discharge different from the recording.
[0089]
Also, regarding the type or number of recording heads to be mounted, two or more numbers may be provided corresponding to a plurality of inks having different recording colors and densities. That is, for example, as a recording mode of the recording apparatus, not only a recording mode of only a mainstream color such as black, but also a recording head may be configured integrally or by a combination of a plurality of different colors, Alternatively, the present invention is extremely effective for an apparatus having at least one of full-color recording modes by color mixing.
[0090]
In addition, in the embodiments of the present invention described above, the ink is described as a liquid. However, ink that is solidified at room temperature or lower and that softens or liquefies at room temperature may be used. In the ink jet system, the temperature of the ink itself is adjusted within a range of 30 ° C. or higher and 70 ° C. or lower to control the temperature so that the viscosity of the ink is within the stable discharge range. A liquid material may be used. In addition, it is solidified and heated in an untreated state in order to actively prevent the temperature rise caused by thermal energy from being used as the energy for changing the state of the ink from the solid state to the liquid state, or to prevent the ink from evaporating. You may use the ink which liquefies by. In any case, by applying thermal energy according to the application of thermal energy according to the recording signal, the ink is liquefied and liquid ink is ejected, or when it reaches the recording medium, it already starts to solidify. The present invention can also be applied to the case of using ink having the property of liquefying for the first time. The ink in such a case is in a state of being held as a liquid or a solid in a porous sheet recess or through-hole as described in JP-A-54-56847 or JP-A-60-71260. Alternatively, the electrothermal converter may be opposed to the electrothermal converter. In the present invention, the most effective one for each of the above-described inks is to execute the above-described film boiling method.
[0091]
In addition, the ink jet recording apparatus according to the present invention may be used as an image output terminal of an information processing device such as a computer, a copying apparatus combined with a reader or the like, and a facsimile apparatus having a transmission / reception function. The thing etc. may be sufficient.
[0092]
The present invention is not limited to the ink jet recording method, and can be applied to other recording methods such as a thermal recording method and a wire dot recording method.
[0093]
【The invention's effect】
According to the present invention, by dividing the division drive timing widely and equally in the drive cycle, the current concentration of the power source and the shock wave interference in the case of the ink jet recording system are further reduced, and there is no image disturbance even if the division drive is performed. A recording device can be supplied.
[0094]
Further, according to the present invention, it is possible to record at an arbitrary pixel pitch higher than the nozzle pitch of the recording head.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a main circuit configuration of a printer.
FIG. 2 is a block diagram of an address generation circuit.
FIG. 3 is a diagram illustrating a data structure of a print buffer.
FIG. 4 is a timing chart showing the operation of the address generation circuit.
FIG. 5 is a diagram illustrating a dot configuration of a print head.
FIG. 6 is a block diagram of an address generation circuit.
FIG. 7 is a diagram illustrating a data structure of a print buffer.
FIG. 8 is a timing chart showing the operation of the address generation circuit.
FIG. 9 is a timing chart showing a print head drive sequence.
10 is a diagram illustrating in detail a dot arrangement of a part of the print head according to the first embodiment.
FIG. 11 is a diagram illustrating a dot arrangement of the entire print head according to the first exemplary embodiment.
FIG. 12 is a block diagram of an address generation circuit according to the first embodiment.
FIG. 13 is a diagram illustrating a data structure of a print buffer according to the first embodiment.
FIG. 14 is a timing chart illustrating an operation of the address generation circuit according to the first exemplary embodiment.
FIG. 15 is a diagram illustrating an example of printing by conventional time-division driving.
FIG. 16 is a diagram illustrating another example of printing by conventional time-division driving.
FIG. 17 is a diagram illustrating a print head according to a second embodiment.
FIG. 18 is a circuit diagram illustrating a configuration of a recording head of Example 2.
FIG. 19 is a timing chart of the second embodiment.
FIG. 20 is a diagram illustrating a print example according to the second embodiment.
FIG. 21 is a diagram illustrating a print head according to a third embodiment.
FIG. 22 is a circuit diagram illustrating a configuration of a recording head of Example 3.
FIG. 23 is a timing chart of the third embodiment.
[Explanation of symbols]
1 CPU
2 Data transfer circuit
3 RAM
4 Print head
11 Address register
12 Horizontal offset register
13 Save register
14 Selector
15 Mask circuit
16 Inverting / non-inverting circuit
17 Adder
18 Carry control circuit

Claims (5)

A print buffer for holding recording data to be transferred to the recording head as a unit of address with a predetermined number of data;
A plurality of recording element groups configured by a plurality of recording elements and corresponding to a plurality of ink colors for recording are arranged in a straight line with a predetermined number of dots equal to the predetermined number of data, and the predetermined dots The recording element group which is arranged so as to obliquely intersect a plurality of recording rows on which recording is to be performed, using a recording head in which each recording element group is composed of recording elements whose number is a natural number of the number A recording apparatus that records an image by moving the column in the arrangement direction of the recording column relative to the recording medium,
A first address designating circuit for sequentially designating read addresses of the recording data in a direction along the recording sequence;
A second addressing circuit for shifting the designation of the address to the address of the adjacent recording row;
The predetermined number of data corresponding to the address unit in which the total number of recording elements of one recording element group and the predetermined number of dots adjacent to each other is every predetermined number of addresses specified by the first addressing circuit. The address is shifted by the second addressing circuit every time the addressing is performed a predetermined number of times that is a natural number multiple of the recording element, so that the plurality of recording columns intersecting the column of the recording elements can be handled. An address switching circuit for transferring data;
A recording apparatus comprising: a recording unit configured to perform recording on an adjacent recording row for each data specified by the predetermined number of times by the first address specifying circuit. The first addressing circuit has an address register for holding a head address of a column corresponding to the recording column in the print buffer, and the second addressing circuit addresses to an address of an adjacent recording column A horizontal offset register that holds an offset value for shifting the designation of the address, and the address switching circuit shifts an address by an offset value held in the horizontal offset register for each predetermined number of address designations The recording apparatus according to claim 1, further comprising a register.   The recording apparatus according to claim 1, wherein the recording element groups corresponding to the recording of the plurality of colors perform recording on different columns on the recording medium.   The recording apparatus according to claim 1, wherein the recording head ejects ink by heat.   The recording head includes a shift register for receiving, from the print buffer, data corresponding to the number of recording elements constituting the plurality of recording element groups not including the dot corresponding to the interval between the plurality of colors. The recording apparatus according to claim 1.

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