JP2007118595A - Recorder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform a transfer process of record data regardless of inclination of nozzle arrays. <P>SOLUTION: This recorder is provided with a generation means of generating a window signal for providing drive timing of a recording head for each nozzle array, a recording buffer having addresses which are successive corresponding to the transporting direction of the recording medium for performing storage and reading of record data, a first storage means for storing data read from the recording buffer, a second storage means for storing data read from the first storage means based on information relating to inclination, and a means of transferring the data stored in the second storage means to each nozzle array of the recording head. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a recording apparatus that performs recording using a recording head, and relates to processing of recording data.

  In recent years, multi-color and multi-nozzle technologies have been accelerated in inkjet recording apparatuses in order to further increase image quality and speed. For this reason, the print data has been devised to transfer a large amount of data to the recording head at high speed.

  FIG. 5 shows a print data transfer control configuration in consideration of transferring a large amount of data to the recording head at high speed, and FIG. 6 shows a print data storage format (Patent Document 1).

  As shown in FIG. 5, the recording data stored in the print buffer is temporarily stored in the SRAM 1 in units of 16 columns as print data determined in various print modes. Thereafter, it is configured to be transferred one column at a time to a recording head (configured with 128 nozzles in this figure).

  The print data transferred to the recording head is controlled by a block drive order signal and a heater drive pulse signal which are separately provided, and is ejected as ink.

  Here, the print buffer is provided on an SDRAM having a burst read function. As shown by (I) in FIG. 6, the recording data is stored in a form that forms continuous addresses in the nozzle row direction (Y direction in the figure). Hereinafter, this type of print buffer configuration is expressed as a raster type print buffer.

  When the read data is DMA-read from the print buffer, if the read start address A is designated, the address is automatically incremented by using the burst read function of the SDRAM. That is, eight words of data in the nozzle row direction are DMA-read from the addresses A, A + 2, A + 4, A + 6, A + 8, A + 12, and A + 14 at high speed. This is shown in FIG. 6 (shown in II).

  Further, when data is read in the next nozzle direction, data for 8 words from the continuous address can be DMA read by setting the read start address to A + 16. By repeating the DMA read while updating the read start address of the print buffer by the print head length (= number of nozzles), it is possible to read 16 columns of data at a time.

  In addition, when the read start address is updated in the scanning direction of the recording head (X direction in the figure), the read start address is updated to A + B and data is read in the same manner. Here, “B” is a predetermined offset value. The read start address and the offset value are determined by setting a set value in a predetermined register, and the register value of the read start address is sequentially updated.

  The read data for 16 columns is stored in the SRAM 1. In the SRAM 1, the print data for each column (column (1) to column (16)) is converted and stored so as to be readable according to the format of the recording head (see (III) in FIG. 6).

  In FIG. 6 (III), when data is read from the addresses a, a + 1, a + 2, and a + 3 of the SRAM 1, print data for one column (column (1)) is read.

  FIG. 8 shows a drive circuit for driving the recording head. The recording head is controlled by a serial recording data signal, a head clock signal, a latch signal for latching data, a block enable signal, and a heater drive pulse signal.

  The block enable signal is an enable signal for each block composed of a plurality of nozzles of the recording head. The heater driving pulse signal is a signal for driving and controlling the discharge heater provided in the recording head.

  In FIG. 8, the recording head is driven by dividing 256 heaters (recording elements) 606 into 16 blocks (one block is composed of 16 heaters), and each block drives 16 heaters. The print data for one column read from the SRAM is rearranged for each block. Here, for example, the block 0 is composed of SEG0, SEG16,..., SEG240. The block 1 is composed of SEG1, SEG17,..., SEG241. Blocks 2 to 15 have the same configuration. Thus, each block is composed of 16 bits.

  The rearranged print data is serially transferred to the recording head by a head clock signal. The print data is received by the 16-bit shift register 801 and then latched by the latch 802 at the rising edge of the latch signal. The block designation is indicated by four block enable signals, and the heater 806 of the designated block developed by the decoder 803 is selected.

  Only the segment of the heater 806 designated by both the block enable signal and the heater recording data signal is driven by the actual heater driving pulse signal (AND gate 805), and recording is performed by ejecting ink.

  The block driving order is determined and controlled so as to minimize the variation in the ink landing position caused by the variation in the nozzle manufacturing process.

  In recent years, there is a case where means for reducing the block enable signal is used by adding block enable data converted into serial data to the serial signal of the print data.

  FIG. 9 is a diagram showing the relationship between the head clock signal and the recording data signal when the recording data is added to the block data and transferred.

In the figure, recording data is transferred to the recording head at the rising edge of the head clock signal and the falling edge of the head clock signal. For example, when the data of block 1 is transferred, the data of SEG0 is transferred as data 0 in the drawing, the data of SEG16 is transferred as data 1,. A block is designated by 4-bit BE0, BE1, BE2, and BE3 following these data. For example, block 1 is selected by sequentially transferring data “1”, “0”, “0”, and “0”.
JP 2003-154640 A

  When the recording head is not accurately mounted on the carriage, that is, when the ink discharge ports are arranged to be inclined with respect to the conveyance direction of the recording medium, the recording position is shifted and a desired recording result cannot be obtained. In particular, the phenomenon becomes remarkable in color printing in which an image is formed by superimposing a plurality of colors.

  There is a case where the recording head is inclined and mounted on the carriage due to a mounting mistake of the user. In addition, there is a case in which a recording head with a previously inclined nozzle array is mounted for use. In this case, information regarding the inclination of the nozzle row is obtained from the adjustment mode and the recording head is controlled based on the information.

  Further, due to the increase in the number of nozzles of the recording head and the length of the nozzle row, correction may be required beyond the range of one column.

  In this case, the nozzle row of the recording head is divided into blocks of 32 nozzles, for example, and a window signal is prepared for each block. Then, the control for correcting the printing timing in units of one column trigger is performed by regarding one recording head as a plurality of recording heads and shifting the timing of the window signal for each block.

  FIG. 10 is a diagram illustrating a control method for performing correction in units of column triggers. In addition, the inclination method is not limited to the form shown in FIG. In the figure, the recording head is composed of 256 nozzles, and is attached to the carriage in a state where printing is performed at a position shifted by the time of one column trigger in units of 64 nozzles.

  In order to correct the tilt by such a recording head and realize good image quality, a window signal (1) to window (1) is used as a window signal for each of the blocks (1) to (8) in units of 32 nozzles. 8) A signal is provided.

  When the window (1) to window (8) signals are all opened at the same timing (when enabled), the recording head is tilted, so for example, the data in block (3) is one column trigger than the data in block (1). As soon as it is ejected with ink.

  Therefore, the window (3) signal is opened after being delayed by one column trigger (one column) from the window (1) signal. By this control, it is possible to form an image as if ink is being ejected by a recording head in which the nozzle row is not inclined.

  That is, one recording head is regarded as an aggregate of a plurality of heads, and the inclination of the recording head is corrected by controlling each independently.

  FIG. 11 is a diagram for explaining the data reading position in the SRAM 1 when the print head tilt correction control shown in FIG. 10 is performed with the configuration shown in FIG.

  In FIG. 11, a to p on the horizontal axis and 0 to 7 on the vertical axis are indexes for indicating the address of the SRAM. a0, a1,..., a7 are arranged at consecutive addresses, and similarly b0, b1,..., b7, c0, c1,. .., p7 is arranged at a continuous address. This address corresponds to the conveyance direction of the recording medium. In other words, it corresponds to the direction perpendicular to the scanning direction of the recording head.

  The value in the square is the data stored at the address, that is, data a is stored at address a, data a + 1 is stored at address a + 1, and data p + 7 is stored at address p + 7. ing.

  When the print head (or nozzle row) is tilted as shown in FIG. 10, the successive addresses (for example, a, a + 1, a + 2, a + 3, a + 4, a + 5, a + 6, a + 7) are accessed from the SRAM 1 shown in FIG. When the recording data for one column is read out, ink is landed on the recording medium in accordance with the inclination of the recording head, and the inclination of the dots occurs.

  Therefore, in order to eliminate the occurrence of such dot inclination, it is only necessary to read data for one column by accessing addresses d, d + 1, c + 2, c + 3, b + 4, b + 5, a + 6, and a + 7.

  However, in the configuration shown in FIG. 5, four triggers (timing) are required in order to read data for one column stored in the SRAM 1. This is because addresses d and d + 1, addresses c + 2 and c + 3, addresses b + 4 and b + 5, and addresses a + 6 and a + 7 have different column positions.

As described above, assuming that the time between triggers is T, the processing time for writing data of 16 columns is W, and the number of recording heads is N, for one bank,
16T> NW (I)
The relationship must be established.

However, in the case of originally reading data for one column across a plurality of column triggers in order to correct the inclination of the recording head, if the inclination is 3 columns as shown in FIG. 10 (I) ceremony,
(16-3) T> NW (II)
This relationship is necessary. This is because when the number N of print heads increases or the number of nozzles per row increases, that is, when W increases, the process of reading data for transferring to the print heads is not in time.

  In other words, considering the amount of data (number of columns) that can be transferred from the SRAM 1 to the recording head for one bank in the configuration shown in FIG. 5, when the slope is 0, data for 16 columns can be transferred. . However, when the slope is 3, only 13 columns of data can be read from one bank.

  Therefore, in the configuration of FIG. 5, the larger the inclination, the smaller the amount of data that can be read from one bank. The transfer processing step from the SRAM 1 to the print head becomes a bottleneck in the data transfer processing system from the print buffer to the print head.

  Further, when the timing for storing in the SRAM 1 is made independent according to the inclination of the recording head, the address management such as the read address of the print buffer is also performed independently, so that the control becomes complicated. Alternatively, when reading from the SRAM 1, it becomes similarly complicated when it is made independent according to the inclination of the recording head.

  In addition, since the above-described control is performed, the bus access ratio increases due to generation of extra DMA processing.

  The present invention has been made in view of the above problems, and an object thereof is to provide a recording apparatus and a control method for the apparatus that can perform efficient memory access and data transfer processing of data.

  In order to solve the above-described problems and achieve the object, the recording apparatus of the present invention includes a plurality of recording element arrays each including a plurality of recording elements in a direction inclined with respect to the conveyance direction of the recording medium. A recording apparatus configured to perform recording on the recording medium using a recording head including a plurality of recording element arrays in a main scanning direction, the input unit configured to input recording data from the outside; An acquisition unit that independently acquires correction information corresponding to an inclination for each block, and a generation unit that generates a permission signal for permitting driving of a plurality of printing elements for each block based on the correction information acquired by the acquisition unit. A first storage means for holding a plurality of buffers capable of holding m columns of recording data input by the input means, and a buffer for holding data for m columns read from the first storage means A plurality of second storage means, a first storage means for reading out data in units of m columns from the first storage means and storing it in one of the buffers of the second storage means by one DMA transfer; Read processing for one column from the first storage means is performed for each block based on the pointer and the correction information corresponding to each block, and for one column read by the first read means. The second storage means for storing data at the same column position with respect to the third storage means, the read processing of the reading means and the storage processing of the second storage means for m columns, the column for reading by the first reading means A control means for updating the position and the column position stored in the second storage means, respectively, and repeatedly executing them, and one column from the second storage means. Comprising a transfer means for transferring the recording head reads data, and driving means for driving the recording element in a block unit based on the permission signal generated by the generation unit.

  As described above, according to the present invention, the time required for the processing can be suppressed even when the access to the print data memory is controlled corresponding to the nozzles of the print head. Furthermore, the complexity of the circuit for performing data transfer can be suppressed.

  Embodiments according to the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram showing the configuration of a recording apparatus that can be applied as an embodiment of the present invention. The recording apparatus of the present embodiment is an ink jet recording apparatus including a so-called ink jet recording type recording head 1.

  This recording head 1 uses an electrothermal transducer such as a heating element having a heating resistor as an energy generating means, among other ink jet recording methods, to heat ink and discharge ink droplets by thermal energy.

  The recording head 1 has four color recording heads, a cyan recording head 1C, a magenta recording head 1M, a yellow recording head 1Y, and a black recording head 1K. The recording heads 1 </ b> C, 1 </ b> M, 1 </ b> Y, and 1 </ b> K for each color are mounted on the carriage 2 in a state of being arranged along the length direction of the guide shaft 3. That is, the recording heads are mounted on the carriage 2 in a state in which the recording heads are arranged along the moving direction (scanning direction) of the carriage 2. The recording head 1 is mounted on the carriage, and the nozzle row for each color forms a predetermined angle with the conveyance direction of the recording medium.

  In FIG. 3, the recording head 1 is mounted on the carriage 2 so as to eject ink downward in the figure. The bearing 2a of the carriage 2 moves along the guide shaft 3 to eject ink droplets, thereby recording paper. An image for one scan is formed on the recording medium 4.

  The reciprocating motion along the guide shaft 3 of the carriage 2 is performed via the timing belt 7 by the rotation of the pulley 6 to which the driving force of the carriage motor 5 is transmitted.

  When recording for one scan by the recording head 1 is completed, the recording head 1 stops recording, and the conveyance motor 9 is driven so that the recording medium 4 positioned on the platen 8 is orthogonal to the moving direction of the carriage 2. Is conveyed by a predetermined amount. Next, image formation for the next one scan is performed while moving the carriage 2 along the guide shaft 3 again. By repeating these operations, the entire recording medium 4 is recorded.

  On the right side of the recording apparatus, a recovery device 10 that performs a recovery operation for keeping the ink ejection state of the recording head 1 in a favorable state is disposed. The recovery device 10 includes a cap 11 that caps the recording head 1, a wiper 12 that wipes the ink discharge surface of the recording head 1, and a suction pump (not shown) that sucks ink from the ink discharge nozzles of the recording head 1. It has been.

  In addition, the recording apparatus of the present embodiment includes an encoder scale 13 and an encoder 14, and is configured to detect the moving speed of the carriage 2 and to perform feedback control when the carriage motor 5 is driven. Also, the ink discharge timing (hereinafter referred to as heat timing) of the recording head 1 is taken by reading the position information of the encoder scale 13 by the encoder 14. A trigger signal (TRG) is generated based on the signal from the encoder. This signal TRG is used for data transfer processing.

  FIG. 4 is a diagram illustrating an internal control configuration of the recording apparatus. In this figure, a thin line represents a control signal, and a thick line represents a data flow. Reference numeral 100 denotes an I / F block (interface block) that exchanges recording data with a host connected to the recording apparatus, and is composed of a FIFO memory.

  When data including recording data is received, the data is temporarily held. The ASIC 103 analyzes the control code from the temporarily held data, and stores the recording data from the data in a recording buffer provided in the RAM 105 using the DMA unit. . This control is performed for data corresponding to each color.

  A CPU 101 performs various controls such as a recording operation. Reference numeral 102 denotes a ROM for storing a program such as a recording operation procedure. Reference numeral 103 denotes an ASIC that controls the entire system under the control of the CPU 101. The ASIC controls the recording data analysis processing described above, processing for DMA reading recording data from a recording buffer, which will be described later, conversion processing for conversion to a format suitable for the nozzle arrangement of the recording head, and processing for transferring to the recording head 1. I do.

  Reference numeral 104 denotes a DMAC (DMA controller) that controls a plurality of DMA channels used in the recording apparatus. For example, when DMA requests overlap, arbitration control is performed with a predetermined priority.

  Reference numeral 105 denotes a RAM for temporarily storing data, and a print buffer is also provided therein. In this embodiment, SDRAM is used as a RAM (storage means), and 8-word data can be read from a continuous address by one DMA read operation (DMA read processing). This 8-word read process is performed by the burst read function.

  Reference numeral 106 denotes an SRAM 1 which stores data after converting the recording data DMA-read from the print buffer arranged in the SDRAM 105 into a format suitable for the recording head 1. Specifically, the data read from the recording buffer is HV converted, and the converted data is stored in the SRAM 1.

  Reference numeral 108 denotes an SRAM 2 for storing data in which print data stored in the SRAM 1 is rearranged in units of columns in accordance with the inclination of the recording head in order to correct the inclination of the recording head.

  Reference numeral 107 denotes a recording head driver that controls the recording head 1 that performs ink jet recording. The drive timing is created from the information from the encoder 14 and is controlled by the ASIC 103.

  FIG. 1 is a diagram illustrating a recording data transfer control configuration according to the embodiment. As shown in FIG. 1, in addition to the SRAM 1 in the system configuration for transferring recording data (printing data) from the recording buffer (printing buffer) to the recording head, an area SRAM 2 is further provided between the SRAM 1 and the recording head 1. The conventional data processing system has only the SRAM 1 shown in FIG.

  Further, the block drive order signal supplied from the ASIC 103 to the recording head 1 is also output to the newly provided SRAM 2. Further, the ASIC 103 outputs correction values (print head tilt correction signal, nozzle row tilt correction signal) for correcting the print head tilt to the SRAM 1. In this case, the inclination state of the array of printing elements is used as data for each block.

  Here, the correction value is a signal for instructing the column position for reading the recording data from the SRAM 1 as shown in FIG. This signal is output independently for each block.

  As shown in FIG. 1, a recording data read signal is output from the ASIC 103 to the recording buffer, and a recording data storage signal is output from the ASIC 103 to the SRAM 1. Further, a recording data read signal is output from the ASIC 103 to the SRAM 1, and a recording data storage signal is output from the ASIC 103 to the SRAM 2. These data transfer processes will be described for one nozzle row (printing element row). Accordingly, when the recording head includes four nozzle rows, this processing system is performed independently.

<Processing flow for SRAM 1 and SRAM 2>
FIG. 2 is a flowchart for explaining a control sequence for accessing the SRAM 1 and the SRAM 2 in the present embodiment.

  When a trigger is input in step S201, first, data for one column of the print head is read from the SRAM 2 in step S202, and transferred to the print head. In step S203, it is confirmed whether or not the storage timing of the SRAM 1 is met.

  As described above, the storage timing from the recording buffer (printing buffer) to the SRAM 1 is executed every 16 triggers, so it is confirmed whether or not the current trigger timing matches the timing.

  If it is determined in step S203 that it is the storage timing in the SRAM 1, storage processing in the SRAM 1 is performed in step S204.

  After the storage process is completed (in the case of N in step S204), the recording data stored in the SRAM 1 in step S205 is read for one column and stored in the SRAM 2. This step S205 is also executed when it is determined as N in step S203.

  Supplementally, in the control shown in FIG. 2, reading from the SRAM 2 is a first priority. Then, the storage timing in the SRAM 1 is checked, and if it is the storage timing, storage from the print buffer to the SRAM 1 is performed by DMA transfer processing. The storage timing in the SRAM 1 is determined, for example, by whether or not 16 columns of data have been read from the SRAM 1. This determination is made by the ASIC 103, for example. The storage process in the SRAM 1 is given second priority. The transfer process from the SRAM 1 to the SRAM 2 has the third priority.

  This SRAM 1 has two areas (bank 0 and bank 1) for storing data for 16 columns. The SRAM 2 has two areas (bank 0 and bank 1) for storing recording data for 16 columns. As shown in FIG. 7, control is performed so that data is stored in the other bank while sequentially transferring from one bank to the recording head of two sides (two areas) of the SRAM 2.

  The SRAM 1 is also controlled so that data is stored in the other bank while it is being transferred from one bank to the SRAM 2.

  Here, in the description, it is assumed that storage means (SRAM1, SRAM2) are provided for each recording head (one nozzle row). A storage means is provided independently for each color.

<Access timing to SRAM>
FIG. 7 is an explanatory diagram of data storage timing and readout timing for SRAM 1 and data storage timing and readout timing for SRAM 2 for data corresponding to one nozzle row.

  SRAM1-W represents a storing process for the SRAM1. SRAM1-R represents a read process from SRAM1. SRAM2-W represents a storage process for the SRAM2. SRAM2-R represents a read process from the SRAM2.

  These memory accesses are performed in synchronization with the signal TRG. The storage process for the SRAM 1 is performed by the DMA means, and data for 16 columns is transferred in a period of 2 triggers. As shown in the figure, the data is alternately stored in the bank 0 (B0) and the bank 1 (B1) with a period of 16 columns.

  The reading process from the SRAM 1 will be described. BLOCK 0 indicates a data reading period corresponding to the block 0. BLOCK2 indicates a data read period corresponding to block 2. BLOCK 6 indicates a data read period corresponding to the block 6. As shown in the figure, reading from the bank 0 is performed at the timing when the storage of the SRAM 1 in the bank 1 is completed.

  Here, the length of the reading period is different for each block because the reading start position is different for each block. This difference depends on the correction value described above.

  The reading of the SRAM 1 will be described by taking the block 0 as an example. Reading of bank 0 is started at TRG19. This reading is performed during a period B0 indicated by an arrow. One column is read per trigger. Since the length of this period is 13 triggers, 13 columns are read. Reading is performed for bank 1 at the next TRG signal. Thereafter, 16 columns are read. Bank 0 and bank 1 read alternately. Similarly, other blocks are read.

  Here, to supplement, for example, in TRG 32, the data of block 0 is read from bank 1, while the data of block 2 is read from bank 0.

  Next, storage processing for the SRAM 2 will be described. The storage start timing for the SRAM 2 is one trigger after the read start timing from the SRAM 1. For example, the storage start timing for the SRAM 2 is TRG20, and the read start timing for the SRAM 1 is TRG19. Then, storage processing for 16 columns is performed on the SRAM 2 in the time of 16 triggers as shown in the figure. The storage process for the SRAM 2 is also performed for one column per trigger.

  Next, the reading process from the SRAM 2 will be described. Reading from the SRAM 2 starts after being stored in one bank of the SRAM 2. The start timing is the same as the storage start timing for the SRAM 2.

  For example, the start timing of storage in the bank 1 of the SRAM 2 is TRG 36, and the read start timing from the SRAM 2 is also TRG 36.

  The recording head drive start timing is one trigger after the read start timing from the SRAM 2.

<Storage state of SRAM 2>
FIG. 12 is a diagram illustrating the storage state of the SRAM 2 in the embodiment. Addresses a, b, c, d,... Are assigned in the scanning direction of the recording head. Further, addresses a, a + 1, a + 2,... Are continuously assigned in the conveyance direction of the recording medium. The SRAM 2 stores 32-bit data per address. The SRAM 1 also stores 32-bit data per address.

  FIG. 12 shows the correspondence between addresses and recording elements of the recording head. For example, data stored at addresses a, b,..., P corresponds to SEG0 to SEG31, and data stored at addresses a + 1, b + 1,..., P + 1 corresponds to SEG32 to SEG63. is doing. That is, 1-bit data corresponds to 1 SEG.

  11 and 12, for simplicity of explanation, the addresses are all represented by the same symbols (a, a + 1,..., P + 6, p + 7), but the actual addresses are unique. It is allocated and another area is provided.

  As shown in FIG. 12, the print data stored in the SRAM 2 is stored by rearranging the data so as to obtain continuous addresses by correcting the inclination of the recording head.

  That is, data d, d + 1, c + 2, c + 3, b + 4, b + 5, a + 6, and a + 7 are stored in order at addresses a to a + 7.

<Storage processing of data read from recording buffer to SRAM 1>
FIG. 13 is an explanatory diagram for explaining the correspondence between the scanning direction A of the recording head and the nozzle row direction B of the recording buffer.

  The recording buffer has an area for holding a data amount for at least one band. As shown in FIG. 13, the area for storing data for one band is divided into N data blocks. The data blocks that are read and stored for each data block by the DMA transfer means are stored in the SRAM 1 in order. When storing in this SRAM 1, HV conversion is performed.

  The size of this one data block is data for 16 columns. Then, when printing by one scan is started, the data block 1 is stored in the bank 0 of the SRAM 1. Then, the next data block 2 is read from the recording buffer and stored in the bank 1 of the SRAM 1. Then, after the reading of the bank 0 is completed, the next data block 3 is stored in the bank 0 of the SRAM 1. As described above, the ASIC 103 alternately stores data in the two banks included in the SRAM 1.

<Reading process from SRAM 1 using pointer>
The ASIC 103 includes a read control unit of the SRAM 1. The read control unit includes independent pointers corresponding to the blocks. That is, since the number of blocks is 8, 8 pointers are provided.

  This pointer can specify a column position across banks.

  For example, the pointer corresponding to block 0 is pointer 0. Similarly, the pointer corresponding to block 1 is pointer 1, and the pointer corresponding to block 2 is pointer 2. In this way, reading is performed using eight pointers.

  When the correction value of block 0 and block 1 (value related to the inclination) is 3, the correction value of block 2 and block 3 is 2, the correction value of block 4 and block 5 is 1, the correction value of block 6 and block 7 is 0 Will be explained. As shown in FIG. 11, the pointers 0 and 1 point to the column position d, and the pointers 2 and 3 point to the column position c. Here, it is assumed that all pointers specify bank 0.

  Then, data is read from each block based on the pointer. For example, the data of block 0 is read from address d, and the data of block 7 is read from address a + 7.

  Then, after reading, the pointer is advanced by one column by one column position. That is, the pointer 0 points to the column position e, and the pointer 7 points to the column position b. In this way, each time the reading control unit performs reading, each pointer advances the position pointed to by one column position. As can be seen from this figure, reading is performed from one bank.

  For example, the pointer 0 designates the column a of the bank 1 instead of designating the column position a of the bank 0 after reading by designating the column p. At this time, the pointer 2 and the pointer 3 designate the column position p of the bank 0.

  Thus, the pointer is controlled by the read control unit so as to designate the first column position of bank 1 after the last column position of bank 0 (here, column position p). Therefore, the pointer designates the first column position of bank 0 next to the last column position of bank 1 (here, column position p).

  As described above, the pointer sequentially specifies the column positions across the two banks.

  As described above, the reading process from the SRAM 1 includes a mode for reading from one bank and a mode for reading from both banks.

<Storage Processing for SRAM 2>
A process for bringing the SRAM 2 into the storage state as shown in FIG. 12 will be described.

  As indicated by the hatched lines in FIG. 11, reading is performed based on independent correction values for each block as described above. That is, data is read from the addresses d, d + 1, c + 2, c + 3, b + 4, b + 5, a + 6, and a + 7 of the bank 0 of the SRAM 1 and data for one column is read.

  Then, the read data for one column is stored at addresses a, a + 1,..., A + 7 of the bank 0 of the SRAM 2.

  This storage corresponds to the read block. That is, data read from the block 0 of the SRAM 1 is also stored in the block 0 in the SRAM 2. Alternatively, data read from the block 3 of the SRAM 1 is also stored in the block 3 in the SRAM 2.

  Here, for example, the data in block 0 is stored, the data in block 1 is stored next, and the data in block 7 is stored last. Control of storage in the SRAM 2 is performed in the order as described above.

  Returning to the description of the reading process, the reading of the next one column of data is performed with respect to the addresses e, e + 1, d + 2, d + 3, c + 4, c + 5, b + 6, b + 7 of the SRAM 1 and the address b of the bank 0 of the SRAM 2. , B + 1,..., B + 7. Thereafter, reading is performed in the same manner.

  Then, reading is performed from the addresses p, p + 1, o + 2, o + 3, n + 4, n + 5, m + 6, m + 7 of the bank 0 of the SRAM 1 and stored in the addresses m, m + 1,. Up to this point, the processing is to read from one bank and store to one bank.

  FIG. 14A is a diagram for explaining the bank 0 of the SRAM 1, and the area A is an area read in the above description. FIG. 15A illustrates the bank 0 of the SRAM 2. The area A2 is an area stored in the above description. A state is shown in which data for 13 columns from column position a to column position m is stored.

  In the next processing, reading from the two banks of the SRAM 1 is performed, and processing for storing in one bank of the SRAM 2 is performed. That is, a process of reading data for one column across the two banks of the SRAM 1 is performed.

  FIG. 14B illustrates the bank 1 of the SRAM 1. Then, the data is read from the area B1 shown in FIG. 14A and the area B2 shown in FIG. 14B, and stored in the area A3 of the bank 0 of the SRAM 2 shown in FIG. 15B.

  Specifically, in the SRAM 1, reading is performed from the addresses a and a + 1 of the bank 1 (included in the region B1) and the addresses p + 2, p + 3, o + 4, o + 5, n + 6, and n + 7 (included in the region B2) of the bank 0. . Then, the data are sequentially stored in the addresses n, n + 1,..., N + 7 of the bank 0 of the SRAM 2.

  The storage order of data in bank 0 of SRAM 2 is first stored in the order of block 0, block 1 and block 2, and finally the corresponding data of block 7 is stored.

  Similarly, for the remaining two columns of data, data for one column is read from the two banks of the SRAM 1 and written to the bank 0 of the SRAM 2.

  That is, the addresses b, b + 1, a + 2, and a + 3 of the bank 1 of the SRAM 1 and the addresses p + 4, p + 5, o + 6, and o + 7 of the bank 0 of the SRAM 1 are read, and the addresses o, o + 1,. Store.

  Further, the addresses c, c + 1, b + 2, b + 3, a + 4, a + 5 of the SRAM 1 and the addresses p + 6, p + 7 of the bank 0 of the SRAM 1 are read, and the addresses p, p + 1,. Store.

  By performing the above processing, the area A3 (for 3 columns) in FIG. 15B can be stored, and the storage processing for 16 columns of data in bank 0 of the SRAM 2 is completed. When the storage process is completed, the state shown in FIG.

  Next, data for 16 columns in the SRAM 2 is stored in the bank 1. In this case, the same processing as that for bank 0 is performed. That is, for region C in FIG. 14B, data for 13 columns is stored as shown in region C2 in FIG. Then, reading is performed from the area D1 in the bank 1 of the SRAM 1 in FIG. 14B and the area D2 in the bank 0 in the SRAM 1 in FIG. 14C, and is stored in the area C3 in the bank 1 in the SRAM 2 shown in FIG. To do.

  After the storage of data for 16 columns is completed in bank 1 of SRAM 2, data for the next 16 columns is stored again in bank 0. That is, the data for 13 columns read from the area E in FIG. 14C is stored in the area E2 of the bank 0 of the SRAM 2, as shown in FIG.

  As described above, the data storage process for the SRAM 2 is executed alternately for the bank 0 and the bank 1.

<Reading from SRAM 2>
Now, the data stored in the bank 0 of the SRAM 2 is transferred to the recording head one column at a time. First, addresses a to a + 7 are read and transferred. In the next transfer, addresses b to b + 7 are read and transferred. Thereafter, the data is read one column at a time and transferred to the recording head. If the addresses p to p + 7 are read and transferred, the reading process of the bank 0 of the SRAM 2 is completed.

  After the reading for the bank 0 of the SRAM 2 is completed, the data read from the SRAM 1 is stored in the bank 0 of the SRAM 2.

  Further, after the reading of the bank 2 of the SRAM 2 is completed, the reading of the bank 1 of the SRAM 2 is performed.

  As described above, according to the present invention, the time required for data processing can be suppressed by independently reading and writing data corresponding to a block even when the print head is inclined or the nozzle array is inclined. can do.

<Another embodiment>
<Modification of column position pointer>
In the above-described embodiment, the pointer is controlled across two banks, but another form may be used.

  For example, for the pointer of each block, a pointer for bank 0 of SRAM 1 and a read pointer for bank 1 may be provided independently. That is, eight pointers per bank may be used, and two pointers may be combined to provide 16 pointers.

  Read out. The case of the storing process in the bank 0 of the SRAM 2 will be described as an example.

  Here, for example, the pointer 00 for the block 0, the pointer 01 for the block 1, and the pointer 07 for the block 7 are shown. The same applies to the pointer of bank 1, for example, the pointer 10 for block 0 of bank 1 and the pointer 11 for block 1.

  Here, block 0 will be described. Since the control is the same for the other blocks, the description thereof is omitted. The case where the correction value of block 0 is 3 will be described.

  As shown in FIG. 11, the pointer 00 points to the column position d. Then, based on the pointer, data is read from address d as data of block 0. Here, the pointer 0 of the bank 1 is in an invalid state.

  Then, after the reading for one column is completed, the pointer 00 moves to the column position e and performs reading. In this way, the control for advancing each pointer by one column position each time reading is performed is the same as in the above-described embodiment.

  The difference is that after the pointer 00 reads at the column position p, the next block 0 is read based on the pointer 10 of the bank 1. Here, the pointer 00 becomes invalid and the pointer 10 becomes valid. At this time, the read control unit performs control so that the pointer 10 designates the column position a. The pointer 10 recommends the column position every time reading is performed.

  Then, after the pointer 10 reads out to the column position p, the pointer 10 becomes invalid. Next, the pointer 00 becomes valid, and reading is performed from the column position a.

  Note that the size of one bank of the SRAM1 and SRAM2 described above is not limited to 16 columns, but may be other values. For example, the number of columns may be 32 or 64.

The figure showing the transfer control composition of the print data in an embodiment. 6 is a flowchart showing access timing of the SRAM 2 in the present embodiment. 1 is a diagram illustrating a configuration of a recording apparatus that can be applied as an embodiment. FIG. 1 is a diagram illustrating an internal configuration of a recording apparatus that can be applied as an embodiment. The figure showing the transfer control structure of the print data as a conventional embodiment. The figure showing the storage format of the print data as a conventional embodiment. The figure explaining the access timing to the memory based on a trigger signal. This is a drive circuit for driving the recording head. The figure showing the relationship between a head clock signal and a recording data signal when adding block data to recording data and transferring. The figure showing the correction | amendment control method with respect to the recording head which inclines in the column trigger unit. The figure explaining the data reading position from SRAM1 at the time of correction control of the recording head shown in FIG. The figure showing the storage format of SRAM2 in an embodiment. Illustration of data in recording buffer The figure explaining reading of SRAM1 in an embodiment The figure explaining the storage with respect to SRAM2 in embodiment

Explanation of symbols

100 I / F block 101 CPU
102 ROM
103 ASIC
104 DMAC
105 RAM
106 SRAM1
107 Recording head driver 108 SRAM 2
801 Shift register 802 Latch 803 Decoder 804, 805 AND gate 806 Heater (recording element)

Claims (6)

Using a recording head that includes a plurality of recording element arrays that are configured by a plurality of recording elements in a direction that is inclined with respect to the conveyance direction of the recording medium, and that includes a plurality of the recording element arrays in the main scanning direction. A recording apparatus for recording on the recording medium,
An input means for inputting recording data from outside;
Obtaining means for independently obtaining correction information corresponding to the inclination for each block;
Based on the correction information acquired by the acquisition unit, a generation unit that generates a permission signal for permitting driving of a plurality of recording elements for each block;
A first storage means for holding a plurality of buffers capable of holding the recording data input by the input means for m columns;
Second storage means comprising a plurality of buffers for holding data for m columns read from the first storage means;
First storage means for reading data in units of m columns from the first storage means by one DMA transfer and storing the data in one of the buffers of the second storage means;
Reading means for performing reading processing for one column from the first storage means on a block-by-block basis on the basis of the pointers corresponding to the blocks and the correction information;
Second storage means for storing data for one column read by the first reading means at the same column position with respect to the third storage means;
The reading process of the reading unit and the storing process of the second storage unit are repeatedly executed by updating the column position read by the first reading unit and the column position stored by the second storage unit for m columns. Control means;
Transfer means for reading out data for one column from the second storage means and transferring the data to the recording head;
A recording apparatus comprising: a driving unit that drives a recording element in units of blocks based on the permission signal generated by the generating unit.   2. The control unit according to claim 1, wherein after the pointer is moved to the last column position of one of the plurality of banks, the pointer is moved to the first column position of the other bank of the plurality of banks. The recording device described in 1.   3. The read unit according to claim 2, further comprising: a mode for reading data for one column from one of a plurality of banks, and a mode for reading data for one column from a plurality of banks. The recording device described.   The recording apparatus according to claim 1, wherein the first storage unit performs the DMA transfer based on a predetermined timing signal.   The recording apparatus according to claim 4, further comprising a determination unit that determines whether or not it is time to execute the DMA transfer.   The data transfer process for one column by the transfer unit, the read process by the read unit, and the storage process by the second storage unit are executed based on a predetermined timing signal. Recording device.

Images