JP2000015874A - Image-forming apparatus and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form highly detailed images by using dots of different diameters without decreasing a throughput. SOLUTION: This image-forming apparatus forms images by scanning of a recording head consisting of a plurality of recording elements. In this case, a bit data generation circuit 1008 reads out image data from a RAM 1004 in accordance with an address generated from an address generation circuit 1007, and generates a plurality of kinds of bit image data of different dot diameters. A write control circuit 1010 and a read control circuit 1011 control an input order and an output order to a FIFO part 1009 so that the bit image data are output in an order different from an order whereby the data are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus and a control method thereof, and more particularly, to an image forming apparatus for forming an image by a recording head including a plurality of recording elements and a control method thereof.

[0002]

2. Description of the Related Art Conventionally, an image forming apparatus such as a printer which has a plurality of recording elements (ink discharge nozzles, heating elements, etc.) as a recording head and forms an image on a recording medium by a dot impact method, a thermal method, or an ink jet method. It has been known. In such a printer, printing is performed while scanning the recording head in a direction orthogonal to the transport direction of the recording medium (recording paper or the like), and when one line has been printed, the recording paper is removed by the width of the recording head. A serial scan method is generally used, in which an image is formed by repeating an operation of carrying. Here, printing means forming image data, which is not limited to character data, on a recording medium.

In a conventional printer, data and commands sent from a connected host computer are analyzed, and bit image data corresponding to a dot configuration of an image to be recorded on a one-to-one basis is stored in a print buffer in a memory. To be stored. Subsequently, while reading the print data from the print buffer and sequentially transferring the data corresponding to the width to the print head, the print element is driven each time the print head moves a distance corresponding to one pixel to form an image. .

In recent years, in order to realize high definition of images,
The dot pitch of a printer tends to be fine, and the data amount stored in a print buffer is increasing accordingly. On the other hand, in order to improve the printing speed, it has become necessary to read a large amount of data stored in a print buffer at a high speed and transfer it to a recording head. Therefore, in a conventional printer, a dedicated data transfer circuit for reading data from a print buffer is provided, and high-speed data transfer is supported by hardware processing such as DMA.

[0005] Further, in response to the recent demand for higher definition of recorded images, there has been proposed a printer which realizes higher definition image formation by performing printing at a fine pitch using dots having different diameters. .

[0006]

However, since the data transfer circuit in the above-mentioned conventional printer has only a relatively simple transfer function, the data structure in the print buffer must match the dot arrangement of the print head. was there. Therefore, when the dot arrangement of the recording head is complicated, for example, when the dot arrangement of the recording head is oblique to the scanning direction, or when a color-specific recording element such as a color printer is provided, etc. However, the data structure stored in the print buffer has also become complicated, and the time required to create print data has increased.

Further, in a printer that forms a highly detailed image using dots having different diameters, data having different dot diameters are treated as different image data.
For example, if there are two types of dot diameters, two types of image data are required. Therefore, since it is necessary to distinguish the image data into a plurality of types, not only the processing becomes complicated, but also the image data amount itself increases, and the processing time further increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and provides an image forming apparatus and a control method for realizing high-definition image formation using a plurality of types of dots without lowering the throughput. The purpose is to do.

[0009]

As one means for achieving the above object, the image forming apparatus of the present invention has the following arrangement.

That is, an image forming apparatus for forming an image on a recording medium by scanning a recording head comprising a plurality of recording elements, comprising: image data holding means for holding input image data; Address control means for controlling an address for reading data from the holding means; and a bit for generating a plurality of types of bit image data based on the data read from the image data holding means in accordance with the address controlled by the address control means. An image generating unit, a bit image holding unit for temporarily holding the plurality of types of bit image data, and the bit image holding unit so that the plurality of types of bit image data are output in a different order from the generation order. Bit image control means for controlling the input order and output order of Based on the output a plurality of types of bit image data from Ttoimeji holding means, and having and an image forming means for forming an image on a recording medium by driving the recording head.

For example, the bit image generating means includes:
It is characterized by generating bit image data having different dot diameters.

For example, the bit image holding means includes:
It is characterized by being constituted by a plurality of FIFO circuits.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an external perspective view showing an outline of the configuration of an ink jet printer IJRA which is a typical embodiment of the present invention.
In FIG. 1, a carriage HC that engages with a spiral groove 5004 of a lead screw 5005 that rotates via driving force transmission gears 5009 to 5011 in conjunction with forward and reverse rotation of a drive motor 5013 has pins (not shown). Then, it is supported by the guide rail 5003 and reciprocates in the directions of arrows a and b. On the carriage HC, an integrated ink jet cartridge IJC having a print head IJH including a plurality of print elements and an ink tank IT is mounted. Reference numeral 5002 denotes a paper pressing plate, which presses the recording paper P against the platen 5000 over the moving direction of the carriage HC. Photocouplers 5007 and 5008 are home position detectors for confirming the presence of the carriage lever 5006 in this region and switching the rotation direction of the motor 5013 and the like. Reference numeral 5016 denotes a member for supporting a cap member 5022 for capping the front surface of the recording head IJH. Reference numeral 5015 denotes a suction device for suctioning the inside of the cap, and performs suction recovery of the recording head through an opening 5023 in the cap. Reference numeral 5017 denotes a cleaning blade. Reference numeral 5019 denotes a member capable of moving the blade in the front-rear direction. These members are supported by a main body support plate 5018.
It goes without saying that the blade is not limited to this form and a known cleaning blade can be applied to this example. Also, 5021
Is a lever for starting suction for recovery from suction, moves with the movement of the cam 5020 engaging with the carriage, and the driving force from the drive motor is controlled by a known transmission mechanism such as clutch switching.

The capping, cleaning, and suction recovery are configured so that desired operations can be performed at the corresponding positions by the action of the lead screw 5005 when the carriage comes to the area on the home position side.
If a desired operation is performed at a known timing, any of the embodiments can be applied.

As described above, the ink tank IT and the recording head IJH may be integrally formed to constitute a replaceable ink cartridge IJC. However, the ink tank IT and the recording head IJH are separated. It may be configured so that only the ink tank IT can be replaced when the ink runs out.

FIG. 2 is an external perspective view showing the structure of an ink cartridge IJC in which an ink tank and a head can be separated. In the ink cartridge IJC, as shown in FIG. 2, the ink tank IT and the recording head IJH can be separated at the position of the boundary line K. When the ink cartridge IJC is mounted on the carriage HC, the ink cartridge IJC is provided with an electrode (not shown) for receiving an electric signal supplied from the carriage HC, and the electric signal causes the recording head IJH to operate as described above. Is driven to eject ink.

In FIG. 2, reference numeral 500 denotes an ink ejection port array. In addition, the ink tank IT is provided with a fibrous or porous ink absorber for holding ink, and the ink is held by the ink absorber.

Although the description has been made on the assumption that the liquid droplets ejected from the recording head are ink and that the liquid contained in the ink tank is ink, the contained matter is not limited to ink. . For example, an ink tank may contain a processing liquid discharged to a recording medium in order to improve the fixability and water resistance of the recorded image or to improve the image quality.

General Control Configuration of Apparatus Next, in order to facilitate understanding of the present embodiment, a general control configuration for executing the above-described recording control of the apparatus will be described. Figure 3 shows an inkjet printer IJR
FIG. 2 is a block diagram illustrating a main configuration of a general control circuit A. In the figure showing a control circuit, 101 is a ROM in which a program executed by the MPU is stored, 102 is an MPU, 103 is an interface (I / F) for receiving data from a host computer (not shown), and 104 is an I / F. R for holding data received by F103 and image data to be printed by the recording head 106
AM and 105 are data transfer units that read image data from the RAM 104 and transfer the read image data to the head driver 107. Reference numeral 106 denotes a print head including a plurality of print elements, and 107 denotes a head driver that drives the print head 106.

The data transferred from the host computer (not shown) is stored in a reception buffer in the RAM 104 via the I / F 103. The MPU 102 creates print data and stores it in a print buffer in the RAM 104. At this time, MPU102 and RAM1
Data transfer between 05 is performed via the data transfer unit 105. Bit image data stored in the print buffer and corresponding one-to-one to the dot configuration of the image to be recorded is
Read by the data transfer unit 105 and the head driver 1
Transferred to 07. Data transfer between the RAM 104 and the data transfer unit 105 is controlled by an address signal Address, a data signal Data, a read signal ReadN, and a write signal WriteN. Here, N added to the end of the read and write signal names indicates that the signal is low active. The data transfer unit 105 reads the data in the print buffer in byte units, converts the data into serial data, and transfers the serial data to the head driver 107.

FIG. 4 shows a schematic configuration of the recording head 106.
According to the drawing, the recording head 106 is an inkjet head in which 136 ink jet nozzles (ejection ports) are arranged in a line, and the 24 nozzles from the upper end are supplied with yellow (Y) ink, and Y Form color dots. Similarly,
The next 24 nozzles form magenta (M) dots, the lower 24 nozzles form cyan (C) dots, and the bottom 64 nozzles form black (K) dots. 8 between each color
A gap corresponding to a dot is provided. The print head 106 includes a 136-bit shift register (not shown), and the data stored in the shift register selects whether to drive each nozzle. In the shift register, 136-bit data is connected to one line, so when transferring data to the recording head 106, 24 bits of Y color, 24 dots of M color, 24 dots of C color, and 24 dots of K color are stored in the shift register. It is necessary to arrange print data in the order of dots.

FIG. 5 shows a timing chart for driving the recording head 106. As shown in FIG.
106 is time-division driven by the head driver 107, and 136
The book nozzle is driven by being divided into 16 times. Adjacent nozzles (eg, Y16, Y15,...) Are sequentially driven at different timings.
(Including 8 dots gaps between nozzle groups).

In a serial printer that drives the recording head while scanning the recording paper, such as the ink jet printer of the present embodiment, the deviation of the driving timing of the recording head is a dot deviation on the recording paper. Therefore, measures have been taken to prevent print misalignment. FIG. 6 is a diagram showing the dot arrangement of the recording head 106 in detail. FIG. 3A shows the nozzle arrangement from the first to the twentieth (Y1 to Y20) of yellow, which is the upper part of the recording head 106, and the recording head 106 moves with respect to a vertical line on the recording paper.
Mounted on the carriage at a 3.58 degree angle.
In the figure, L indicates one dot pitch, here, 70.6 μm (360 d
pi). That is, the recording head 106 has an inclination of one dot in the horizontal direction for every 16 dots in the vertical direction. Therefore, at a printing resolution of 720 dpi, the dot sequence formed on the recording paper by the drive sequence shown in FIG. 5 is as shown in FIG. 6B. According to FIG. 6B, the shift in the drive timing of the time-division driving is offset by the inclination of the nozzles of the recording head 106, so that the dots from the first nozzle to the eighth nozzle are arranged vertically and the ninth nozzle It can be seen that the dots from the nozzle to the 16th nozzle are formed so as to be vertically arranged with a distance of 1/2 dot to the right. That is, when viewed from the entire recording head 106, dots in the adjacent row are formed every eight nozzles as shown in FIG. 7, and by driving the entire recording head 106 once, a half dot is formed on the recording paper. A total of 20 dot rows are formed in a stepwise manner at intervals.

Hereinafter, the data transfer processing in the data transfer section 105 will be described in detail.

FIG. 8 shows a data transfer unit 105 in which a RAM 104
FIG. 3 is a block diagram illustrating a configuration of an address generation circuit that generates an address for reading a print buffer and a mask buffer in the memory. Here, the mask buffer stores mask data for performing appropriate mask processing on the print data read from the print buffer, and uses a part of the RAM 104.

In FIG. 8, reference numerals 601 to 610 denote first address generation circuits for generating addresses PBA0 to PBA18 for reading a print buffer, and an address (K, Y, M, C) register
601a-d, horizontal offset (KH, YH, MH, CH) register 602
a to 602d, selector 603, save register 604, selector 60
5, selector 606, mask circuit 607, inverting / non-inverting circuit 60
8. It comprises an adder 609 and a carry control circuit 610.

The data signals D0 to D15 are data buses of the MPU 102, and set a value in each register. Address register
601a-d store the start address of each color, and the horizontal offset registers 602a-d store the horizontal offset value of each color. Outputs of the address registers 601a to 601d are selected by the selector 603 and output as signals PBA0 to PBA18. The save register 604 temporarily holds the value output by the selector 603 and outputs the signals LA0 to LA18. Selector 605 is a PBA0 ~
18 and one of LA0 to 18 are selected to output signals SA0 to SA18. The selector 606 selects the output of the horizontal offset registers 602a-602d. The mask circuit 607 controls the mask of the output of the selector 606. The output value of the mask circuit 607 is 0 in the mask state, and the selector 6
The output value of 06 is output as is. Inverting / non-inverting circuit 60
8 controls the inversion / non-inversion of the output of the mask circuit 607.
For example, in the case of generating an address in the reverse direction in bidirectional printing, the inversion control is performed. The adder 609 is connected to the selector 6
The output value of 05 and the output value of the inverting / non-inverting circuit 608 are added to output signals NPA0 to NPA18. Carry control circuit 610 controls the carry input signal of adder 609. The output signals NPA0 to NPA18 of the adder 609 are input to the address registers 601a to 601d, and reset the address value.

Reference numerals 612 to 622 denote second address generating circuits for generating addresses MBA0 to MBA18 for reading the mask buffer. The function of each configuration in the second address generation circuit is equivalent to each of the configurations 601 to 610 of the above-described first address generation circuit, and a detailed description thereof will be omitted. However, in the second address generation circuit, the Y, M, and C horizontal offset registers are integrated as a color horizontal offset (LHM) register 613b. Also, the staircase pattern (Z
The P) register 623 is connected to the data signals D0 to D15 and stores the staircase pattern of the recording head 106. Here, the staircase pattern is data indicating the shape of a dot row formed by one driving of the recording head 106. The selector 624 selects staircase pattern data. The output of the selector 624 is input to the mask circuits 607 and 619, and controls the mask state.

The selector 611 switches between the print buffer addresses PBA0 to PBA18 and the mask buffer addresses MBA0 to MBA18.

FIG. 9 shows the concept of the data structure of the print buffer. According to FIG. 9, the print buffer is
It is divided into four areas of Y, M, C, and K. The rectangle indicated by the rectangle in each area indicates 1-byte print data,
The mathematical expression in the rectangle indicates the address where the print data is stored. In the formula, Y, M, C, and K are start addresses of each color, and YH, MH, CH, and KH are horizontal offset values of each color. Data to be printed by one drive of the recording head 107 is indicated by hatched portions in FIG. 9, that is, three bytes of addresses Y, Y + 1 + YH, Y + 2 + 2YH, and addresses M and M + 1. +
3 bytes of MH, M + 2 + 2MH, addresses C, C + 1 + CH, C + 2 + 2CH
3 bytes and address K, K + 1 + KH, K + 2 + 2KH,…, K + 7 + 7KH
8 bytes. Therefore, when transferring print data to the recording head 106, it is necessary to read the print buffer diagonally. The order in which the areas are arranged in the print buffer is not particularly limited, for example, in the order of Y, M, C, and K.

FIG. 10 is a timing chart showing the operation of the address generation circuit shown in FIG. 8 during forward printing. In FIG. 8, since the operations of the first address generation circuit for generating the print buffer address and the second address generation circuit for generating the mask buffer address are almost the same, the operation of the first address generation circuit will be described below. I do.

The first address generation circuit generates an address in synchronization with the CLK signal. Predetermined values are set in the address registers 601a to 601d and the horizontal offset registers 602a to 602d in advance. The value of the staircase pattern register 623 is set so as to be set for every 8 dots of the print data, that is, for every 1 byte. When the data transfer unit 105 starts reading the print buffer, first, the value Y of the address register 601b is selected by the selector 603, and the signal PBA0
Output as ~ 18. At this time, since the selector 611 has selected the print buffer address, the values of PBA0 to PBA18 are output as the address signal Address of the RAM 104. At this time, a read pulse is output from the data transfer unit 105 as the read signal ReadN. Therefore, the print data is read from the address Y of the RAM 104 to the data transfer unit 105 and transferred to the recording head 106. The read start address Y is stored in the save register 604.

The selector 605 selects PBA0 to PBA18, the selector 606 selects the value YH of the horizontal offset register 602b, and the output of the selector 624 is the staircase pattern register 623.
Is set according to the setting of the mask circuit 607.
Is in a non-mask state, and outputs the value YH of the horizontal offset register 602b. Since the inversion / non-inversion circuit 608 is controlled to be non-inversion, the output of the mask circuit 607 is output as it is. Since the carry control circuit 610 sets the carry, the added value is + 1 + YH, and the output NP of the adder 609 is
The value of A0 to 18 is Y + 1 + YH. This value is fed back to the address register 601b. Therefore, the value of the address register 601b is set to Y + 1 + YH at the next clock, and RAM1
The print data is read from the address Y + 1 + YH of 04 and transferred to the recording head 106.

At this time, since the output of the selector 624 is set by the setting of the staircase pattern register 623, the mask circuit 607 is in a non-masked state and outputs the value YH of the horizontal offset register 602b. Therefore, the added value becomes + 1 + YH, and the value of the address register 601b becomes Y + 2 + 2YH at the next clock. Therefore, in the data transfer unit 105, for the yellow print buffer, three bytes of data at addresses Y, Y + 1 + YH, and Y + 2 + 2YH are transferred to the recording head 106. When the address Y + 2 + 2YH is read, the selector 605 outputs the value Y (LA0-18) held in the save register 604 as SA0-18.
Further, the mask circuit 607 is in a non-mask state and outputs YH, and the carry control circuit 610 resets the carry, so that the added value becomes YH, so that the value Y + YH of NPA0 to NPA18 is set in the address register 601b. You.

Similarly, magenta, cyan, and black print data are sequentially read out by the data transfer unit 105 in three-byte units and transferred to the recording head 106. However,
Eight bytes are transferred for black print data.

The address generating circuit shown in FIG. 8 includes a first address generating circuit for generating a print buffer address and a second address generating circuit for generating a mask buffer address.
It is controlled to operate once. The selector 611 switches and outputs the print buffer addresses PBA0 to PBA18 and the mask buffer addresses MBA0 to MBA18 every clock. Since the output of the address generation circuit by the selector 611 is connected to the address signal Address of the RAM 104, the data transfer unit
In 105, data can be alternately read from the print buffer and mask buffer of the RAM 104. The data transfer unit 105 performs an AND operation on the data read from the print buffer using the subsequently read mask data, and then transfers the data to the print head 106.

As described above, in a general serial printer, the read addresses of the print buffer and the mask buffer are controlled in accordance with the nozzle arrangement of the print head 106 and the print timing shift for each pixel caused by the drive timing thereof. By doing so, appropriate recording was realized.

The control configuration of the embodiment will be described below.

The nozzle configuration and the dot arrangement of the recording head in this embodiment are the same as those shown in FIGS. 4, 6, and 7. In 720 dpi printing, a dot row vertically arranged by 8 dots is formed.

Further, each nozzle in this embodiment can discharge two types of ink droplets having different dot diameters. FIG. 11 is a diagram illustrating a state of image formation by the recording head of the present embodiment. As shown in (a) of the figure, first, large dots and small dots are alternately formed by 8 dots in the nozzle direction. Then, as shown in (b), the large dot and the small dot are shifted by one dot in the main scanning direction, superimposed on the dot formed in (a) (dots indicated by oblique lines), and eight dots in the nozzle direction again. Form alternately. In the figure, L is one dot pitch. In this way, two types of dots having different diameters (large dot and small dot) are 8 dots each in the nozzle direction,
An image is formed by alternately overlapping large dots and small dots every other dot in the main scanning direction. Hereinafter, image formation in which large / small dots are alternately overlapped in this embodiment is referred to as interlaced printing.

Hereinafter, a control configuration of the present embodiment for executing print control in the above-described ink jet printer IJRA shown in FIG. 1 will be described. FIG. 12 is a block diagram illustrating a main configuration of a control circuit of the inkjet printer IJRA according to the present embodiment. In FIG.
Since 1006 and 1013 are equivalent to 101 to 106 and 107 shown in FIG. 3, detailed description is omitted. Reference numeral 1007 denotes an address generation circuit for reading data stored in the print buffer and the mask buffer. In the present embodiment, the internal configuration of the address generation circuit 1007 is the same as that in FIG. 8 described above so that the general configuration of the buffer in the serial printer can be used without being changed. 1008 is based on the data read from the print buffer and the data read from the mask buffer.
This is a bit image generation circuit that generates bit image data of large dots and small dots corresponding to the dot configuration of the image to be recorded on a one-to-one basis. Reference numeral 1009 denotes a FIFO unit that temporarily holds the bit image data generated by the bit image generation circuit 1008. 1010 and 1011 are FIFO units 1009
A write control circuit and a read control circuit that control writing and reading of data to and from the memory. 1012 FI
The parallel-to-serial conversion circuit converts parallel data read from the FO unit 1009 into serial data (hereinafter, parallel-to-serial conversion).

Hereinafter, the image forming process in this embodiment will be described.

Image data transferred from an external device such as a host computer is stored in a reception buffer in a RAM 1004 via an I / F 1003. The MPU 1002 creates print data and stores it in a print buffer in the RAM 1004. At this time, data transfer between the MPU 1002 and the RAM 1004 is performed by the data transfer unit 10
Data reading from the print buffer and the mask buffer is performed by the address generation circuit 1007.

In interlaced printing using large dots and small dots, which is a feature of the present embodiment, data input from the host computer is not directly printed but is stored in the mask buffer and the input data from the host computer. The bit image data to be actually printed is generated based on the mask data and the printing is performed in accordance with the bit image data. Therefore, the bit image generation circuit 1008 generates bit image data to be used for an actual printing operation based on the data read from the print buffer and the mask buffer. In the present embodiment, the scanning direction 72 input from the host computer is used.
For 0 dpi data, large dot data and small dot data are generated for each one column based on data corresponding to two columns of this data and mask column data for two columns. Thus, in this embodiment,
Print data is generated for each bit using two columns as one unit.

FIG. 13 shows the concept of print data generation in this embodiment, which will be described below. In the figure, P1-i
(i = 1 ... 16) is the first column data read from the print buffer, P2-i is the second column data read from the print buffer, and M1-i is read from the mask buffer
Data in the first column, M2-i is data in the second column read from the mask buffer, and D1-i and S1-i are data P1-i, P2-i, M1 in the read two columns. -i, M2-
Large dot data and small dot data generated based on the 4 bits of i are shown.

Accordingly, the timing of reading data from the print buffer and the mask buffer is as shown in FIG. 14, although the details will be described later. That is, in FIG.
As can be understood from Address, when generating data to be printed by one drive of the recording head 1006, the data in the print buffer and the mask buffer are stored at addresses Y and Y + YH in the print buffer, and YM and YM + LHM in the mask buffer. address,
Print buffer addresses Y + 1, Y + 1 + YH, mask buffer addresses YM + 1, YM + 1 + LHM, ..., print buffer K + 7 + 7K
H, K + 7 + 8KH, KM + 7 + 7KHM, KM + 7 + 8K of mask buffer
The data is read alternately every two bytes in the order of addresses HM. Hereinafter, generation of the read address in the present embodiment will be described in detail.

[Buffer Read Address Generation Processing] Here, the operation of the address generation circuit 1007 of the present embodiment for generating read addresses in the above order will be described in detail. As described above, the detailed configuration of the address generation circuit 1007 in the present embodiment is the same as that in FIG. The address generation circuit 1007 generates an address in synchronization with the CLK signal. Predetermined values are set in the address registers 601a-d and 612a-d and the horizontal offset registers 602a-d and 613a, b in advance. Further, since data is read from the print buffer and the mask buffer every two columns, the staircase pattern register 623 is set so that a predetermined value is set every two bytes. The outputs of the carry control circuits 610 and 622 are connected to the least significant bit and the second least significant bit of the adders 609 and 621, and the carry is input to either of them at a predetermined timing.

First, 2-byte data is read from the print buffer. When the data transfer unit 1005 starts reading the print buffer, first the address register
The value Y of 601b is selected by the selector 603, and the signals PBA0 to
Output as 18. At this time, since the selector 611 has selected the print buffer address, the values of PBA0 to PBA18 are
The read signal is output as the address signal Address of the RAM 1004, and a read pulse is output as the read signal ReadN. Therefore, RAM10
The print data is read from the address Y of address 04 and transferred to the bit image generation circuit 1008. Here, the start address Y at the time of reading is stored in the save register 604.

The selector 605 selects PBA0-18, the selector 606 selects the value YH of the horizontal offset register 602b, and the output of the selector 624 outputs the staircase pattern register 623.
Is set according to the setting of the mask circuit 607.
Is in a non-mask state, and outputs the value YH of the horizontal offset register 602b. Since the inversion / non-inversion circuit 608 is controlled to be non-inversion, the output of the mask circuit 607 is output as it is. Here, since the carry control circuit 610 does not generate a carry, the added value is + YH, and the output of the adder 609 is output.
The value of NPA0-18 is Y + YH. This value is fed back to the address register 601b. Therefore, the value of the address register 601b transferred to the bit image generation circuit 1008 is set to Y + YH at the next clock, and the address Y of the RAM 1004 is
The print data is read from the address + YH.

At this time, the selector 606 selects the value YH of the horizontal offset register 602b, but the mask circuit 607
Is in a mask state, and its output value is 0. Also,
Since the carry generated by carry control circuit 610 is input to the least significant bit of adder 609, the added value is +1. Further, the selector 605 has selected the output value Y of the save register 604, and the output of the adder 609 is Y + 1. Therefore,
The value of the address register 601b is set to Y + 1 at the next clock.

Next, 2-byte data is read from the mask buffer. When the data transfer unit 1005 starts reading the mask buffer, first, the address register 612b
Is selected by selector 615, and signals MBA0-18
Is output as At this time, since the selector 611 has selected the mask buffer address, the value of MBA0 to
004 is output as the address signal Address and the read signal R is output.
A read pulse is output to eadN. Therefore, the mask data is read from the address YM of the RAM 1004 and transferred to the bit image generation circuit 1008. Here, the start address YM at the time of reading is stored in the save register 616.

Then, the selector 617 selects MBA0-18, and the selector 618 selects the value LHM of the horizontal offset register 613b.
Is selected, and the output of the selector 624 is set by the setting of the staircase pattern register 623, so that the mask circuit 619 is in a non-masked state, and outputs the value LHM of the horizontal offset register 613b. Inverting / non-inverting circuit 6
Since 20 is controlled to be non-inverted, the output of the mask circuit 619 is output as it is. Here, the carry control circuit 622
Does not generate carry, the added value is + LHM, and the output value of the adder 621 is YM + LHM. This value is fed back to the address register 612b. Therefore, the value of the address register 612b is set to YM + LHM at the next clock,
Print data is read from the address YM + LHM of the RAM 1004 and transferred to the bit image generation circuit 1008.

At this time, although the selector 618 has selected the value LHM of the horizontal offset register 613b, the mask circuit 619
Is in a mask state, and its output value is 0. Also,
Since the carry generated by carry control circuit 622 is input to the least significant bit of adder 621, the added value is +1. The selector 617 has selected the output of the save register 616, and the output of the adder 621 is YM + 1. Therefore, the value of the address register 612b is set to YM + 1 at the next clock, and the mask data is read from the address YM + 1 of the RAM 1004 and transferred to the bit image generation circuit 1008.

Next, the process returns to the data reading sequence of the print buffer. With the value Y + 1 of the address register 601b set as described above, the print data is read from the address Y + 1 of the RAM 1004 and transferred to the bit image generation circuit 1008. Here, the value Y is stored in the save register 604.
Remains stored. The selector 605 selects PBA0 to PBA18, and the output of the selector 624 is set by the setting of the staircase pattern register 623, so that the mask circuit 607 is in a non-masked state and the value of the horizontal offset register 602b is set.
Outputs YH. Since the inversion / non-inversion circuit 608 is controlled to be non-inversion, the output of the mask circuit 607 is output as it is. Since carry control circuit 610 does not generate carry, the added value is + YH, and the values of outputs NPA0-18 of adder 609 are Y + 1 + YH. This value is fed back to the address register 601b, the print data is read from the address Y + 1 + YH of the RAM 1004, and the bit image generation circuit 10
Transferred to 08.

At this time, since the output of the selector 624 is set by the setting of the step pattern register 623, the mask circuit 607 is in a non-mask state. Here, the output YH of the horizontal offset register 602b becomes 2YH by being shifted by one bit by a shift circuit (not shown). The carry generated by carry control circuit 610 is added to adder 6
The input value is +2+
2YH. Since the selector 605 has selected the output of the save register 604, the values of the outputs NPA0 to NPA18 of the adder 609 are Y + 2 + 2YH. Therefore, the value of the address register 601b becomes Y + 2 + 2YH at the next clock.

Next, the process returns to the data reading sequence of the mask buffer. As in the case of reading from the print buffer described above, YM + 1,
The data at address YM + 1 + LHM is read and the address register
Update 612b to YM + 2 + 2LHM.

Next, returning to the data reading sequence of the print buffer, the value Y + 2 + of the address register 601b is read again.
With 2YH, print data is read from the address Y + 2 + 2YH of the RAM 1004 and transferred to the bit image generation circuit 1008. Here, the value Y is still stored in the save register 604. The selector 605 selects PBA0 to PBA18, and the output of the selector 624 is set by the setting of the staircase pattern register 623, so that the mask circuit 607 is in a non-masked state and outputs the value YH of the horizontal offset register 602b. Since the inversion / non-inversion circuit 608 is non-inversion, the output value of the mask circuit 607 is output as it is. Since carry control circuit 610 does not generate carry, the added value is + YH, and the values of outputs NPA0-18 of adder 609 are Y + 2 + 3YH. This value is fed back to the address register 601b, and RA
Print data is read from the address Y + 2 + 3YH of M1004 and transferred to the bit image generation circuit 1008.

At this time, since the output of the selector 624 is set by the setting of the staircase pattern register 623, the mask circuit 607 is in a non-mask state, and the output YH of the horizontal offset register 602b is output by a shift circuit (not shown).
Since the carry is shifted by one bit to 2YH and no carry occurs in carry control circuit 610, the added value is + 2YH
Becomes Also, since the selector 605 has selected the output of the save register 604, the output of the adder 609 is Y + 2YH. Therefore, the value of the address register 601b becomes Y + 2Y at the next clock.
H. At this time, the save register 604 is cleared.

Next, returning to the read sequence of the data of the mask buffer, the data of the addresses YM + 2 + 2LHM and YM + 2 + 3LHM are similarly read, and the address register 612b is updated to YM + 2LHM. At this time, the save register 616 is cleared.

In this manner, when generating data to be printed by one drive of the recording head 1006, 6 bytes of yellow data are read from the print buffer by 6 bytes each of 2 bytes from the print buffer. And transferred to the bit image generation circuit 1008. Similarly, magenta, cyan, and black data are sequentially read and transferred to the bit image generation circuit 1008. However, for black, 16 bytes are read from both buffers and transferred.

As described above, in the serial printer according to the present embodiment, the control of the read addresses of the print buffer and the mask buffer can be realized with almost the same configuration as the conventional one.

Bit Image Data Generation In the bit image generation circuit 1008, every time 2 bytes of read data from the print buffer and 2 bytes of read data from the mask buffer are ready, 1 byte of large dot data and 1 byte of small dot data Generate one byte.

FIG. 15 is a diagram showing the correspondence between the print data generated by the bit image generation circuit 1008 and each nozzle of the recording head 1006. In the figure, one square represents 8-bit data (corresponding to eight nozzles), and a square indicated by uppercase letters represents data for large dots, and a square indicated by lowercase letters represents data for small dots. Print data corresponding to one column of large dot data and one column of small dot data is generated based on the data of two columns read from the print buffer and the mask buffer, respectively. That is, the bit image generation circuit 1008 generates print data corresponding to the cells indicated by hatching in FIG. However, in practice, the recording head 10
The nozzle array 06 has an inclination as shown in FIG. 6 (a), and large dots and small dots must be alternately printed in 8-dot units as shown in FIG. 11 (b). .
Accordingly, the bit image data generated in the bit image generation circuit 1008 is, for example, Y1A, Y2a, Y3B, M1C, M2c, M3D, C1E, C2e, C3
F, K1G, K2g, K3H, K4h, K5I, K6i, K7J, K8j
The corresponding print data is finally converted to serial data (parallel-serial conversion) in the parallel-serial conversion circuit 1012 via the FIFO unit 1009, and then transferred to the head driver 1013.

Bit Image Data Transfer As described above, the print data generated in the bit image generation circuit 1008 is transferred to the head driver 10 in the order of generation.
It is not forwarded to 13. Therefore, it is necessary to temporarily hold the generated bit image data, select predetermined data at the timing of printing, and transfer the selected data to the head driver 1013. In the present embodiment, the generated bit image data is temporarily stored in the FIFO unit 1009, and data to be printed is selected and transferred to the head driver 1013. This FI
Writing and reading of data to and from the FO unit 1009 are controlled by a write control circuit 1010 and a read control circuit 1011, respectively.

FIG. 16 is a block diagram showing a schematic internal configuration of the FIFO unit 1009. The FIFO unit 1009 has an 8-bit × 17-stage FIF.
O1, FIFO2, 8-bit × 4-stage FIFO3, readout circuit 10
The selector 1504 is configured to select the outputs (8 bits) of FIFO1 to FIFO3 under the control of 11. The output data DIN [7 ... 0] of the bit image generation circuit 1008 is supplied to the FI by the write enable signals WE [1 ... 0] from the write control circuit
It is held in any of FO1 to FIFO3. Also, FIFO1 17
Data of the first row, the 17th row of FIFO2, and the fourth row of FIFO3 (8 bits)
Are connected to a selector 1504, and can be arbitrarily selected as output data DOUT [7 ... 0] by a read select signal RSEL [1 ... 0] from a read control circuit 1011.

The print data DOUT [7 ... 0] selected by the selector 1504 is sent to the parallel-serial conversion circuit 1012. Figure
17A and 17B are timing charts for reading large dot data and small dot data from the FIFO unit 1009, and show successive timings from FIG. 17A to FIG. 17B. In the drawing, Y1A, Y1a,... Correspond to the symbols of each cell shown in FIG. 15, and P1 to P17 and Q1 to Q10 are initial data held in the FIFO unit 1009 in advance. The latch pulse has two functions: a trigger signal of a sequence for creating bit image data and transferring it as print data to the head driver 1013, and a latch signal for determining print data to be transferred to the head driver 1013.

As shown in FIGS. 17A and 17B, initially generated bit image data Y1A and Y1a are held in FIFO1 and FIFO2 by write enable signals WE [1... 0] of write control circuit 1010, respectively. . Then, the next generated Y2A and Y2a are held in FIFO3 and FIFO1, respectively. As described above, according to FIGS. 17A and 17B, the bit image data generated by the bit image generation circuit 1008 is held in any of FIFO1 to FIFO3 in the order of generation. The read control circuit 1011 starts reading with the latch pulse as a trigger, selects any one of FIFO1 to FIFO3 every time bit image data is generated by the bit image generation circuit 1008, and is held in the selected FIFO. The bit image data is sent to the parallel-serial conversion circuit 1012 as print data. For example, in FIG. 17B, for example, when FIFO2 is selected, Y1A, Y2
a, Y3B, M1C, M2c,..., K6i, K7J, K8j are sent to the parallel-serial conversion circuit 1012 in this order. The parallel-serial conversion circuit 1012 converts these bit image data into serial data and transfers the serial data to the head driver 1013.

As described above, the FIFO for temporarily holding data is arbitrarily determined by the write control circuit 1010, and the read data from the FIFO unit 1009 can be arbitrarily selected by the read control circuit 1011. At a predetermined timing regardless of the order in which the data was generated,
It is possible to transfer print data corresponding to the nozzle arrangement of the recording head 1006.

Processing Flowchart An outline of the flow of the image forming processing in the present embodiment described above is shown in the flowchart of FIG.

First, in step S 200, image data input from a host computer or the like to the serial printer of this embodiment is stored in a print buffer on the RAM 1004. In the mask buffer, mask data may be stored in advance, or may be input together with image data. Next, in step S201, the read address of the print buffer and the mask buffer is generated by the address generation circuit 1007 as described above.
Read in S202. Then, in step S203, the bit image generation circuit 1008 generates bit image data having different dot diameters.

Then, in step S204, the generated bit data is written to a FIFO unit 1009 composed of a plurality of FIFOs, temporarily stored, and then read out from the FIFO unit 1009 in step S205. In steps S204 and S205, the write control circuit 1010 and the read control circuit 1011
By controlling the order of writing and reading the bit image data to and from the FO unit 1009, the bit images are output in a different order from the order of generation.

In step S206, the FIFO unit 1009
After the bit image data output from is converted into serial data by the parallel-serial conversion circuit 1012, the
Is transferred to the head driver 107 and is used for image formation by the recording head 106.

As described above, according to the present embodiment,
Large dot data and small dot data are created based on the input image data and mask pattern, and bit image data matched to the nozzle arrangement of the print head can be transferred to the head driver at high speed. Further, since the buffer configuration for holding the input image data is not different from the conventional one, print data can be created and transferred regardless of the dot diameter. In this case, since the processing is performed by hardware, the throughput of the printer is not reduced.

<Modification of this Embodiment> In this embodiment, an example in which two types of large and small dots having different diameters are formed by the recording head has been described. The feature of this embodiment is that print data is created and transferred. The method for changing the actual dot diameter in the recording head is not particularly limited.

In the present embodiment, an example has been described in which two types of bit image data corresponding to large dots and small dots are generated. However, the present invention is not limited to this example, and is applicable to dots having different diameters. The present invention is also applicable to a case where three or more types of bit image data are generated.

Although the present embodiment has been described with respect to an example in which the present invention is applied particularly to an ink jet printer, the present invention drives a recording head having a plurality of recording elements while scanning a recording sheet. A so-called serial printer is applicable.

In this embodiment, an example has been described in which print data is subjected to an appropriate mask process and then transferred to the printhead. However, if the input print data is output as it is, the mask process is necessary. Absent. In addition, the present invention is of course applicable to a printer having a monochrome recording head.

In the present embodiment, a means (for example, an electrothermal converter or a laser beam) for generating thermal energy as energy used for discharging ink is provided, particularly in the ink jet recording system. The printing apparatus of the type in which the change of the state of the ink (film boiling) is caused by the energy has been described. However, according to the bubble jet type, it is possible to achieve higher density and higher definition of the recording.

As for the representative configuration and principle, it is preferable to use the basic principle disclosed in, for example, US Pat. Nos. 4,723,129 and 4,740,796. This method can be applied to both the so-called on-demand type and continuous type.In particular, in the case of the on-demand type, it is arranged corresponding to the sheet or liquid path holding the liquid (ink). Electrothermal transducers
By applying at least one drive signal corresponding to the recorded information and providing a rapid temperature rise exceeding the film boiling, heat energy is generated in the electrothermal transducer, thereby causing film boiling on the heat acting surface of the recording head. As a result, bubbles in the liquid (ink) corresponding to the drive signal on a one-to-one basis can be formed, which is effective. By discharging the liquid (ink) through the discharge opening by the growth and contraction of the bubble, at least one droplet is formed. When the drive signal is formed into a pulse shape, the growth and shrinkage of the bubble are performed immediately and appropriately, so that the ejection of the liquid (ink) having particularly excellent responsiveness can be achieved, which is more preferable.

As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. Further, when the conditions described in US Pat. No. 4,313,124 relating to the temperature rise rate of the heat acting surface are adopted, more excellent recording can be performed.

As the configuration of the recording head, in addition to the combination (straight liquid flow path or right-angle liquid flow path) of the combination of the discharge port, liquid path, and electrothermal converter as disclosed in the above-mentioned respective specifications, A configuration using U.S. Pat. No. 4,558,333 and U.S. Pat. No. 4,459,600 which disclose a configuration in which a heat acting surface is arranged in a bending area is also included in the present invention. In addition, Japanese Patent Application Laid-Open No. S59-5959 discloses a configuration in which a common slot is used as a discharge portion of an electrothermal converter for a plurality of electrothermal converters.
And JP-A-59-138461 which discloses a configuration in which an opening for absorbing a pressure wave of thermal energy corresponds to a discharge portion.
The configuration may be based on Japanese Patent Publication No.

Further, as a full-line type recording head having a length corresponding to the width of the maximum recording medium that can be recorded by the recording apparatus, the length is determined by combining a plurality of recording heads as disclosed in the above-mentioned specification. This may be either a configuration satisfying the above requirements or a configuration as a single recording head formed integrally.

In addition, the print head is replaceable with a print head of a replaceable chip type, which can be electrically connected to the main body of the apparatus or supplied with ink from the main body of the apparatus, or integrated with the print head itself. Alternatively, a cartridge type recording head provided with an ink tank may be used.

It is preferable to add recovery means for the recording head, preliminary auxiliary means, and the like provided as components of the recording apparatus of the present invention since the effects of the present invention can be further stabilized. . If these are specifically mentioned, capping means for the recording head, cleaning means, pressurizing or suction means, preheating means using an electrothermal transducer or another heating element or a combination thereof, and printing Performing a preliminary ejection mode for performing another ejection is also effective for performing stable printing.

Further, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, and may be a single recording head or a combination of a plurality of recording heads. Alternatively, the apparatus may be provided with at least one of full colors by color mixture.

In the embodiments of the present invention described above, the ink is described as a liquid. However, an ink which solidifies at room temperature or lower, or an ink which softens or liquefies at room temperature may be used. In general, in the ink jet method, the temperature of the ink itself is adjusted within a range of 30 ° C. or more and 70 ° C. or less to control the temperature so that the viscosity of the ink is in a stable ejection range. It is sufficient if the ink is in a liquid state.

In addition, in order to positively prevent the temperature rise due to thermal energy as energy for changing the state of the ink from the solid state to the liquid state, the temperature is positively prevented.
Alternatively, in order to prevent evaporation of the ink, an ink which solidifies in a standing state and liquefies by heating may be used. In any case, the application of heat energy causes the ink to be liquefied by application of the heat energy according to the recording signal and the liquid ink to be ejected, or to start to solidify when reaching the recording medium. The present invention is also applicable to a case where an ink having a property of liquefying for the first time is used. In such a case, as described in JP-A-54-56847 or JP-A-60-71260, the ink is held as a liquid or solid in a porous sheet recess or through hole, It is good also as a form which opposes an electrothermal transducer. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

In addition, as a form of the recording apparatus according to the present invention, in addition to those provided integrally or separately as an image output terminal of an information processing apparatus such as a computer, a copying apparatus combined with a reader and the like, It may take the form of a facsimile machine having functions.

In this embodiment, the droplets ejected from the recording head are described as being ink, and the liquid contained in the ink tank is described as being ink. However, the contained material is limited to ink. It is not something to be done. For example, an ink tank may contain a processing liquid discharged to a recording medium in order to improve the fixability and water resistance of the recorded image or to improve the image quality.

<Other Embodiments> Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (a single device) may be used. For example, the present invention may be applied to a copying machine, a facsimile machine, and the like.

Further, an object of the present invention is to provide a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU or MP) of the system or the apparatus.
It goes without saying that U) is also achieved by reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

As a storage medium for supplying the program code, for example, a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like is used. Can be.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

[0097]

As described above, according to the present invention, highly detailed image formation using a plurality of types of dots can be realized without lowering the throughput. As a result, the degree of freedom in image formation is dramatically increased, and a higher-definition image can be formed.

[0098]

[Brief description of the drawings]

FIG. 1 is an external perspective view illustrating a schematic configuration of an inkjet printer according to an embodiment of the present invention.

FIG. 2 is an external perspective view illustrating a configuration of an ink cartridge.

FIG. 3 is a block diagram illustrating a main configuration of a general control circuit of the inkjet printer.

FIG. 4 is a diagram illustrating a dot configuration of a recording head.

FIG. 5 is a timing chart illustrating a print head driving sequence.

FIG. 6 is a diagram illustrating in detail a part of a dot array of the recording head.

FIG. 7 is a diagram illustrating a dot arrangement of the entire recording head.

FIG. 8 is a block diagram illustrating a general configuration of a buffer address generation circuit in the data transfer unit.

FIG. 9 is a diagram illustrating a general data structure of a print buffer.

FIG. 10 is a timing chart illustrating general address generation processing in the address generation circuit.

FIG. 11 is a diagram illustrating a state of image formation in the present embodiment.

FIG. 12 is a block diagram illustrating a main configuration of a control circuit according to the present embodiment.

FIG. 13 is a diagram illustrating the concept of a bit image generation process according to the present embodiment.

FIG. 14 is a timing chart illustrating an address generation process in the address generation circuit according to the present embodiment.

FIG. 15 is a diagram illustrating a correspondence between print data generated in the present embodiment and each nozzle of a print head.

FIG. 16 is a block diagram illustrating an internal configuration of a FIFO unit according to the present embodiment.

FIG. 17A is a diagram illustrating F of bit image data according to the present embodiment.
6 is a timing chart showing a write / read process to an IFO unit.

FIG. 17B illustrates F of bit image data in the present embodiment.
6 is a timing chart showing a write / read process to an IFO unit.

FIG. 18 is a flowchart illustrating an image forming process according to the present embodiment.

[Explanation of symbols]

 1001 ROM 1002 MPU 1003 interface 1004 RAM 1005 data transfer section 1006 print head 1007 address generation circuit 1008 bit image generation circuit 1009 FIFO section 1010 write control circuit 1011 read control circuit 1012 parallel-serial conversion circuit 1013 head driver

Claims (16)

[Claims] An image forming apparatus that forms an image on a recording medium by scanning a recording head including a plurality of recording elements, comprising: an image data holding unit that holds input image data; Address control means for controlling an address for reading data from the holding means; and a bit for generating a plurality of types of bit image data based on the data read from the image data holding means in accordance with the address controlled by the address control means. An image generation unit; a bit image holding unit for temporarily holding the plurality of types of bit image data; and the bit image holding unit so that the plurality of types of bit image data are output in an order different from the generation order. Bit image control means for controlling the input order and output order of the Preparative image based on an output a plurality of types of bit image data from the holding means, the image forming apparatus characterized by having an image forming means for forming an image on a recording medium by driving the recording head. 2. The image forming apparatus according to claim 1, wherein the bit image generating unit generates bit image data having different dot diameters. 3. The image forming apparatus according to claim 2, wherein the bit image generation unit generates two types of bit image data having different dot diameters. 4. The image forming apparatus according to claim 1, wherein the bit image holding unit outputs already stored data in response to input of new data. 5. The method according to claim 1, wherein the bit image holding unit includes a plurality of F
5. The image forming apparatus according to claim 4, comprising an IFO circuit. 6. The image forming apparatus according to claim 5, wherein the bit image control unit controls which of the plurality of FIFO circuits receives the bit image data. 7. The image forming apparatus according to claim 6, wherein the bit image control unit controls which of the plurality of FIFO circuits outputs the bit image data. And a mask data holding unit for holding mask data for generating bit image data based on the image data, wherein the address control unit reads the mask data from the mask data holding unit. The bit image generating means, based on the data read from the image data holding means and the mask data read from the mask data holding means in accordance with the address controlled by the address control means, 2. The image forming apparatus according to claim 1, wherein the bit image data is generated. 9. A parallel-serial conversion unit for converting bit image data output from the bit image holding unit into serial data, wherein the image forming unit converts the bit image data converted to serial data by the parallel-serial conversion unit. 2. The image forming apparatus according to claim 1, wherein the recording head is driven to form an image on a recording medium based on the image data. 10. The image forming apparatus according to claim 1, wherein the recording head is configured such that a plurality of recording elements are driven with a predetermined delay. 11. The image forming apparatus according to claim 10, wherein the recording head arranges a plurality of recording elements in a state inclined from a conveying direction of a recording medium. 12. The image forming apparatus according to claim 1, wherein the recording head is an inkjet recording head that performs recording by discharging ink. 13. The recording head according to claim 1, wherein the recording head ejects ink by using thermal energy, and includes a thermal energy converter for generating thermal energy applied to the ink. Item 13. The image forming apparatus according to Item 12. 14. An image forming control method in an image forming apparatus for forming an image on a recording medium by scanning a recording head including a plurality of recording elements, wherein the data is stored in a memory holding input image data. An address generating step of generating an address for reading; a memory reading step of reading image data from the memory according to the address generated in the address generating step; and a plurality of types of bit image data based on the data read from the memory. Generating a bit image, a bit image inputting step of inputting the plurality of types of bit image data to a temporary memory, a bit image output step of outputting bit image data from the temporary memory, and an output from the temporary memory. Based on the bit image A head driving step of driving a head, wherein in the bit image input step and the bit image output step, the plurality of types of bit image data are output in a different order from the generation order, An image forming control method comprising controlling an input order and an output order to a memory. 15. The image forming control method according to claim 14, wherein the temporary memory includes a plurality of FIFOs. 16. A computer-readable memory in which a program code for image processing in an image forming apparatus that forms an image on a recording medium by scanning a recording head including a plurality of recording elements is stored, wherein the program code is A code of an address generation step of generating an address for reading data from a memory holding the input image data, and a code of a memory reading step of reading image data from the memory according to the address generated in the address generation step. A code of a bit image generating step of generating a plurality of types of bit image data based on data read from the memory; a code of a bit image input step of inputting the plurality of types of bit image data to a temporary memory; Bit image from temporary memory A code of a bit image output step of outputting data; and a code of a head driving step of driving a recording head based on the bit image output from the temporary memory, wherein the bit image input step and the bit image output step , Wherein the order of input and output to the temporary memory is controlled so that the plurality of types of bit image data are output in an order different from the order of generation.