JPH08142409A - Printer - Google Patents

Abstract

PURPOSE: To shorten a printing time by increasing processing speed when the image data in an image memory is transmitted to a printing head. CONSTITUTION: Ink is emitted from a plurality of the nozzles arranged on a printing head while the printing head is reciprocally moved in a main scanning direction on the basis of the image data VD stored in an SRAM 12 to perform printing on recording paper at every several lines. When the image data VD is received at every one line, a memory control part 13 stores respective line data in the SRAM 12 in the main scanning direction at every one pixel corresponding to one address. Further, the memory control part 13 stores the predetermined pixel data of a plurality of line data in a sub-scanning direction corresponding to one address when the image data VD is stored in the SRAM 12. An address control part 22 alters the stored address of the pixel data in the SRAM 12 corresponding to nozzle arrangement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial printing type printing apparatus such as an inkjet printer which prints several lines on a recording paper while reciprocating the printing head in the main scanning direction.

[0002]

2. Description of the Related Art Generally, in a printing apparatus of this type, for example, an inkjet printer, a print head is provided so as to be capable of reciprocating in a main scanning direction, and a plurality of print elements as print elements are provided on a surface of the head facing a recording paper. Nozzles are arranged in series in the sub-scanning direction. Then, while the print head is reciprocally moved in the main scanning direction, ink is ejected from each nozzle to perform printing on several lines on the recording paper.

By the way, for example, in a facsimile machine, image data is received line by line. For this reason,
When the above inkjet printer is applied as a printing device in a facsimile machine, first, at least the number of line data corresponding to the number of nozzles is stored in the image memory. In this state, the line data is transferred to the print head while sequentially reading out one pixel for each pixel from the image memory, and the same head prints several lines at a time.

Conventionally, when image data is received line by line, as shown in FIG. 12 (a), each line data is set to 1 pixel by 8 pixels in the main scanning direction.
It is stored in the image memory 35 in association with one address. Therefore, when printing the image data,
As shown in (b), line data of 8 pixels corresponding to a predetermined address in the main scanning direction is sequentially read from the image memory 35 in the sub scanning direction. Then, as indicated by the broken line box in the figure, it is necessary to perform a process of sequentially transferring only one predetermined pixel data from the read eight pixel data to the print head.

[0005]

Therefore, conventionally, the process of transferring the image data stored in the image memory 35 to the print head becomes complicated, the processing speed becomes slow, and the time required for printing is reduced. There was a problem that it became long.

The present invention has been made to solve the above problems, and an object thereof is to shorten the printing time by increasing the processing speed when transferring the image data in the image memory to the print head. An object of the present invention is to provide a printing device that can be realized.

[0007]

In order to achieve the above object, in the invention of claim 1, the image data transferred line by line is associated with one address for each pixel in the main scanning direction. And a control means for controlling so that the image is stored in the image memory.

According to a second aspect of the present invention, the control means controls, when the image data is stored in the image memory, to store predetermined pixel data of a plurality of line data in the sub-scanning direction in association with one address. To do.

According to a third aspect of the present invention, the control means includes a changing means for changing the storage address of each pixel data in the image memory according to the arrangement configuration of the printing elements.

[0010]

Therefore, according to the invention of claim 1, when the image data is transferred line by line, each line data is
Each pixel in the main scanning direction is stored in the image memory in correspondence with one address. Therefore, when the image data in the image memory is transferred to the print head, it is possible to read each line data from the memory for each pixel as it is without any special processing and transfer it to the print head. The processing speed becomes faster.

According to the second aspect of the invention, the predetermined pixel data of the plurality of line data in the image memory can be read at a time in the sub-scanning direction and transferred efficiently to the print head, so that the processing speed is increased. Get faster.

According to the third aspect of the invention, even when the print elements are arranged obliquely with respect to the sub-scanning direction or in a staggered arrangement, the image is formed regardless of the arrangement of the print elements. It is possible to always read the image data from the memory by a fixed method. As a result, it is not necessary to change the method of reading the image data from the image memory according to the arrangement configuration of the print elements, and the process of transferring the image data in the image memory to the print head is simplified.

[0013]

Embodiment An embodiment in which the printing apparatus of the present invention is embodied in a facsimile machine equipped with an inkjet printer will be described below with reference to the drawings. As shown in FIG. 2, a print head 1 is supported along a guide rod 2 so as to be capable of reciprocating in the main scanning direction of a recording paper (not shown), and a plurality of print elements (64 in this embodiment) are provided on the front surface thereof. The nozzles 3 are arranged in series at predetermined intervals so that they form an angle of 45 degrees with the sub-scanning direction. Then, while the print head 1 is reciprocally moved within a predetermined area facing the recording paper, ink is ejected from each nozzle 3 onto the recording paper, and a line corresponding to the number of nozzles 3 is formed on the recording paper in a dot matrix. Printing is done every few minutes.

By arranging the nozzles 3 so as to be inclined with respect to the sub-scanning direction, the distance between the adjacent nozzles 3 in the sub-scanning direction is greater than that when the nozzles 3 are arranged along the sub-scanning direction. Can be narrowed. Therefore, the recording linear density in the sub-scanning direction is improved and a high-resolution printed image can be obtained. Further, in this case, since it is not necessary to form the actual space between the adjacent nozzles 3 to be small, the device for ejecting the ink from each nozzle 3 can be easily formed in a relatively wide range.

Next, the circuit configuration of this facsimile apparatus will be described. As shown in FIG. 1, a CPU (Central Processing Unit) 6 has a ROM (Read Only Memory) 7 storing a program for controlling the operation of the entire apparatus, and a temporary storage of various information. A RAM (random access memory) 8 is connected via a bus bs. The NCU 9 controls the connection with the telephone line. Modem 1
0 modulates and demodulates transmitted / received data.

The reading unit 11 reads an image on a document. SRAM (static RAM) 12 as image memory
Is for temporarily storing the received image data and the image data read by the reading unit 11. This SR
The AM 12 has a storage capacity capable of storing the number of lines corresponding to the number of the nozzles 3 of the print head 1, that is, the image data of one scan of the print head 1.

The memory control unit 13 as a control means is
Image data corresponding to a predetermined address is written in the RAM 12, or image data corresponding to a predetermined address is read from the SRAM 12. Although not particularly shown, a pair of SRAMs 12 are actually provided in the present embodiment, and the memory control unit 13 has a pair of SRAs.
Image data is written to and read from each SRAM 12 while switching the connection with the M12. The image processing unit 14 encodes and decodes image data, and serially transfers the decoded image data to the line data memory control unit 13. The oscillator 15 generates a reference clock signal SCLK having a predetermined frequency (8 MHz in this embodiment).

The head motor 16 is a stepping motor, and reciprocates the print head 1 in the main scanning direction via a moving mechanism (not shown). The paper feed motor 17 is also a stepping motor, and conveys the recording paper in the sub-scanning direction via a feed roller or the like (not shown) each time printing of one scan by the print head 1 is completed. A recording unit 18 is configured by the print head 1, the motor 16 for the head, the paper feed motor 17, and the like.

Next, the structure of the memory controller 13 will be described in detail. As shown in FIG. 3, the data control unit 2
Reference numeral 1 is for controlling input / output of image data to / from the SRAM 12. The read signal DR and the write signal WR from the CPU 6 and the reference clock signal SCLK from the oscillator 15 are input to the data control unit 21 via the bus bs. Further, the data control unit 21 is supplied with the video clock signal VCLK of a predetermined frequency (2 MHz in this embodiment) from the image processing unit 14. Then, based on the input of these signals, the data control unit 21 outputs the first read signal OE1 and the write signal WE to the SRAM 12, and outputs the second read signal OE2 and the latch signal LT to the register 24 described later. . The second read signal OE2 is also output to the address control unit 22, which will be described later. The data control unit 21 outputs the chip enable signal CE to the SRAM 12 based on a command from the CPU 6. Then, by switching the chip enable signal CE between H and L, the pair of SRAMs 12 are selectively connected to the data control unit 21.

The address control unit 22 as a changing means is
When inputting / outputting image data to / from the SRAM 12, the SRA
It is for designating a write address and a read address of image data in M12. In addition to the reference clock signal SCLK and the video clock signal VCLK, the address control unit 22 has a vertical synchronization signal VSYNC and a horizontal synchronization signal HSYNC from the image processing unit 14.
When C is input, the second data from the data control unit 21
Read signal OE2 is input. The vertical synchronization signal VSYNC is output by the image processing unit 14 at the start of transfer of image data for one scan of the print head 1, and the horizontal synchronization signal HSYNC is output by the processing unit 14 of line data. It is output at the start. Then, the address controller 22 receives the SRAM signals based on the input of these signals.
12-bit X-axis address signals A3 to A14 corresponding to the main scanning direction are output, and 3-bit Y-axis address signals A0 to A2 corresponding to the sub-scanning direction.
Is output.

That is, as shown in FIG. 6, the SR of this embodiment is
The AM 12 includes memory cells 12a having a bit number slightly larger than 2048 bits so as to store at least read image data of a B4 size document in the main scanning direction (X-axis direction). Further, the SRAM 12 can store image data for the number of lines corresponding to the number of nozzles 3 of the print head 1 in the sub-scanning direction (Y-axis direction).
The memory cell 12a for 64 bits is provided, and eight memory cells 12a form one block. And X
In the axial direction, the memory cell 12a having one address
And the address is assigned to each block in the Y-axis direction.

Therefore, in the SRAM 12, the address signals A0 to A2 and A3 from the address control section 22 are sent.
8 memory cells 12a having an address corresponding to the address signal are designated based on the input from A14 to A14. Then, in this state, the first read signal OE1 or the write signal WE from the data control unit 21 is input to the SRAM 12, so that the eight bits corresponding to the eight addressed memory cells 12a are input. Image data (8-bit pixel data) D0 to D7 is read or written.

Further, the address control section 22 is responsive to the input of the vertical synchronizing signal VSYNC to prepare for the start of the input of the image data for one scan of the print head 1 in response to the address signal A.
0 to A2 and A3 to A14 are set to initial values. Further, the address control unit 22 sets the X-axis address signals A3 to A14 to initial values and inputs the horizontal synchronization signal HSYNC based on the input of the horizontal synchronization signal HSYNC so as to prepare for the start of input of line data. Each time, one is counted. This counting is performed from "1 to 8", and the address control unit 22 notifies the selector 23 described later of the count value, and when the count value returns to "1", the Y-axis address signal A0 Increment A2. Further, the address control unit 22 increments the X-axis address signals A3 to A14 based on the input of the second read signal OE2.

As shown in FIG. 3, the selector 23 has an S
The 8-bit pixel data D0 to D7 output in parallel from the RAM 12 are stored. Also, the selector 23 has
The image data VD is input from the image processing unit 14 pixel by pixel in synchronization with the video clock signal VCLK. Then, the selector 23 determines the 8-bit pixel data D0 to D based on the count value notified from the address control unit 22.
The predetermined 1-bit pixel data in 7 is replaced with the image data VD for one pixel. For example, as shown in FIG. 6, if the count value notified from the address control unit 22 is “6”, the selector 23 causes the 8-bit pixel data D0 to D7.
The sixth pixel data in the middle is replaced with the image data VD for one pixel.

The register 24 latches the 8-bit pixel data D0 to D7 stored in the selector 23 on the basis of the latch signal LT from the data control section 21 and also outputs a second read signal from the control section 21. Based on OE2, the latched 8-bit pixel data D0 to D7
To the SRAM 12 in parallel. The three-state buffer 25 allows the 8-bit pixel data D0 to D7 output in parallel from the SRAM 12 to be output on the bus bs based on the command signal from the data control unit 21,
Cut off.

Next, the structure of the data control unit 21 will be described in detail. As shown in FIG. 4, the first flip-flop 26 is synchronized with the rising edge of the reference clock signal SCLK from the oscillator 15 which is input to the C terminal.
H / L of video clock signal VCLK input to the terminal
Hold the state of. And the first flip-flop 2
6 outputs the held state of the video clock signal VCLK as an output signal SG1 from the Q terminal, and outputs a signal having a phase opposite to that of the output signal SG1.
Output from the bar Q terminal as G2.

The second flip-flop 27 synchronizes with the rising edge of the reference clock signal SCLK input to the C terminal and outputs H / H of the output signal SG1 from the first flip-flop 26 input to the D terminal. Hold the L state. Then, the second flip-flop 27 outputs the held state of the output signal SG1 from the Q terminal as the output signal SG3, and outputs the signal in the opposite phase to the output signal SG3 as the output signal SG4 to the Q terminal. Output more. That is, the first and second flip-flops 26,
Reference numeral 27 denotes a shift register, and the video clock signal VCLK held in the first flip-flop 26.
The H / L state is held in the second flip-flop 27 in the subsequent stage with a delay of one cycle of the reference clock signal SCLK.

The output signal SG2 from the first flip-flop 26 and the output signal SG3 from the second flip-flop 27 are input to the first NAND circuit 28. Then, the first NAND circuit 28 outputs, as the latch signal LT, a signal which becomes L level only when the two input output signals SG2 and SG3 are both at H level. The output signal SG1 from the first flip-flop 26 and the output signal SG4 from the second flip-flop 27 are input to the second NAND circuit 29. Then, the second NAND circuit 29 receives the input 2
A signal that becomes L level only when the two output signals SG1 and SG4 are both at H level is output as the second read signal OE2.

The first OR circuit 30 has the first NA
The latch signal LT from the ND circuit 28 and the read signal RD from the CPU 6 are input. Then, the first OR circuit 30 outputs a signal which becomes H level when at least one of the two input signals LT and RD is H level, as the first read signal OE1.
The output signal SG3 from the second flip-flop 27 and the write signal WR from the CPU 6 are input to the second OR circuit 31. Then, the second OR circuit 31
Outputs, as the write signal WE, a signal that becomes H level when at least one of the two input signals SG3 and WR is H level.

Although not shown in FIG. 4, the data control unit 21 switches H / L of the chip enable signal CE based on a command from the CPU 6 as described above, and also the three-state buffer 25. The command signal is output to.

Next, the operation of the facsimile apparatus configured as described above will be described focusing on the time chart of FIG. When image data reception is started via the NCU 9 and the modem 10, the received image data is sequentially transferred to the image processing unit 14 for each line and subjected to processing such as decoding. Then, as shown in FIG. 5, the image data VD is
In synchronization with the fall of the video clock signal VCLK to the L level, the selector 2 of the memory control unit 13 pixel by pixel.
Input to 3.

On the other hand, when the video clock signal VCLK falls to the L level, the data control unit 2 of the memory control unit 13 is synchronized with the rising of the reference clock signal SCLK.
The first flip-flop 26 of 1 holds the L level state of the video clock signal VCLK. Therefore, at time t1 shown in FIG. 5, the output signal SG1 from the Q terminal of the first flip-flop 26 is lowered to the L level and the output signal S from the Q terminal at the bar is output.
G2 is raised to H level. Further, the state of the video clock signal VCLK held in the first flip-flop 26 is held in the second flip-flop 27 with a delay of one cycle of the reference clock signal SCLK. Therefore, at the time t2, the output signal SG3 from the Q terminal of the second flip-flop 27 falls to the L level, and the output signal SG4 from the bar Q terminal rises to the H level.

The output signal SG2 from the Q terminal of the first flip-flop 26 and the output signal SG3 from the Q terminal of the second flip-flop 27 are the first NA.
It is input to the ND circuit 28. Therefore, the latch signal LT output from the first NAND circuit 28 becomes L level from the time when the output signal SG2 rises to H level at time t1 to the time when the output signal SG3 falls to L level at time t2. Get down. The latch signal LT is input to one input terminal of the first OR circuit 30, and the CPU 6 is input to the other input terminal of the OR circuit 30.
The read signal DR from is input. When receiving the image data, the CPU 6 outputs the read signal D to be output.
Both R and the write signal WR are held at the L level. Therefore, in the first read signal OE1 output from the first OR circuit 30, the H / L state of the latch signal LT appears as it is. Then, at time t1, the first read signal OE1 is set to L together with the latch signal LT.
When falling to the level, 8-bit pixel data D0 to D7 are read out from the SRAM 12 and input to the selector 23.

At this time, in the SRAM 12,
Address signals A0 to A2, A from the address controller 22
Based on the inputs 3 to A14, eight memory cells 12a having an address corresponding to the address signal are designated. Therefore, in this state, the first read signal OE
1 falling to the L level causes eight addressed memory cells 12a, as shown in FIG. 6, for example.
From, the 8-bit pixel data D0 to D7 are read out and input to the selector 23.

Before the received image data is stored in the SRAM 12, the white pixel data is stored in all the memory cells 12a. Further, at this time, the three-state buffer 25 shuts off the pixel data D0 to D7 from the SRAM 12 so as not to be output onto the bus bs based on the command signal from the data control unit 21.

Then, in the selector 23, the count notified from the address control unit 22 as shown in FIG. 6, for example, between the time t1 and the time t2 when the first read signal OE1 falls to the L level. Based on the value
Predetermined 1-bit pixel data in the 8-bit pixel data D0 to D7 is replaced with the image data VD for one pixel input from the image processing unit 14. Then, at time t2, when the latch signal LT rises to the H level, the 8-bit pixel data D0 to D7 in the selector 23 are latched in the register 24.

The output signal SG3 from the second flip-flop 27 is input to one input terminal of the second OR circuit 31 and C is input to the other input terminal of the OR circuit 31.
The write signal WR from PU6 is input. At this time, since the write signal WR is held at the L level, the write signal W output from the second OR circuit 31
In E, the H / L state of the output signal SG3 appears as it is. Then, at time t2, the write signal WE
Goes to L level with the output signal SG3, S
The RAM 12 is in a state where image data can be written to the designated address.

After that, the video clock signal VCLK goes high.
When rising to the level, the first flip-flop 26 holds the H level state of the video clock signal VCLK in synchronization with the rising of the reference clock signal SCLK. Therefore, at time t3, the output signal SG1 from the Q terminal of the first flip-flop 26 rises to the H level, and the output signal SG2 from the Q terminal of the bar flips to the L level. Also, at this time t3
From the time t delayed by one cycle of the reference clock signal SCLK from
At timing 4, the output signal SG3 from the Q terminal of the second flip-flop 27 rises to the H level, and the output signal SG4 from the bar Q terminal falls to the L level.

Then, the Q of the first flip-flop 26 is
The output signal SG1 from the terminal and the second flip-flop 2
The output signal SG4 from the bar Q terminal of 7 is the second NA
It is input to the ND circuit 29. Therefore, the second read signal OE2 output from the second NAND circuit 29 is between the time when the output signal SG1 rises to the H level at time t3 and the time when the output signal SG4 falls to the L level at time t4. Fall to L level. Then, at time t3, the second read signal OE
When 2 falls to the L level, the 8-bit pixel data D0 latched in the register 24 as shown in FIG.
~ D7 is output to the SRAM 12 and written to the eight addressed memory cells 12a.

Then, at the time t4, when the write signal WE rises to the H level together with the output signal SG3 and the second read signal OE2 rises to the H level, the writing of the image data to the SRAM 12 is completed. In other words, the image data VD for one pixel transferred from the image processing unit 14 is SR
It is stored in AM12. Further, the address controller 22 increments the X-axis address signals A3 to A14 based on the rising edge of the second read signal OE2. As a result, the designated address in the SRAM 12 is shifted by 1 bit in the main scanning direction.

In this way, the image data VD transferred line by line from the image processing unit 14 corresponds to one address for each pixel in the main scanning direction and corresponds to the SRAM 1
Sequentially stored in 2. When the transfer of one line is completed, the transfer to the next line is started. At this time,
By the horizontal synchronization signal HSYNC from the image processing unit 14,
The address control unit 22 counts, and the count value is notified to the selector 23. When the count value returns from "8" to "1", the Y-axis address signals A0 to A2 are also incremented. Then, for the next line data as well,
The data is sequentially stored in the SRAM 12 in correspondence with one address for each pixel in the main scanning direction.

As described above, the SRAM 12 stores the number of line data corresponding to the number of nozzles 3, that is, 64 line data. In this embodiment, the nozzles 3 are arranged in series on the print head 1 so as to form an angle of 45 degrees with the sub-scanning direction. Then, in the present embodiment, as shown in FIG. 7, each pixel data of the received image data is stored in the SRAM 12 in a state shifted in the main scanning direction according to the arrangement configuration of the nozzles 3. Note that, in FIG. 7, the memory cells 12a in the SRAM 12 are depicted with a smaller number than the actual number in both the main scanning direction and the sub scanning direction. Further, in FIG. 7, the SRAM 12
The character "M" is stored therein as image data.

As shown in the figure, when the image data is transferred line by line to the SRAM 12, the line data of the first line is 1 in the main scanning direction of the SRAM 12.
One pixel is stored from the second address. The line data of the second line is stored pixel by pixel from the second address of the SRAM 12 in the main scanning direction. In this way, the line data sequentially input to the SRAM 12 is stored in a state of being shifted by one address in the main scanning direction.

Then, in this state, the printing operation based on the image data in the SRAM 12 is started. That is, first, in response to a command signal from the data control unit 21, the three-state buffer 25 is switched to a state in which data output is permitted. In this state, the read address of the image data in the SRAM 12 is designated by the address signals A0 to A2 and A3 to A14 from the address control unit 22,
Based on the first read signal OE1 from the data control unit 21, the 8-bit pixel data D0 to D from the SRAM 12
7 is sequentially output to the bus bs via the three-state buffer 25. Then, the pixel data D0 to D7 are sequentially input to the print head 1 via the bus bs.

As shown in FIG. 6, the address control unit 2
2 sets the Y-axis address signals A0 to A2 to "000" to "1".
Every time it is incremented to 11 ", the X-axis address signals A3 to A14 are incremented. That is, SR
The image data in the AM 12 is sequentially read in units of 8 pixels in the sub-scanning direction and transferred to the print head 1 in parallel, and in the main scanning direction every time the reading of 64 pixels in the sub-scanning direction is completed. The designated address is shifted by one address. Therefore, 6 of the print head 1
The 64 line data in the SRAM 12 are transferred to each of the four nozzles 3 by one pixel. As a result, as shown in FIG. 8, while the print head 1 is moved in the main scanning direction within a predetermined area facing the recording paper P, ink is ejected from each nozzle 3 onto the recording paper P based on the input image data. Then, printing for several lines is performed.

At this time, as shown in the figure, since the nozzles 3 are arranged so as to be inclined, when the print head 1 is moved to the right in the figure, the lower nozzles 3 advance later. come. However, as described above, since each line data in the SRAM 12 is stored in a state of being shifted by one address in the main scanning direction according to the arrangement configuration of the nozzles 3, the lower nozzles 3 are delayed. Ink ejection is started. As a result, as shown in FIG. 8, even when the arrangement angle of the nozzles 3 is inclined at 45 degrees, the obtained print image is in a normal state without being inclined.

As described above, in the present embodiment, even if the image data is received line by line, each line data corresponds to one address for each pixel in the main scanning direction.
It is stored in the RAM 12. Therefore, when the image data in the SRAM 12 is transferred to the print head 1, the SRAM
It is possible to read each line data from 12 as it is for each pixel and transfer it to the print head 1 without any special processing. Therefore, the processing speed when transferring the image data in the SRAM 12 to the print head 1 can be increased, and the printing time can be shortened.

Further, in the present embodiment, when the image data is stored in the SRAM 12, predetermined pixel data of eight line data in the sub-scanning direction is stored corresponding to one address. Therefore, the predetermined pixel data of the line data for eight lines in the SRAM 12 can be read at once in the sub-scanning direction and transferred to the print head 1 in parallel. Therefore, the image data can be efficiently transferred to the print head 1, and the image data transfer processing speed can be further increased.

In the print head 1 described above, the nozzles 3 are arranged in series so as to form an angle of 45 degrees with respect to the sub-scanning direction, but as shown in FIG. 9, the nozzles 3 are arranged in a staggered pattern. The diagonally arranged print head 1 may be used. When the nozzles 3 are arranged in this way,
Each pixel data of the received image data is stored in the SRAM 12 in a state as shown in FIG. 10 according to the array configuration. Incidentally, also in FIG. 10, the SRAM 12
The character "M" is stored therein as image data.

As shown in the figure, when the image data is transferred line by line to the SRAM 12, the line data of the first line is 1 in the main scanning direction of the SRAM 12.
One pixel is stored from the second address. The line data of the second line is stored pixel by pixel from the third address of the SRAM 12 in the main scanning direction. Furthermore, regarding the line data of the third line,
One pixel is stored from the second address of the SRAM 12 in the main scanning direction. In this way, the SRAM 12
The line data sequentially input to is stored in a state in which the line data is shifted in a diagonal zigzag pattern in the main scanning direction. Therefore, when the printing operation based on the image data in the SRAM 12 is performed in this state, the printed image obtained on the recording paper P is in a normal state without being shifted in a zigzag pattern as shown in FIG.

As described above, in the present embodiment, the address control unit 22 changes the SRAM according to the arrangement configuration of the nozzles 3.
The storage address of each pixel data in 12 is changed. Therefore, even when the nozzles 3 are arranged obliquely with respect to the sub-scanning direction or in a staggered arrangement as described above, the image data is always read from the SRAM 12 regardless of the arrangement of the nozzles 3. It is possible to read by a fixed method. As a result, it is not necessary to change the method of reading the image data from the SRAM 12 according to the arrangement configuration of the nozzles 3, and the SRAM
The process of transferring the image data in 12 to the print head 1 is simplified. Therefore, in the present embodiment, the transfer process of the image data to the print head 1 can always be performed easily and quickly regardless of the arrangement configuration of the nozzles 3.

The present invention is not limited to the above embodiment, but may be embodied by changing the configuration of each part as follows. (1) The nozzle 3 may be arranged in the sub-scanning direction, or the arrangement of the nozzles 3 may be changed to an arrangement other than the above. Also in this case, the address control unit 22 may change the storage address of each pixel data in the SRAM 12 according to the array configuration.

(2) Changing the number of nozzles 3 and changing the storage capacity of the SRAM 12 accordingly. (3) The present invention is embodied in a general inkjet printer other than a facsimile machine. Further, in addition to the inkjet type printing apparatus, the present invention should be embodied in a printing apparatus that performs printing by a thermal head having a plurality of heating elements as printing elements.

The technical ideas other than the claims that can be understood from the above-described embodiments will be described below. (1) The printing device according to claim 3, wherein the printing elements are arranged at an angle of 45 degrees with respect to the sub-scanning direction.

By doing so, the interval in the sub-scanning direction between the adjacent printing elements becomes narrower, so that a high-resolution printed image can be obtained. Moreover, a plurality of printing elements can be easily formed in a relatively wide range.

[0056]

As described above in detail, according to the first aspect of the invention, the processing speed when transferring the image data in the image memory to the print head can be increased, and the printing time can be shortened. Can be planned.

According to the second aspect of the present invention, the predetermined pixel data of the plurality of line data in the image memory can be read at one time in the sub-scanning direction and can be efficiently transferred to the print head. The transfer processing speed becomes faster.

According to the third aspect of the invention, even if the printing elements are arranged obliquely with respect to the sub-scanning direction or in a staggered arrangement, printing is performed regardless of the arrangement of the printing elements. The transfer process of image data to the device can always be performed easily and quickly.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a partial perspective view showing a print head in which nozzles are arranged obliquely.

FIG. 3 is a circuit configuration diagram showing details of a memory control unit.

FIG. 4 is a circuit configuration diagram showing details of a data control unit.

FIG. 5 is a time chart showing the operation of the memory control unit.

FIG. 6 is an explanatory diagram showing a configuration of SRAM.

FIG. 7 is an explanatory diagram showing a state in which image data is stored in SRAM.

FIG. 8 is an explanatory diagram showing a printing state on recording paper.

FIG. 9 is a front view showing a print head in which nozzles are arranged in a diagonal zigzag pattern.

FIG. 10 is an explanatory diagram showing a state in which image data is stored in SRAM.

FIG. 11 is an explanatory diagram showing a printing state on a recording sheet.

FIG. 12 is an explanatory diagram showing a storage state of image data in a conventional image memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Print head, 3 ... Nozzle, 12 ... SRAM as image memory, 13 ... Memory control unit as control means, 2
DESCRIPTION OF SYMBOLS 1 ... Data control part, 22 ... Address control part as a change means, 23 ... Selector, 24 ... Register.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H04N 1/034

Claims (3)

[Claims] 1. Based on image data stored in an image memory, while reciprocating the print head in the main scanning direction, a plurality of printing elements arranged on the head print on a recording paper for several lines. The printing device is provided with a control means for controlling the image data transferred line by line to be stored in the image memory in correspondence with one address pixel by pixel in the main scanning direction. 2. The printing device, wherein the control means controls, when storing image data in an image memory, to store predetermined pixel data of a plurality of line data in the sub-scanning direction in association with one address. 3. The printing apparatus according to claim 1, wherein the control unit includes a changing unit that changes a storage address of each pixel data in the image memory according to the arrangement configuration of the printing elements.