JPS6258910B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an inkjet recording device, and particularly to an inkjet recording device that stores and reads out an image signal for one dot line (hereinafter referred to as "one line") in one memory. The present invention relates to an inkjet recording device that is inexpensive and suitable for integration.

(Prior Art) Generally, when a deflection type inkjet storage device is used in a copying machine or the like, an image of a document is read by a line scanner and sent as a one-line serial signal to a recording device. Therefore, it is necessary to convert the one-line serial signal into a data arrangement according to the head configuration of the recording apparatus, and then supply the signal to the head for printing. For example, one line of serial signal read by a line scanner
D ₁ , D ₂ , ..., D ₃₆₀₀ are sent to the recording device,
As shown in Fig. 5, 60 (generally m) ink jet heads H ₁ , H ₂ , ..., H ₆₀ each having 60 stages (generally m stages) of deflection are used. hand,
When recording as a printed dot line consisting of 3600 dots (60 x 60) on a 210 mm screen, inkjet head _H1 has _D1 to _D60 , and _H2 has _D61 to _D120.
,..., H ₆₀ takes charge of D ₃₅₄₁ to _{D 3600} , respectively, and prints in a line. In this case, the dots of the same deflection stage are simultaneously printed by 60 inkjet heads. That is, first the groups (D ₁ , D ₆₁ ,...D ₃₅₄₁ ) are printed simultaneously, and when the next deflection position is reached, the group (D ₂ , D ₆₂ ,...D ₃₅₄₂ ) is printed, and so on. 60 pieces are printed at each same deflection position. In order to convert a serial input signal, which generally consists of m×m dots, into parallel signals in groups separated by m dots, conventionally, m shift registers each having m stages (60 stages) are used. (60 pieces) in series, one line of image signal is stored in the shift register at once, data is read out in parallel from each output of every m (60 pieces) shift register corresponding to each head, and each (60 heads) for printing.

(Problems with the Prior Art) However, such a conventional method requires a cycle for storing the image signal in the shift register and a cycle for reading and recording the image signal from the shift register. That is, since printing is not performed while the image signal for one line is stored in the shift register, there is a drawback that the printing speed is reduced. Furthermore, since the number of outputs is large, the number of pins on the package increases, which is a significant disadvantage when attempting to integrate the device. In order to improve the printing speed, the shift register was set to 2.
Although it is conceivable to store and read data alternately, this would not only make the device complicated and expensive, but also be disadvantageous for integration.

The present invention enables printing at the same speed as when using two sets of shift registers with one memory for one line, and can be realized by using one ordinary package of RAM. The purpose is to provide a storage device that is advantageous for integration and is inexpensive.

(Means for Solving the Problems) The present invention arranges m heads with m deflection stages at regular intervals in the dot arrangement direction of one dot line, and inserts recording paper in a direction perpendicular to the dot arrangement direction. An inkjet recording device that sends images relatively includes a storage means having a storage capacity for storing an image signal for at least one dot line, each storage cycle consisting of a readout period and a subsequent writing period, and a storage means which also has rows in the column direction of the storage means. Addressing means that can sequentially address in the direction as well, and the direction of addressing can be switched between the column direction and the row direction for each dot line; control means for reading one bit of an already stored image signal during a writing period and writing one bit of a new one dot line image signal during the write period; and means for supplying the read image signal to m heads. It is characterized by having

(Function) According to the present invention, each memory cycle consists of a read cycle and a subsequent write cycle, and the storage means is sequentially addressed using an addressing means to write and read serial image signals for one dot line. I do. At this time, in the present invention, the addressing direction of the storage means is alternately switched between the vertical direction and the horizontal direction for each dot line. When each dot of the image signal a of one dot line is sequentially read out in the read period of each memory cycle by sequentially addressing in the row direction of the storage means by the addressing means, the rows of the storage means are sequentially read out in the read period of each memory cycle. The image signal b of the next one-dot line is sequentially addressed in the direction
Write each dot. Next, in reading out the image signal b of one dot line written in this way, the addressing means sequentially addresses the memory means in the column direction, and each dot of the image signal b of the one dot line is read out in each memory cycle. Reading is performed sequentially during the period, and during the writing period of the same memory cycle, the addressing means sequentially addresses the storage means in the column direction to write each dot of the image signal c of the next one dot line.

In this way, by alternating the directions of read and write addressing for each dot line, it is possible to read signals from one line and write signals from the next line at the same time. The storage means can be made smaller and faster, and the printing speed can be increased.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

First, the principle of the present invention is explained in 60 steps of 60 deflections (m=
An example in which the number of dots per line by the inkjet head (60) is 3600 dots (m×m) will be explained. The serial image signal a (a ₁ , a ₂ , a ₃ , ...a ₃₆₀₀ ) of 3600 dots in one line is sequentially stored vertically in an area of 60 rows and 60 columns in the memory, as shown in Figure 4 a. written. The image signals written in this way are transferred horizontally one column at a time, as shown in Figure 4b.
A ₁ , a ₆₁ , a ₁₂₁ , . . . are read out sequentially, and 60 read signals for each column are supplied in parallel to 60 ink jet heads for printing.

In the read operation shown in FIG. 4b, as is well known in memory technology, each memory cycle has a read half cycle followed by a write half cycle, so the write half cycle is used to input the next line. Image signal b (b ₁ , b ₂ , b ₃ ,
..., b ₃₆₀₀ ).

When this input image signal b is then sequentially read out in the vertical direction as b ₁ , b ₆₁ , b ₁₂₁ . . . as shown in FIG. 4c, printing signals from 60 heads are sequentially obtained. In this readout, as in the case of FIG. 4b, the inputted image signal c(c ₁ , c 2 , c ₂ , c ₃ , …, c ₃₆₀₀ ) are written vertically.

In this way, by alternating vertical and horizontal accesses, it is possible to read the storage signal of one line and write the next line at the same time (that is, in the first and second half of the same memory cycle). This makes it possible to increase the printing speed.

FIG. 1 is an overall configuration diagram of an embodiment of the head drive system of an inkjet recording apparatus according to the present invention, in which 1 is a 1.5MHz clock generator, 2 is a sexagesimal row address counter, and 3 is a sexagesimal column address. 4 is a memory unit using static RAM of 64 x 64 bits, 5 is a 60-stage shift register, 6 is a latch circuit, 7 is a 1/30 frequency divider circuit, and 8 is a 1/30 frequency divider.
The frequency divider circuit 9 is a head unit consisting of 60 heads each performing 60 stages of deflection.

FIG. 2 is a diagram showing the configuration of the memory unit 6 in FIG. 1, where 11 is a row address decoder that selects a row, 12 is a column address decoder that selects a column, 13 is a 64×64 bit memory array, and 14 is a row address decoder that selects a row. , 15 are gates, R ₀ to R ₅ are input lines of the row address decoder 11, and C ₀ to _{C 5} are input lines of the column address decoder 12.

Next, the operation of FIGS. 1 and 2 will be explained with reference to FIG. 4.

() Prior to printing, one line of image signals is stored in the memory unit 4 through the gate 14. At this time, the image signals are It will be remembered as follows.

That is, the 60 advance address counter 2 counts up the 1.5MHz clock of the clock generator 1, and the 60 base column address counter 3 counts up every 60th pulse (carry), as shown in FIG. When 60 pieces of data are stored in the memory array 13 vertically, they are stored sequentially in the next column, and by repeating this process, 60 pieces of data are stored vertically and 60 pieces of data are stored horizontally. are respectively stored as shown in FIG. 4a. That is, 60×60=3600 data are stored.

() After storing 3,600 dots of data in the memory unit 4, the next printing operation begins. The 60 pieces of data in each row are the signals that give the 60 stages of deflection for each head, and the data that gives the Nth stage of deflection for each head are stored in the Nth column. Therefore, in order to print from each head at the same time, reading is performed sequentially in the horizontal direction. That is, the hexadecimal column address counter 3 counts up the clock of the clock generator 1, and every time it counts 60, it calculates a carry.
60 progress address counter 2 counts up. As a result, reading In other words, the data for the first deflection printing of each of the 60 heads, the data for the second deflection printing of each head, and the 60th printing data of each head are read out (the (See Figure 4 b).

() The read signal is output through the gate 15, sent to the 60-stage shift register 5, converted from a serial signal to a parallel signal, and sent to the latch circuit 6. Latch circuit 6
converts the image signal every 60 bits of the serial signal
60 parallel outputs, this is head unit 9
, so that each deflection stage of each head is printed simultaneously. The head unit is a charge control deflection type ink jet head.

Writing, reading, and printing of image signals are performed in this way, and when controlling the reading address, the memory unit's R/W
A 1.5MHz clock is supplied to the (read/write) terminal, and as shown in Figure 3, the read operation is performed at the HIGH portion of the 1.5MHz clock.
Since the image signal is stored in the LOW portion, after reading the contents of the same address, the image signal of the next line is stored at the same address. In this manner, subsequent lines are stored sequentially across the memory array of FIG.

In () and (), since the next line was written at the same time as the next line was sequentially read in the horizontal direction, when printing the next line, the reading and writing were carried out in the vertical direction. This allows printing and memorization.

By repeating steps () and () above, it becomes possible to print the entire surface of the recording paper using one memory unit. The output of the shift register 5 is read into the latch circuit 6 at the rising edge of the 25KHz clock, which is obtained by dividing the excitation clock 50KHz by 1/2, and is synchronized with the generation of droplets. By setting the cycle to /2, a guard drop is generated. If a guard drop is not required, all droplets can be printed by doubling the frequency of the clock generator 1, dividing it by 1/60, and sending it as it is to the latch circuit 6 as an excitation clock.

In the above description, an example is shown in which a 64×64, ie, 4096-bit RAM is used, but it goes without saying that a 60×60, ie, 3,600-bit RAM may also be used. Further, although a copying machine has been described, a facsimile machine or the like may also be used, and the present invention is not limited to this.

(Effects of the Invention) As explained above, the present invention arranges m heads that perform m stages of deflection at regular intervals in the dot arrangement direction of one dot line, and records data in a direction perpendicular to the dot arrangement direction. In an inkjet recording device that relatively feeds paper, each memory cycle consists of a read cycle followed by a write cycle, and one line written by addressing sequentially in the row direction (column direction) of the memory. By addressing and reading the serial signal in the column direction (row direction), it is converted into a printing data array according to the head configuration. At this time, reading the signal of a certain dot line in the memory and writing the signal of the next dot line are performed by addressing in the same memory cycle, which eliminates the conventional method of using one shift register to store the image signal of one dot line. The printing speed can be improved compared to the apparatus described in 2007, which requires waiting until the reading of all the signals of a certain dot line is completed before writing the image signals of the next line. Furthermore, compared to conventional devices that improve printing speed by alternately using two shift registers, each with a storage capacity for the image signal of one dot line, even if the speed is the same, the memory capacity is lower. Since it only takes half the time and the configuration is simple, it is advantageous for integrating the memory and peripherals, and has the advantage of being inexpensive.

In addition, in the present invention, since the number of heads used and the number of deflection stages of each head are made equal, addressing in the row direction and column direction of the memory can be realized by the same addressing means, and the number of heads is equal. The structure is simpler than the structure in which m is different from the number n of deflection stages of each head (invention of Japanese Patent Application No. 16830/1983 filed on the same day by the present applicant).

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram of the head drive system of an inkjet recording apparatus according to the present invention, FIG. 2 is a configuration diagram of the memory unit in FIG. 1, and FIG. 3 is a time diagram showing the relationship between clock signals and read/write operations. 4 is a diagram showing the writing/reading order of the memory for explaining the principle of the present invention, and FIG. 5 is a diagram showing the relationship between the head and the printing dot line. 1... Clock generator, 2... 60 progress address counter, 3... Hexadecimal column address counter, 4...
...Memory unit, 5...Shift register, 6...
... Latch circuit, 7, 8 ... Frequency divider circuit, 9 ... Head unit, 11 ... Row address decoder, 12
...Column address decoder, 13...Memory array, 14, 15...Gate.

Claims (1)

[Claims] 1. m heads each having m deflection stages are arranged at regular intervals in the dot arrangement direction of one dot line,
An inkjet recording device that relatively sends recording paper in a direction perpendicular to the dot arrangement direction has a storage capacity to store an image signal for at least one dot line, and each storage cycle consists of a read period and a subsequent write period. means, an addressing means capable of sequentially addressing both the column and row directions of the storage means, and in which the direction of addressing is switched between the column and row directions for each dot line; , a control means for reading one bit of an already stored image signal during a read period of a storage cycle of each address of the storage means, and writing one bit of a new one dot line image signal during the write period; An inkjet recording device comprising: means for supplying ink to m heads. 2. The addressing means has an address counter for specifying a row and an address counter for specifying a column. In addressing in the column direction, the carry of the address counter for specifying a column is input to the address counter for specifying a row, and 2. The inkjet recording apparatus according to claim 1, wherein in directional addressing, the carry of an address counter for row designation is switched and connected so as to be input to the address counter for column designation.