JP2866103B2 - Image processing device and image recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention mainly reads out image data for each color from a memory for storing image data, and mainly uses a recording head for each color. The present invention relates to an image processing and recording apparatus for recording an image with a carriage mounted at predetermined intervals in a scanning direction.

[Related Art] For example, in a thermal transfer color printer, the operation of scanning the thermal head is repeated while changing the ink ribbon a required number of times. In such a configuration, since a plurality of colors (writing heads) are not driven at the same time, many attempts to increase the printing speed cannot be expected.

However, for example, in a carriage equipped with cyan, magenta, yellow, and black writing heads,
It is possible to record an image for one scan while writing simultaneously, that is, with one movement. In this case, since there is a physical interval between the write heads, a corresponding amount of delay processing is required when transmitting data of each color to the recording head.

It is to be noted that there is an interval between the heads inevitably due to the configuration. Moreover, at this head interval,
If the printer has a printing density of 400 dpi, a shift of 100 μm will cause a color shift of 1.5 pixels or more.

When recording a natural picture, this value is obviously a fatal trouble.

[Problems to be Solved by the Invention] Conventionally, RAMs have been used to correct such physical intervals.
To generate a time difference between data writing and data reading.

However, in this case, the following problem occurs.

Independent RAM must be provided for each color.

Since a large-capacity low-priced RAM has many byte units, a circuit becomes complicated to convert multi-color 1-bit serial data into byte data for each color.

These problems have resulted in an adverse effect of increasing the size and cost of the apparatus.

SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and has a simple configuration in which image data of a plurality of colors that are serially input in a predetermined order is immediately changed from an input state to a color-by-color that is configured by predetermined bits. It is an object of the present invention to provide an image processing apparatus which can convert data into parallel data and write data in a different area for each color in a memory.

Further, the second invention records an image based on the image data for each color stored as described above, thereby simplifying the device configuration and speeding up the image development, resulting in an image. It is an object of the present invention to provide an image recording apparatus that speeds up data input to recording.

[Means for Solving the Problems] To solve the problems, for example, an image processing apparatus of the present invention has the following configuration. That is, a memory that stores image data in accordance with an input address, and holds image data of each color component that is input in a predetermined order for a predetermined number of bits, and stores the stored image data every bit number corresponding to the number of colors. And a shift register that outputs as parallel data for each color component by counting the input of a predetermined clock signal, and exchanges bits from the lower part of the count value corresponding to the number of recording colors with the upper bit group, Address generation means for outputting as an address indicating a write position of data to the memory; and write means for writing image data output as parallel data from the shift register at an address position generated by the address generation means. Prepare.

[Operation] In the image processing apparatus of the present invention, image data of each color component input in a predetermined order is output as parallel data for each color by the shift register, and the parallel data is generated by an address generated by the address generating means. Thus, the image data is stored in a storage area different for each color.

Embodiment An embodiment according to the present invention will be described below in detail with reference to the accompanying drawings. In the embodiment, a bubble jet printer will be described as an example.

FIG. 4 is a diagram showing the structure of a printing system for actually recording an image.

In the figure, reference numeral 19 denotes a carriage equipped with heads corresponding to each color of cyan (hereinafter, referred to as C), magenta (hereinafter, referred to as M), yellow (hereinafter, referred to as Y), and black (hereinafter, referred to as K). Is driven in the main scanning direction. 20
Is a wire fixed to the carriage 19 and stretched over pulleys 21 provided at both ends of its movement range. A motor 22 is connected to one of the pulleys and serves as a drive source for scanning and driving the carriage 19 in the S direction. twenty three
And 24 are first and second guard rails extending in the S direction for guiding the carriage 19. 25 regulates the recording surface of a recording medium such as recording paper or film,
A platen roller 26 for transporting the recording medium is a motor combined with the platen roller 25 for rotating the recording medium during transport.

Reference numeral 27 denotes a control signal transmission cable, one end of which is attached to the carriage 19, and the other end of which is connected to a control circuit (not shown). Then, image data, control signals and the like are transmitted through the cable 27. still,
This cable 27 is in the form of a flexible cable so as to follow the displacement of the carriage 19.

 The structure of the carriage 19 is shown in FIG.

As shown in the figure, the carriage 19 has bubble jet write heads of a total of four colors of C, M, Y and K incorporated therein. In the case of the embodiment has ink discharge ports of each head with 128 dots fraction, each interval L _1, L _2, L ₃ and Do connexion are arranged in a row. That is, it is shown that 128 dots can be printed for each of the four colors by one scanning movement in the S direction (scanning direction).

Now, when considering the printer with a printing density of 400 dpi, in the example of the print head to the 128 dots as one line, the printing width L ₀ is approximately 8 mm.

Next, the operation principle of the bubble jet printer will be described with reference to FIG.

In this state, the ink is exposed to the outside through a narrow passage. A heater is arranged on one surface of the passage, and when printing is to be performed, an electric current is supplied to the heater to cause overheating.
Then, as shown in state 3 to state 7, air bubbles (bubbles) are generated in the ink, and the ink is discharged to the outside by this force.

In the configuration of FIG. 6, such ink ejection ports are C, M, Y, K
This means that 128 heads are placed on each head.

An outline of processing relating to storage of image data of the present embodiment in the above-described printing system configuration will be described with reference to FIGS.

In the embodiment, it is assumed that the data for each color is transmitted serially in the order of C, M, Y, K, C, M. Further, the description will be omitted assuming that a known technique for actual driving of the recording head is used.

In FIG. 1, the serial image data 1 sent in the above-described manner is taken into the 29-bit shift register 3. Of the outputs of the 29-bit shift register 3, a total of 8 bits of Q ₀ , Q ₄ , Q ₈ , Q _12, ..., Q ₂₈ are used to write data to the SRAM 4 (in the embodiment, the capacity is 32 KB = 32 × 1024 bytes). Is output. That is, the in SRAM4 connexion is because those bits of 4 bits every other serial data is input to the data input terminal D ₀ to D _7, that data in a state of being separated for each color is input Become.

The counter value Q ₀ to Q ₁₄ of the 15 bits that are generated by the address counter 5, as shown, the Q ₀ is the SRAM address bits A _13, the Q ₁ is A _14, the Q ₁₄ from below Q ₂ It is connected to the address bits a ₁ to a _12.

Incidentally, although the description will be made before and after, the 29-bit shift register 3,
The SRAM 4 and 15-bit address counters 5 are operated in synchronization with the clock output from the timing generation circuit 6.

Hereinafter, the operation of each of these elements will be described based on the timing chart shown in FIG.

Image data is synchronized with the rising edge of the image clock.
The fact that M, Y, and K are input in this order has been described above. Now, assuming that the beginning of the image data is C ₀ , M ₀ , Y ₀ , K ₀ , the eighth pixel C ₇ ,
When M ₇ , Y ₇ , K ₇ , that is, data of 8 bits is input for each color, an address counter, a shift register, a WE
(Write enable) becomes active, and data is written to SRAM4.

At this time, the write data and its address for the SRAM are as shown at 10 to 18 in FIG.

More specifically, the outputs Q _{0 to} Q ₁₄ of the 15-bit address counter 5 at each timing when the WE signal becomes active are 0001 _H , 0002 _H , 0003 _H , 0004 _H (H indicates a hexadecimal number. ). However, the 15-bit address counter 5
Since the connection with the address of the SRAM has the relationship described above (shown in FIG. 1), the address for the SRAM 4 is 200
_{That is} , 0 _H , 4000 _H , 6000 _H , and 0001 _H.

That is, if the described memory space of SRAM 4, as shown in FIG. 3, the address of 32KB space "0000 _H to 1
FFF _H "region of K region, the address" 2000 _H ~3FFF _H "is C region, the address" 4000 _H ~5FFF _H "is M region and address," 6000 _H ~7FFF _H "becomes Y region.

In this manner, the data of the pixels of each color sent as serial data can be stored in the SRAM 4 in byte units. Incidentally, Tara memory summer full, for example when the Y data is written 7FFF _H address specification, the following will be going crowded newly written from address 6000 _H.

As described above, according to this embodiment, it is possible to convert multi-color serial data into byte data for each color with a simple configuration, and store byte data of each color while allocating it to one memory. Become. Therefore, the cost can be reduced without increasing the size of the device.

In this embodiment, the case where serial data is received, converted into byte data for each color, and allocated to one RAM for storage is described. However, the present invention is not limited to this.

For example, the input interface may be parallel instead of serial. Of course, in this case, it is necessary to receive parallel data for each color.

Further, in the present embodiment, the memory capacity allocated to each color is set to 8 Kbytes, but the present invention is not limited thereto. For example, when a RAM having a higher recording density due to the recording head and a larger capacity is required, for example, when using a RAM of about 64 Kbytes, the lower 2 bits of the address counter (16-bit output) are connected to the upper address of the RAM. Then, the memory capacity allocated to each color can be doubled to 16 Kbytes.

[Effects of the Invention] As described above, according to the present invention, with a simple configuration,
Image data of a plurality of colors that are serially input in a predetermined order are immediately converted from input state into parallel data for each color composed of predetermined bits, and stored in a memory in a different area for each color. It becomes possible to write parallel image data of each color.

According to the second aspect, by recording an image based on the image data for each color stored as described above, the apparatus configuration is simplified, and the image development is performed at a high speed. It is possible to increase the speed from input of image data to recording.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration from input of image data to writing into a memory in this embodiment, FIG. 2 is a timing chart for explaining the operation of each circuit configuration in FIG. 1, and FIG. FIG. 1 is a diagram showing a memory space of a RAM and a storage area for each color, FIG. 4 is a diagram showing a configuration of a printing system in an embodiment, FIG. 5 is a diagram for explaining the principle of a bubble jet printer, FIG. 6 is a diagram showing the configuration of the carriage of the embodiment. In the figure, 1 ... serial image data, 2 ... image clock, 3 ... 29-bit shift register, 4 ... SRAM, 5 ...
.., A 15-bit address counter, 6... A timing signal generation circuit, and 19... A carriage.

Claims (3)

(57) [Claims] A memory for storing image data in accordance with an input address; storing a predetermined number of bits of image data of each color component input in a predetermined order; and storing the stored image data in correspondence with the number of colors. A shift register that outputs as color data for each color component by outputting every bit number, counts the input of a predetermined clock signal, and sets the number of bits corresponding to the number of recording colors from the lower count to the upper bit group. Address generating means for exchanging and outputting as an address indicating a write position of data to the memory; and writing and writing image data output as parallel data from the shift register at an address position generated by the address generating means. An image processing apparatus comprising: 2. An image recording apparatus, wherein a plurality of recording heads corresponding to a plurality of different colors are mounted on a carriage at predetermined intervals, and an image is recorded by reading image data of each color from a memory for storing image data. In the method, the input image data is held for a predetermined number of bits, and the held image data is output every bit number corresponding to the plurality of different colors, thereby outputting as parallel data for each color component. A register for counting the input of the predetermined clock signal, exchanging the number of bits corresponding to the number of recording colors from the lower order of the count value with an upper order bit group, and outputting as an address indicating a write position of data to the memory. Generating means for storing image data of each color component inputted in a predetermined order in the shift register. Image recording apparatus and to store the image data to be output as parallel data from the shift register to the memory according to the address generated by said address generating means. 3. The shift register outputs image data of each color component as parallel data in byte units for each color, and the predetermined clock signal input to the address generating means generates byte data for each color. 3. The method according to claim 2, wherein the input is performed in synchronization with the operation.
An image recording device according to the above item.