JPH07195743A - Recording device - Google Patents

Abstract

PURPOSE:To reduce an intervension by a shock wave and prevent an image from being disorganized, by a method wherein the device is constituted so that an angle to be formed with an arranging direction of a recording element and a relative scanning direction between a recording head and a recorded medium is set up in a fixed state, the recording elements which is made into a group are divided equally by a number of groups within a driving cycle of the recording head for driving. CONSTITUTION:Dots are arranged and formed on recording paper as shown in the right on the drawing it is decided that nozzles Y1-Y2 are arranged on printing head as shown in the left and the printing head is inclined in a fixed state to the recording paper. At this time, an angle theta to be formed with an arranging direction of a recording element and a relative running direction between the printing head and the recording paper is set up so that a formula is satisfied between a pixel pitch (a) of a relative direction and vertical direction of the recording head and the recording paper and a pixel pitch (b) of the relative scanning direction, wherein 1<=P<M, M is taken as a number of groups by which the recording element is divided in an equal distance. Then the group is driven by dividing the recording head equally into M within a driving cycle of the recording head.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus for recording on a recording medium by time division driving.

[0002]

2. Description of the Related Art There are a dot impact recording method, a thermal recording method, an ink jet recording method and the like as a method of recording on a recording medium with a recording head having a plurality of recording elements. In these methods, when the number of recording elements increases, the power consumption for driving instantaneously increases, which leads to an increase in size of the power supply device and an increase in current capacity of the power supply line for power supply.

Further, in the ink jet recording system, when a large number of nozzles (recording elements) are driven at the same time, the shock wave generated in each nozzle causes a large interference in the common liquid chamber on the ink supply side in the recording head, so that ejection is not possible. Be stable.

A method that has been often used as a means for solving the problem is a method in which a recording element is divided into a plurality of groups and dividedly driven within a driving cycle. In this method, driving power consumption is dispersed within a driving cycle to reduce problems in the power supply system, and in the inkjet recording method, shock wave interference is reduced.

[0005]

However, what is recorded at a regular pixel position on the recording medium only after being originally driven simultaneously, the recording position is different from the regular pixel position as shown in FIG. 15 due to the division drive. Therefore, the image is disturbed.
The example of FIG. 15 is a case where the number of divisions is four and the division drive is performed. The broken line intersection is the normal recording position, ● is the position where ink droplets landed by the recording head according to the image information, and ○ does not appear on the recording paper originally, but the ink droplets did not land according to the image information. Indicates the position. This example is an example in which vertical ruled lines are printed, and it can be seen that if the divided drive timings are widely dispersed within the drive cycle, image distortion is large.

Therefore, the division drive timing cannot be widely dispersed, and FIG. 16 shows an example in which the division drive is equally divided drive within a half of the drive cycle. Although the image distortion is reduced, it still exists, and the effect of suppressing the interference in the common liquid chamber is reduced to half.

According to the present invention, the division drive timing is widely dispersed within the drive cycle to further reduce the malfunction of the power supply system and the shock wave interference in the case of the ink jet recording method, and the image is not disturbed even when the division drive is performed. It is an object to provide a recording device.

[0008]

In order to achieve the above-mentioned object, a recording apparatus of the present invention divides a plurality of recording elements arranged on a straight line into M groups of a predetermined distance unit, and according to image information. A recording device for performing recording on a recording medium by driving the recording head to scan the recording medium at a relative speed with respect to the recording medium by dividing the recording element into M times for recording. Direction and the relative scanning direction between the recording head and the recording medium, θ, the pixel pitch in the direction perpendicular to the relative scanning direction between the recording head and the recording medium, and the relative scanning direction between the recording head and the recording medium. When the pixel pitch is b, tan θ = (P × b) / (M × a) where P is 1 ≦
P <M is an integer, and the M groups are driven by being divided into M equal parts within the drive cycle of the recording head.

[0009]

According to the above construction, the deviation between the inclination θ and the divisional driving is canceled out, and the printing deviation can be eliminated.

[0010]

Embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration applicable to the recording apparatus of the present invention. In Figure 1, 1 is CP
U, 2 are data transfer circuits, 3 is RAM, and 4 is a print head.

CPU 1 creates print data and RAM 3
Store in the print buffer inside. CPU1 and RAM3
Data transfer between them is performed via the data transfer circuit 2. The print data stored in the print buffer is read by the data transfer circuit 2 and transferred to the print head 4. Data transfer between the data transfer circuit 2 and the RAM 3 is performed by address signal ADDRESS and data signal DAT.
A, read signal READ-, write signal WRITE
Controlled by. Here, -indicates that the signal is low active.

The data transfer circuit 2 reads the data in the print buffer byte by byte, converts it into serial data, and transfers it to the head 4. The head 4 is an inkjet head in which 128 ink ejection nozzles (ejection ports) are arranged in one row, and has a built-in 128-bit shift register. The serial data transferred from the data transfer circuit 2 is sequentially stored in the shift register, and whether to drive each nozzle is selected based on this data.
By driving the head once, a maximum of 128 dots (for example, black dots) arranged vertically in a line on the recording paper can be obtained.
Individually formed. Further, in this printer, the print head is mounted on a carriage to scan the recording paper in the horizontal direction, and the recording paper is conveyed in the vertical direction.

FIG. 2 is a block diagram of an address creating circuit for reading the print buffer in the data transfer circuit 2.

In FIG. 2, 11 is a black address (K).
Register, 12 horizontal offset for black (KH) register, 13 save register, 14 selector, 15 mask circuit, 16 inversion / non-inversion circuit, 17 adder, 18
Is a carry control circuit. The data signals D0 to 15 are C
Transfers the data written by PU1. The address register 11 and the horizontal offset register 12 receive the data signal D0.
15 to 15, the address register 11 stores the start address value and the horizontal offset register 12 stores the horizontal offset value. The CPU 1 manages the setting of the start address and the horizontal offset. Although black (K) is taken as an example of the print color here, cyan (C), magenta (M), yellow (Y), or the like may be used.

Output signal PBA0 of address register 11
˜18 are connected to the address signal ADDRESS of the RAM 3 through the output buffer. The save register 13
The value output from the address register 11 is temporarily stored and output to the signals LA0 to LA18. Selector 14 is PBA
0 to 18 or LA 0 to 18 is selected to select the signal SA
Output to 0-18. The mask circuit 15 controls masking of the output of the horizontal offset register 12. The output value of the mask circuit 15 is 0 in the mask state, and when not in the mask state, the output value of the horizontal offset register 12 is output as it is.

The inversion / non-inversion circuit 16 is a mask circuit 15.
Controls the inversion / non-inversion of the output. The adder 17 adds the output value of the selector 14 and the output value of the inverting / non-inverting circuit 16 and outputs the result as signals NPA0 to NPA18. The carry control circuit 18 controls the carry input signal of the adder 17.
The signals NPA0 to 18 are input to the address register 11 and used to reset the address value.

FIG. 3 shows the data structure of the print buffer. In FIG. 3, each rectangle shows 1-byte print data, and the expression in the rectangle shows an address where each print data is stored. In the equation, K is a start address and KH is a horizontal offset value. The 16-byte data from address K to K + 15 is print data of 128 dots that are continuous in the vertical direction, and is printed by driving the print head once. Further, the address of the print data changes by KH per dot in the horizontal direction.

FIG. 4 is a timing chart showing the operation of the data transfer circuit 2. The operation of the address creating circuit shown in FIG. 2 will be specifically described with reference to FIG.

First, the forward printing, that is, the case where the carriage scans the recording paper from left to right will be described.
In FIG. 4, CLK is a clock signal for synchronously moving the address generation circuit, and each part of the address generation circuit changes in synchronization with the rising edge of CLK. The value of the address register 11 is K and the horizontal offset register 12 is
The value of is set to KH in advance.

When the data transfer circuit 2 starts reading from the print buffer, the value K of the signals PBA0-18 is RA.
The M3 address signal ADDRESS is output, and the read pulse is output as the read signal READ-. Therefore, the print data is read from the start address K,
It is transferred to the print head 4. At the time of this first read, the start address K is stored in the save register 13, and the values of the signals LA0 to 18 become K.

Since the selector 14 selects the signals PBA0-18, the values of the signals SA0-18 are PBA0-18.
Is equal to The mask circuit 15 is in the masked state, and the output value is 0. Since the inverting / non-inverting circuit 16 is in the non-inverting state, the output value 0 of the mask circuit 15 is output as it is. Since the carry control circuit 18 sets the carry, it has the same effect as adding (incrementing) 1 to the adder 17.

In FIG. 4, the signal with the name of the adder is the output value of the inverting / non-inverting circuit 16 and the carry control circuit 18.
Of the signals SA0 to 18 and the sum of the added values are output to the signals NPA0 to 18. Since the added value is +1, the value of NPA0-18 becomes K + 1, and this value is fed back to the address register 11. Therefore, the value of the address register 11 is set to K + 1 at the next clock, the print data is read from the address K + 1 and transferred to the print head 4.

Similarly, the value of the address register 11 is sequentially added up to K + 15. Therefore, the print buffer address is read continuously from K to K + 15,
For convenience, 16 bytes of print data are transferred to the print head.

At the last clock, the selector 14 selects the signals LA0 to LA18, so that the values of the signals SA0 to 18 become the value K stored in the save register 13. Further, since the mask circuit 15 is in the non-masked state and outputs the value KH of the horizontal offset register 12, and the carry control circuit 18 resets the carry, the added value becomes KH. Therefore, the value of NPA0-18 becomes K + KH, and this value is set in the address register 11 by the last clock.

As shown in FIG. 3, the address K + KH is the print data to the right of the address K, and the address register 1
The value of 1 is automatically reset to the address on the right after transfer of the print data for one drive of the print head. Therefore, once the CPU sets the start address before scanning the carriage, it does not need to reset the address while scanning the carriage.

Next, the case of reverse printing will be described. When printing in the reverse direction, the addresses of the print buffer are continuously read from K to K + 15 as in the case of the forward printing, and 16 bytes of print data are transferred to the print head. However, at the last clock, the inverting / non-inverting circuit 1
6 is in the inverted state, and the carry control circuit 18 sets the carry, so that the added value becomes -KH. Therefore, the value of the address register 11 is K after the print data transfer is completed.
It is set to -KH and indicates the address on the left of the address K.

The selector 14 and the mask circuit 1
5, the selected state, the masked state, and the inverted state of the inverting / non-inverting circuit 16 are controlled by a timing control circuit (not shown) based on the clock signal CLK.

As described above, since the data transfer circuit according to the present example automatically reads the data in the print buffer, the CPU 1 scans the carriage by setting the start address once before scanning the carriage. In the meantime, it is not necessary to be involved in reading the print buffer. Therefore, the load on the CPU 1 is reduced.

Further, by setting the horizontal address change of the print buffer with the horizontal offset register, it becomes possible to arbitrarily set the vertical address continuation amount. For example, it is possible that the CPU 1 creates a print buffer composed of 32 bytes in the vertical direction, and at the time of printing, prints using only the print data of 16 bytes in the vertical direction. Therefore, the CPU 1 can determine the structure of the print buffer regardless of the number of dots of the print head, and the print buffer can be easily created.

Next, another example which is a premise of the present invention will be described. The main circuit configuration of the printer including the data transfer circuit in this example is the same as that in FIG. 1, and includes a CPU 1, a data transfer circuit 2, a RAM 3, and a print head 4.

FIG. 5 shows the dot structure of the print head in this example. The print head is an inkjet head in which 136 ink jet nozzles (ejection ports) are arranged in a line, and yellow ink is supplied to the 24 nozzles from the top to form yellow dots on the recording paper. Similarly, a magenta dot is formed on the next 24 nozzles, a cyan dot is formed on the lower 24 nozzles, and a black dot is formed on the lowermost 64 nozzles. A gap of 8 dots is provided between each color.

The print head has a 136-bit shift register, and whether or not to drive each nozzle is selected based on the data stored in the shift register. Since the shift register is connected to one line of 136-bit data, when transferring the data to the print head, print data of 24 dots of yellow, 24 dots of magenta, 24 dots of cyan, and 64 dots of black are arranged and sent in this order.

FIG. 6 is a block diagram of an address creating circuit for reading the print buffer in the data transfer circuit 2. 6, 101a is a black address (K) register, 101b is a yellow address (Y) register, 101c is a magenta address (M) register,
101d is a cyan address (C) register, 102a is a black horizontal offset (KH) register, 102b is a yellow horizontal offset (YH) register, 102c is a magenta horizontal offset (MH) register, 102d is a cyan horizontal offset (CH) register, 103. Is a selector, 104 is a save register, 105 is a selector, 10
6 is a selector, 107 is a mask circuit 108 is an inverting / non-inverting circuit, 109 is an adder, and 110 is a carry control circuit.

The data signals D0 to 15 transfer the data written by the CPU 1. Address registers 101a-d
And the horizontal offset registers 102a-d are data signals D
Address registers 101a-d store the start address value of each color, and horizontal offset registers 102a-d store the horizontal offset value of each color. The CPU 1 manages the setting of the start address and the horizontal offset. The outputs of the address registers 101a to 101d are selected by the selector 103 and output as signals PBA0 to 18. The signals PBA0-18 are connected to the address signal ADDRESS of the RAM 3 through the output buffer. The save register 104 temporarily stores the value output by the selector 103 and outputs it to the signals LA0 to LA18. The selector 105 selects either PBA0-18 or LA0-18 and outputs it as the signal SA0-18. Selector 10
6 selects the output of the horizontal offset registers 102a-d.

The mask circuit 107 controls the mask of the output of the selector 106. The output value of the mask circuit 107 becomes 0 in the mask state, and when not in the mask state, the output value of the selector 106 is output as it is. The inversion / non-inversion circuit 108 controls the inversion / non-inversion of the output of the mask circuit 107. The adder 109 adds the output value of the selector 105 and the output value of the inverting / non-inverting circuit 108 to obtain a signal NP.
Output to A0-18. The carry control circuit 1110 controls the carry input signal of the adder 17. Signal NPA0
.About.18 are input to the address registers 101a to 101d and used to reset the address value.

The data structure of the print buffer is shown in FIG. FIG. 7 is divided into four areas, and each area shows a print buffer for yellow, magenta, cyan, and black in order from the top. The rectangle in each area shows 1-byte print data, and the expression in the rectangle shows the address where the print data is stored. In the formula, Y is a yellow start address, YH is a yellow horizontal offset value, M is a magenta start address, MH is a magenta horizontal offset value,
C is a cyan start address, CH is a cyan horizontal offset value, K is a black start address, and KH is a black horizontal offset value.

3 bytes from address Y to Y + 2, 3 bytes from address M to M + 2, addresses C to C
The 3-byte data up to +2 and the 8-byte data from addresses K to K + 7 are print data arranged in the vertical direction, and are printed by driving the print head once. In addition, the address of the print data changes for each dot in the horizontal direction by YH for yellow, MH for magenta, CH for cyan, and KH for black.

FIG. 8 is a timing chart showing the operation of the address creating circuit of FIG. 6, showing the case of forward printing. The operation of the address creating circuit shown in FIG. 6 will be specifically described with reference to FIG.

In FIG. 8, CLK is a clock signal for synchronously moving the address generation circuit, and each part of the address generation circuit changes in synchronization with the rising edge of CLK. The values of the address registers 101a to 101d are K, Y, M,
In C, the values of the horizontal offset register 12 are KH, YH,
It is preset in MH and CH. Data transfer circuit 2
When the reading of the print buffer starts, the value Y of the address register 101b is first selected by the selector 103 and output to the signals PBA0 to PBA18. The values of the signals PBA0 to 18 are the address signal ADDR of the RAM3.
The read pulse is output to the ESS and the read pulse is output to the read signal READ-. Therefore, the print data is read from the start address Y and transferred to the print head 4. At the time of this reading, the start address Y is stored in the save register 10
4 and the values of the signals LA0 to LA18 become Y.

Since the selector 105 selects the signals PBA0-18, the values of the signals SA0-18 are PBA0-1.
Is equal to 8. Although the selector 106 selects the value YH of the horizontal offset register 102b, the mask circuit 1
Since 07 is in a masked state, the output value is 0. Since the inverting / non-inverting circuit 108 is in the non-inverting state, the mask circuit 1
The output value 0 of 07 is output as it is. Since the carry control circuit 110 has set the carry, the adder 10
It has the same effect as adding 1 to 9.

In FIG. 8, the signal with the name of the added value is the output value of the inverting / non-inverting circuit 108 and the carry control circuit 1.
The outputs of 10 are added, and the signals SA0 to 18 and the sum of the added values are output to the signals NPA0 to 18. Since the added value is +1 the value of NPA0-18 is Y +
The value becomes 1, and this value is fed back to the address register 101b.

Therefore, the value of the address register 101b is set to Y + 1 at the next clock, the print data is read from the address Y + 1 and transferred to the print head 4. Similarly, the value of the address register 101b is Y + 2.
The print buffer address is Y to Y.
Up to +2 is read and 3 bytes of yellow print data are transferred to the print head.

When the address Y + 2 is read, the selector 105 selects the signals LA0-18, so that the values of the signals SA0-18 become the value Y stored in the save register 104. Further, the mask circuit 15 is in the non-masked state and outputs the value YH of the horizontal offset register 102b, and the carry control circuit 18 resets the carry, so that the added value becomes YH. Therefore, the value of NPA0-18 becomes Y + YH, and this value is set in the address register 101b by the last clock.

As shown in FIG. 7, the address Y + YH is the print data on the right side of the address Y in the yellow print buffer, and the value of the address register 101b is automatically the address on the right side after the transfer of the yellow print data. Will be reset to. Similarly, magenta, cyan, and black print data are sequentially read. However, for black only, 8-byte print data is transferred to the print head.

Each time the transfer of print data for each color is completed,
Since the values of the address registers 101a to 101d are reset to the addresses on the right side of each print buffer, the CPU
In No. 1, once the start address is set before scanning the carriage, it is not necessary to reset the address while scanning the carriage. At the time of reverse printing, the value of the address registers 101a to 101d can be set to the address on the left side by using the inversion / non-inversion circuit 108 as in the case of the first embodiment.

The selectors 103, 105 and 10
The timing control circuit (not shown) controls the selected state, the masked state, and the inverted state of the mask circuit 107, the inversion / non-inversion circuit 108 based on the clock signal CLK.

As described above, since the data transfer circuit according to the present embodiment independently manages the print buffers for each color of yellow, magenta, cyan, and black, the data transfer to the print head transfers the print data of each color in a predetermined order. Although it must be sent in combination with
1 makes it possible to create print buffers for each color independently, and the load of print buffer creation is reduced.

By setting the horizontal address change of the print buffer of each color by the horizontal offset register, the vertical address continuation amount can be arbitrarily set. Therefore, the structure of the print buffer can be determined regardless of the number of dots of the print head, and the optimum print buffer structure can be adopted according to the processing of the CPU 1 and the memory capacity.

In the above description, it is assumed that the four color print heads are used. However, in the present example, for example, the timing control circuit described above controls to use only the black address register and the horizontal offset register. As a result, the same processing as in the above example can be performed, and thus it is naturally possible to use a monochrome head. As a result, the printer adopting this example can be equipped with print heads having different numbers of colors and different numbers of nozzles.
In that case, the data transfer method of various print heads can be supported simply by changing the setting (mode setting) of the data transfer circuit, so the print buffer configuration can be made common to different types of heads. The load on the CPU 1 can be reduced and the program size for print buffer creation processing can be reduced.

Furthermore, if the print head is provided with information for identifying the number of colors, the number of nozzles, etc., it is possible to automatically print according to the type of print head by detecting it on the printer side. Becomes

As described above, in this example, the data transfer circuit independently controls the addresses of the print buffers of the respective colors, so that the data transfer to the print head requires sending the print data of the respective colors in combination. No, C
The PU can create print buffers for each color separately, and the load of creating print buffers is reduced. In addition, it is possible to easily use print heads having different numbers of colors and dots, and the print buffer can be configured in common for different types of heads, which reduces the load on the CPU.

Example 1 Next, an example of the present invention will be described. The main circuit configuration of the printer including the data transfer circuit in this embodiment is the same as that of FIG.
1, a data transfer circuit 2, a RAM 3, and a print head 4. Further, the dot configuration of the print head in this embodiment is the same as that in FIG. 5, 136 ink jet nozzles are arranged in a line, and 24 dots of yellow, 24 dots of magenta, 24 dots of cyan, and 64 dots of black are arranged in this order from the top. Composed.

FIG. 9 is a timing chart showing the drive sequence of the print head in this embodiment. In FIG. 9, the print head is driven in a time division manner, and 136 nozzles are divided into 16 times and driven. Adjacent nozzles are sequentially driven at different timings (for example, Y16, Y15,
...) and the nozzles that are driven at the same time are every 16 dots (including a gap of 8 dots between the nozzle groups, that is, 1 nozzle).
The distance unit corresponds to 6 dots). By time-division drive, the peak value of the current required to drive the print head can be reduced and the load on the power supply can be reduced. Further, by driving the adjacent nozzles at different timings, it is possible to reduce the vibration of the ink in the head due to the ejection of the ink droplets, the ink ejection characteristics of the head, and the ink refill time (refill time).
Can be improved.

However, since the serial printer drives the print head while moving the print head with respect to the recording paper, the deviation of the driving timing is the deviation of the dot position on the recording paper. In the driving method as shown in FIG. 9, the dot rows are formed in a saw shape with a time difference due to time division. Therefore, when the print head is driven in a time-division manner, it is necessary to take some measures so as not to cause print misalignment due to a time difference in drive timing.

A method of preventing print deviation due to time-division driving in this embodiment will be described with reference to FIG. The diagram on the left side of FIG. 10 shows the nozzle arrays from the first (Y1) to the twentieth (Y20) of yellow which is the upper part of the print head, and the print head is 3.58 with respect to the vertical line on the recording paper. It is attached to the carriage in a tilted state. That is, the print head has an inclination of 1 dot in the horizontal direction for every 16 dots in the vertical direction. The carriage scans the recording paper in the horizontal direction. In the figure, L indicates one dot pitch, which is 70.6 μm (360 DPI) in this embodiment.

In this state, the dot arrangement formed on the recording paper by the driving sequence of FIG. 9 is shown on the right side of FIG. Since the deviation of the driving timing due to the time division driving is canceled by the head inclination,
The dots up to the nozzle eye are arranged vertically so that no print misalignment occurs. Since the dots after the 17th nozzle are vertically arranged with a distance of 1 dot to the right, the dots in the adjacent column on the right side are formed, and no printing deviation occurs. That is, when viewed from the entire print head, dots in the adjacent row are formed for every 16 nozzles as shown in FIG. 11, and the print head is driven once to form a staircase (one dot interval) on the recording paper.
10 dot rows are formed.

That is, in this embodiment, the angle formed by the arrangement direction of the recording elements and the relative scanning direction of the recording head and the recording medium is θ = 3.58 degrees, and is perpendicular to the relative scanning direction of the recording head and the recording medium. Direction pixel pitch is a = 70.6μ
m and the pixel pitch in the relative scanning direction between the recording head and the recording medium is b = 70.6 μm, tan θ = (P × b) / (M × a) = 1/16, (P =
1, M = 16), and 16 groups are set to 1 within the drive cycle of the recording head.
The drive is divided into six equal parts.

FIG. 12 is a block diagram of an address creating circuit for reading the print buffer in the data transfer circuit 2. In FIG. 12, address (K to C) registers 101a to d, horizontal offset (KH to CH) registers 102a to d, selector 103, save register 1
04, selector 105, selector 106, mask circuit 1
The functions of 07, the inverting / non-inverting circuit 108, the adder 109, and the carry control circuit 110 are the same as those in FIG.

111 is a staircase pattern (ZP) register,
Reference numeral 112 denotes a selector, and in this embodiment, these circuits are characteristic of the above example.

The staircase pattern register 111 is connected to the data signals D0 to D15 and stores the staircase pattern of the print head. The staircase pattern is data indicating the shape of a dot row formed by driving the print head once. The selector 112 selects staircase pattern data. The output of the selector 112 is input to the mask circuit 107 to control the mask state.

The data structure of the print buffer is shown in FIG. The structure of the print buffer itself is exactly the same as that in FIG. 7, but the data printed by one-time driving of the print head is the hatched portion in FIG. 13, namely, 3 bytes of address Y, Y + 1, Y + 2, YH, and address. 3 bytes of M, M + 1, M + 2 + MH, addresses C, C
+1, C + 2 + CH 3 bytes and addresses K to K
It is 8 bytes up to + 7 + 3KH. Therefore, when the print data is transferred to the print head, the print buffer is read obliquely as shown by the colored portion in FIG.

FIG. 14 is a timing chart showing the operation of the address generating circuit of FIG. 12, showing the case of forward printing. The operation of the address creating circuit shown in FIG. 12 will be specifically described with reference to FIG.

In FIG. 14, CLK is a clock signal for synchronously moving the address generation circuit, and each part of the address generation circuit changes in synchronization with the rising edge of CLK. The values of the address registers 101a to 101d are K, Y,
For M and C, the values of the horizontal offset register 12 are KH and Y.
It is preset to H, MH, and CH. The value of the staircase pattern register 111 is set so that it is set every 16 dots of print data, that is, once every 2 bytes. When the data transfer circuit 2 starts reading the print buffer, the value Y of the address register 101b is first read.
Are selected by the selector 103, and the signals PBA0-PBA0
18 is output. The values of the signals PBA0-18 are RAM3
Address signal ADDRESS, and a read pulse is output as a read signal READ-. Therefore, the print data is read from the start address Y and transferred to the print head 4. At the time of this reading, the start address Y is stored in the save register 104 and the signals LA0 to LA1
The value of 8 becomes Y.

Since the selector 105 selects the signals PBA0-18, the values of the signals SA0-18 are PBA0-1.
Is equal to 8. Although the selector 106 selects the value YH of the horizontal offset register 102b, the mask circuit 1
Since 07 is in a masked state, the output value is 0. Since the inverting / non-inverting circuit 108 is in the non-inverting state, the mask circuit 1
The output value 0 of 07 is output as it is. Since the carry control circuit 110 has set the carry, the adder 10
It has the same effect as adding 1 to 9.

In FIG. 14, the signal with the name of the added value is the sum of the output value of the inversion / non-inversion circuit 108 and the output of the carry control circuit 110.
And the sum of these added values is output to the signals NPA0-18.
Since the added value is +1 the value of NPA0-18 is Y
It becomes +1 and this value is fed back to the address register 101b. Therefore, the address register 101
The value of b is set to Y + 1 at the next clock and the address Y
The print data is read from +1 and transferred to the print head 4.

At this time, since the output of the selector 112 is set by the setting of the staircase pattern register 111, the mask circuit 107 is in the non-masked state and outputs the value YH of the horizontal offset register 102b. Therefore, the added value becomes + 1 + YH, and the address register 101b
Is added up to Y + 2 + YH at the next clock. Therefore, for the yellow print buffer, the print data read from the 3 bytes at the addresses Y, Y + 1, Y + 2 + YH is transferred to the print head.

When the address Y + 2 + YH is read, the selector 105 selects the signals LA0 to LA18, so that the values of the signals SA0 to 18 become the value Y stored in the save register 104. Further, since the mask circuit 15 is in the non-masked state and outputs YH, and the carry control circuit 18 resets the carry, the added value becomes YH. Therefore, the value of NPA0-18 becomes Y + YH, and this value is set in the address register 101b. Similarly, magenta, cyan, and black print data are sequentially read. However, for black only, 8-byte print data is transferred to the print head.

Each time the print data of each color is transferred,
Since the values of the address registers 101a to 101d are reset to the addresses on the right side of each print buffer, the CPU
In No. 1, once the start address is set before scanning the carriage, it is not necessary to reset the address while scanning the carriage. During reverse printing, the value of the address registers 101a to 101d can be set to the address on the left side by using the inversion / non-inversion circuit 108.

The selectors 103, 105 and 10
6, 112, mask circuit 107, inverting / non-inverting circuit 10
The selection state, the mask state, and the inversion state of No. 8 are set by the timing control circuit (not shown) as in the embodiment.
It is controlled based on.

As described above, the data transfer circuit according to the present embodiment has a function of reading the print buffer obliquely in correspondence with the stepwise dot array shape formed by the print head, so that the CPU 1 is aware of the dot array shape. The print data in the print buffer can be created without doing so, and the load on the CPU can be reduced.

In the present embodiment, the case in which the column is switched every 16 dots has been described. However, if the switching dot length is a transfer unit of print data, that is, a multiple of 8 dots, the set value of the staircase pattern register is simply changed. Correspondence is possible. It is also possible to use a monochrome head.

As described above, since the data transfer circuit has the function of reading the print buffer according to the dot arrangement shape of the print head, the CPU can create print data without being aware of the dot arrangement shape of the print head. it can.

When used in the ink jet recording system, it is possible to reduce the interference of shock waves in the common liquid chamber.

(Second Embodiment) FIG. 17 schematically shows a second embodiment of the present invention. The recording head 4 is of the bubble jet type, has 32 nozzles, and has a four-division drive configuration as shown in the circuit diagram of FIG. Here, 41 is a 64-bit shift register, 42 is a latch register,
43 is an AND gate for block selection, and 44 is a heating element.

The angle θ formed by the nozzle arrangement direction of the recording head 4 and the vertical direction of the recording head 4 in the scanning direction (arrow A) with respect to the recording paper 5 has a relationship of tan θ = 1/4. This embodiment is an example in which M = 4 and P = 1 and the vertical and horizontal pixel pitches are equal. The vertical and horizontal pixel pitch is 360 dpi, so the nozzle pitch is 360 × cos (tan ⁻¹ (1/4)), that is, about 349 dpi.

The drive frequency of the recording head 4 is 3 kHz, and a carriage (not shown) for scanning the recording head 4 scans the recording paper 5 in the direction of arrow A at a speed of 211.7 mm / sec. The group numbers of the 32 nozzles included in the recording head 4 are BLOCK1, BLOCK2, B in order from the top.
LOCK3, BLOCK4, BLOCK1, BLOCK
2, BLOCK3, BLOCK4, ... The driving order of each group is (m × P / M + C), and in this example, C =
If -0.25 is set, the order of the values after the decimal point becomes the driving order, that is, BLOCK1, BLOCK2, BLOCK3, BL.
It becomes OCK4.

The drive circuit of FIG. 18 is driven by equal division as shown in FIG. Since the drive frequency of the recording head 4 is 3 kHz (333 μs) as described above, the drive cycle of each group is 83.3 μs. The pixel pitch shift between the adjacent nozzles in the direction of arrow A is 1/4 pixel, which is 83.3.
The carriage advances ¼ pixel in the period of μs. Therefore, the droplets ejected from each nozzle land exactly at the regular pixel position as shown in FIG.

As the data for the nozzles in each group, the data of the corresponding column may be read and given by using the data transfer circuit shown in the first embodiment.

(Embodiment 3) Embodiment 3 is shown in FIG. In this example, a recording apparatus of 600 dpi is realized by using a recording head of 360 dpi without image disturbance. The angle θ is configured to have the following expression.

Tan θ = 4/3 M is 3, and three-division driving is performed. The circuit configuration is shown in FIG. Here, parts corresponding to those in FIG. 18 are designated by the same reference numerals.

The driving order of the three groups is (m × P / M +
C), that is, in the ascending order after the decimal point of (m × 4/3 + C). C is an element that determines the initial value of the cyclically driven group order, and is -1/3 in this example. The group numbers are BLOCK1, BLOCK2, BLOCK3, B in order from the top of the recording head 4 as in the second embodiment.
LOCK1, BLOCK2, BLOCK3 ... From the above, the driving order of each group is BLOCK1, BLOC
K2, BLOCK3, BLOCK1, BLOCK2, B
.., and the drive waveform is shown in FIG.

(Others) The present invention provides excellent effects particularly in a recording apparatus using an inkjet recording head for recording by forming thermal liquid by utilizing thermal energy among inkjet recording systems. Is.

Regarding its typical structure and principle, see, for example, US Pat. Nos. 4,723,129 and 4740.
What is done using the basic principles disclosed in 796 is preferred. This method is a so-called on-demand type,
Although it is applicable to any of the continuous type, in particular, in the case of the on-demand type, to the electrothermal converter arranged corresponding to the sheet or liquid path holding the liquid (ink), By applying at least one drive signal that corresponds to the recorded information and causes a rapid temperature rise beyond nucleate boiling, heat energy is generated in the electrothermal converter, causing film boiling on the heat-acting surface of the recording head. As a result, the liquid (ink) that responds to this drive signal as a single unit
It is effective because bubbles can be formed inside. The liquid (ink) is ejected through the ejection openings by the growth and contraction of the bubbles to form at least one droplet. It is more preferable to make this drive signal into a pulse shape because bubbles can be immediately and appropriately grown and contracted, so that liquid (ink) ejection with excellent responsiveness can be achieved. As the pulse-shaped drive signal, those described in US Pat. Nos. 4,463,359 and 4,345,262 are suitable. If the conditions described in US Pat. No. 4,313,124 of the invention relating to the rate of temperature rise on the heat acting surface are adopted, more excellent recording can be performed.

The structure of the recording head is the combination of a discharge port, a liquid passage, and an electrothermal converter (straight liquid passage or right-angled liquid passage) as disclosed in the above-mentioned specifications. In addition, US Pat. No. 4,558,333 and US Pat. No. 4, which disclose a configuration in which a heat acting portion is arranged in a bending region.
A configuration using the specification of No. 459600 is also included in the present invention. In addition, Japanese Unexamined Patent Publication No. 59-123670 discloses a configuration in which a common slit is used as a discharge portion of the electrothermal converter for a plurality of electrothermal converters, and an opening for absorbing a pressure wave of thermal energy is provided. The effect of the present invention is effective even if the structure corresponding to the discharging portion is disclosed in Japanese Patent Laid-Open No. 59-138461. That is, according to the present invention, recording can be surely and efficiently performed regardless of the form of the recording head.

Further, the present invention can be effectively applied to a full line type recording head having a length corresponding to the maximum width of a recording medium which can be recorded by the recording apparatus. Such a recording head may have a structure that satisfies the length by combining a plurality of recording heads or a structure as one recording head integrally formed.

In addition, even in the case of the serial type as in the above example, the recording head fixed to the main body of the apparatus, or the electrical connection to the main body of the apparatus or the ink from the main body of the apparatus by being attached to the main body of the apparatus The present invention is also effective when a replaceable chip-type recording head that can be supplied or a cartridge-type recording head in which an ink tank is integrally provided in the recording head itself is used.

Further, as the constitution of the recording apparatus of the present invention, it is preferable to add ejection recovery means of the recording head, preliminary auxiliary means and the like because the effect of the present invention can be further stabilized. Specifically, heating is performed by using a capping unit, a cleaning unit, a pressure or suction unit for the recording head, an electrothermal converter or a heating element other than this, or a combination thereof. Examples thereof include a preliminary heating unit for performing the discharge and a preliminary discharge unit for performing discharge different from the recording.

Regarding the type and number of recording heads to be mounted, two or more recording heads may be provided corresponding to a plurality of inks having different recording colors and densities. That is, for example, the recording mode of the recording apparatus is not limited to the recording mode of only the mainstream color such as black, but it may be either the recording head is integrally formed or a plurality of combinations may be used. The present invention is also extremely effective for an apparatus provided with at least one of full-color recording modes by color mixing.

In addition, in the above-described embodiments of the present invention, the ink is described as a liquid, but an ink that solidifies at room temperature or lower and that softens or liquefies at room temperature may be used. Or, in the inkjet system, it is common to adjust the temperature of the ink itself within the range of 30 ° C. or higher and 70 ° C. or lower to control the temperature so that the viscosity of the ink is within the stable ejection range. Sometimes, a liquid ink may be used. In addition, the temperature rise due to thermal energy is positively prevented by using it as the energy of the state change of the ink from the solid state to the liquid state, or in order to prevent the evaporation of the ink, it is solidified and heated in the standing state. You may use the ink liquefied by. In any case, by applying thermal energy such as ink that is liquefied by applying thermal energy according to the recording signal and liquid ink is ejected, or that begins to solidify when it reaches the recording medium. The present invention can be applied to the case where an ink having a property of being liquefied for the first time is used. In this case, the ink is
JP-A-54-56847 or JP-A-60-7
As described in Japanese Patent No. 1260, it may be configured to face the electrothermal converter in a state of being held as a liquid or a solid in the concave portion or the through hole of the porous sheet. In the present invention, the most effective one for each of the above-mentioned inks is to execute the above-mentioned film boiling method.

In addition, as the form of the ink jet recording apparatus of the present invention, besides the one used as an image output terminal of an information processing apparatus such as a computer, a copying apparatus combined with a reader or the like, and a facsimile apparatus having a transmission / reception function It may be a form or the like.

The present invention is not limited to the ink jet recording system, but can be applied to other recording systems such as a thermal recording system and a wire dot recording system.

[0093]

According to the present invention, the division drive timing is widely and equally distributed within the drive cycle to further reduce the current concentration of the power source and the shock wave interference in the case of the ink jet recording system, and the division drive is performed. It is possible to supply a recording device without image distortion.

Further, according to the present invention, it is possible to record with an arbitrary pixel pitch higher than the nozzle pitch of the recording head.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main circuit configuration of a printer.

FIG. 2 is a block diagram of an address generation circuit.

FIG. 3 is a diagram showing a data structure of a print buffer.

FIG. 4 is a timing chart showing the operation of the address generation circuit.

FIG. 5 is a diagram showing a dot configuration of a print head.

FIG. 6 is a block diagram of an address generation circuit.

FIG. 7 is a diagram showing a data structure of a print buffer.

FIG. 8 is a timing chart showing the operation of the address generation circuit.

FIG. 9 is a timing chart showing a drive sequence of the print head.

FIG. 10 is a diagram showing in detail the dot arrangement of a part of the print head of the first embodiment.

FIG. 11 is a diagram illustrating a dot array of the entire print head according to the first exemplary embodiment.

FIG. 12 is a block diagram of an address creating circuit according to the first embodiment.

FIG. 13 is a diagram illustrating a data structure of a print buffer according to the first embodiment.

FIG. 14 is a timing chart showing the operation of the address creating circuit according to the first embodiment.

FIG. 15 is a diagram showing an example of printing by conventional time division driving.

FIG. 16 is a diagram showing another example of printing by conventional time-division driving.

FIG. 17 is a diagram illustrating a print head according to a second exemplary embodiment.

FIG. 18 is a circuit diagram illustrating a configuration of a recording head according to a second embodiment.

FIG. 19 is a timing chart of the second embodiment.

FIG. 20 is a diagram illustrating a printing example according to the second embodiment.

FIG. 21 is a diagram illustrating a print head according to a third exemplary embodiment.

FIG. 22 is a circuit diagram showing a configuration of a recording head of Example 3.

FIG. 23 is a timing chart of the third embodiment.

[Explanation of symbols]

 1 CPU 2 data transfer circuit 3 RAM 4 print head 11 address register 12 horizontal offset register 13 save register 14 selector 15 mask circuit 16 inversion / non-inversion circuit 17 adder 18 carry control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location B41J 2/255 B41J 3/04 103 B 3/10 106 L (72) Inventor Toshiharu Inui Ota, Tokyo 3-30-2 Shimomaruko-ku, Canon Inc. (72) Inventor, Kazuhiro Nakata 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (3)

[Claims] 1. A recording head, which divides a plurality of recording elements arranged on a straight line into M groups each having a predetermined distance unit, and divides the recording element into M groups according to image information to perform recording, relative to a recording medium. A recording device that performs scanning at a speed and drives the recording head to perform recording on a recording medium, wherein an angle formed by an array direction of the recording elements and a relative scanning direction of the recording head and the recording medium is θ, the pixel pitch in the direction perpendicular to the relative scanning direction of the recording head and the recording medium is a,
When the pixel pitch in the relative scanning direction between the recording head and the recording medium is b, tan θ = (P × b) / (M × a) where P is 1 ≦
A recording apparatus, wherein P <M is an integer, and the M groups are driven by being divided into M equal parts within a drive cycle of the recording head. 2. When the group number m of M groups (a natural number less than or equal to M) is the order of recording element arrangement, m
2. The recording apparatus according to claim 1, wherein division driving is performed in the ascending order of the values after the decimal point of × P / M + C (where C is a constant including the decimal point). 3. The recording apparatus according to claim 1, wherein the recording head ejects ink by heat.