JP3673538B2 - Method for forming nonvolatile semiconductor memory device - Google Patents

Description

[0001]
[Industrial application fields]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device (so-called EEPROM) capable of electrically writing and erasing information and having a memory effect that does not require external power to hold information and a method for forming the same It is.
[0002]
[Prior art]
A conventional nonvolatile semiconductor memory device is disclosed in, for example, Document I (“Monthly Semiconductor World”, April 1991, pages 94 to 98, press journal).
[0003]
FIG. 8 shows an example of the structure of the nonvolatile memory device disclosed in Document I.
[0004]
This conventional structure is also called an ETOX (EEPROM with Tunnel Oxide) cell, and the configuration of the cell is as follows.
[0005]
The ETOX cell includes a P-conductivity type semiconductor substrate 50, a tunnel oxide film 52, a floating gate electrode 54, an interlayer insulating film 56, a control gate electrode 58, n⁺ Type source region 60, n⁺ Type drain region 62, n^- A type source region 64 and a p type drain region 66 are formed.
[0006]
This ETOX cell is structurally the same as an EEPROM, but is characterized in that the tunnel oxide film 52 of the cell is formed to about 10 nm (nanometers).
[0007]
N⁺ In order to suppress the tunnel leak between the bands on the lower surface of the type source region 60, n^- A mold source region 64 is provided.
[0008]
N⁺ A p-type drain region 66 is provided on the lower surface of the type drain region 62 in order to improve the writing efficiency.
[0009]
On the substrate 50, a tunnel oxide film 52, a floating gate electrode 54, an interlayer insulating film 56, and a control gate electrode 58 are stacked. The tunnel oxide film 52 provided on the substrate 50 is provided in contact with a part of each of the source region 60 and the drain region 62.
[0010]
In recent years, an insulating film having a three-layer structure of an upper oxide film / nitride film / lower oxide film (Oxide-Nitride-Oxide film: abbreviated ONO film) has been put into practical use as the interlayer insulating film 56 (FIG. 13 of Reference I). , P98).
[0011]
[Problems to be solved by the invention]
However, when an ONO film is used as the above-described conventional ETOX type interlayer insulating film (upper oxide film / nitride film / lower oxide film), a lower oxide film is formed on the floating gate electrode. At this time, a lower oxide film is formed by performing a high-temperature heat treatment by thermal oxidation (for example, 1000 ° C. for 10 minutes in oxygen gas). For this reason, there is a problem that phosphorus (P) contained in the floating gate electrode penetrates into the lower oxide film or the tunnel oxide film and the film thickness becomes non-uniform. The reason for this will be described with reference to FIGS.
[0012]
7A shows a cross-sectional view in which a tunnel oxide film 52 and a floating gate electrode 54 are respectively stacked on a substrate 50, and FIG. 7B shows a lower layer oxidation by heating treatment on the upper surface of the floating gate conductor layer 54. It is sectional drawing which shows the state in which the film | membrane 56 was formed. The heating condition at this time is oxygen (O₂ ) Heat treatment (1000 ° C., 10 minutes) in gas.
[0013]
As can be understood from FIG. 7A, before the lower oxide film 56 is formed by thermal oxidation, no growth of the crystal grain boundary is observed in the floating gate electrode formed of polysilicon. However, as can be understood from FIG. 7B, the <110> direction in the floating gate electrode 54 formed of polysilicon by performing thermal oxidation to form the lower oxide film 56 on the surface of the floating gate electrode. Then, the crystal grain boundary 59 grows with strong orientation. At this time, the crystal grain boundary 59 has grown to the upper and lower surfaces of the floating gate electrode 54. For this reason, phosphorus (P) atoms doped in the floating gate electrode 54 are segregated at the grain boundaries. Segregation here refers to a state in which phosphorus atoms are discharged to the grain boundaries and phosphorus (P) is accumulated at the interface between the tunnel oxide film 52 or the lower oxide film 56 and the floating gate electrode 54. For this reason, high-concentration phosphorus is distributed on the upper surface or the lower surface of the floating gate electrode 54. For example, in the process of forming the lower oxide film 56, the portion where the crystal grain boundary 59 occurs and the portion where it does not occur are oxidized. A difference occurs in the film growth rate. As a result, irregularities occur at the interface between the floating gate electrode 54 and the lower oxide film 56 or at the interface between the tunnel oxide film 52 and the floating gate electrode 54. For this reason, the thicknesses of the tunnel oxide film 52 and the lower oxide film 56 themselves are not uniform. In addition, phosphorus segregated at each interface is diffused also into the lower oxide film 56 and the tunnel oxide film 52, and therefore the data retention characteristics of the EEPROM are deteriorated. The reason is considered as follows.
[0014]
When phosphorus diffuses into the tunnel oxide film 52 and the lower oxide film 56, this phosphorus element becomes the center of trapping positive charges, so that the energy band of each oxide film is bent, and as a result, the effective band forming band is obtained. The potential barrier height (barrier height) is lowered. For this reason, electrons easily tunnel through the tunnel oxide film 52 or the lower oxide film 56, so that the data retention characteristics of the EEPROM deteriorate. Therefore, the electrons accumulated in the floating gate electrode 54 easily move to the control gate electrode side or the source region side, the data retention characteristics deteriorate, and the optimum data rewrite operation cannot be performed.
[0015]
Several methods for preventing the diffusion of phosphorus atoms doped in the floating gate electrode have been considered. One of them is a method of lowering the oxide film formation temperature when forming the lower oxide film by thermal oxidation.
[0016]
However, since the formation of the lower oxide film of the nonvolatile semiconductor memory device is usually performed using a thermal oxidation method, if the film formation temperature is lowered, the oxide film formation rate is reduced, and a desired oxide film is formed. It takes a long time for heat treatment to obtain the thickness. For this reason, phosphorus atoms in the floating gate diffuse into the lower oxide film or tunnel oxide film, and the interface between the floating gate electrode / lower oxide film and the floating gate electrode / tunnel oxide film is aligned. There is a problem that the uniformity of the film thickness itself deteriorates.
[0017]
Another method for preventing the diffusion of phosphorus atoms is to suppress the concentration of phosphorus (P) contained in the floating gate electrode. However, lowering the concentration of phosphorus (P) doped in the floating gate electrode increases the electric resistance of the floating gate electrode, which is naturally limited. Therefore, the P concentration is 1 × 10²⁰Atom / cm^Three Cannot be lowered below.
[0018]
Therefore, the growth of the crystal grains of the floating gate electrode is suppressed, the consistency of the interface between the interlayer insulating film and the floating gate electrode, and the uniformity of the thickness of the tunnel oxide film at the interface between the floating gate electrode and the tunnel oxide film. An excellent nonvolatile semiconductor memory device and a method for forming the same have been desired.
[0019]
[Means for Solving the Problems]
  According to a first aspect of the present invention, there is provided a semiconductor substrate of a first conductivity type, a source region and a drain region provided in the vicinity of the surface of the semiconductor substrate, a tunnel oxide film sequentially stacked on the semiconductor substrate,Formed on the tunnel oxide filmFloating gate electrode,It is formed on the floating gate electrode and consists of lower oxide film, nitride film, and upper oxide filmInterlayer insulation filmAnd formed on the interlayer insulating filmNonvolatile semiconductor memory device having control gate electrodeForming methodAbout.
  AndA floating gate is formed on the oxide film to be a tunnel oxide film by performing a heat treatment using a mixed gas of a silicon-containing group IV hydrogen gas, a germanium-containing group IV gas, and a dopant gas for doping an impurity element. Impurity concentration of electrode is 5 × 10 ²⁰ Atom / cm ^Three Above Si _1-x ―Ge _x A step of forming a mixed film (x is a numerical value representing a composition and takes a value between 0.05 <x <0.4), a lower oxide film of an interlayer insulating film, and a surface of a floating gate electrode And a step of forming by thermal oxidation.
[0021]
  According to a second aspect of the present invention, there is provided a first conductivity type semiconductor substrate, a source region and a drain region provided in the vicinity of the surface of the semiconductor substrate, a tunnel oxide film sequentially stacked on the semiconductor substrate,Formed on the tunnel oxide filmFloating gate electrode,It is formed on the floating gate electrode and consists of lower oxide film, nitride film, and upper oxide filmInterlayer insulation filmAnd formed on the interlayer insulating filmThe present invention relates to a method for forming a nonvolatile semiconductor memory device including a control gate electrode.
  And tunnel oxide filmAs oxide filmOn top, by performing a heat treatment using a mixed gas of a silicon-containing group IV hydrogen gas and a germanium-containing group IV gas,Floating gate electrodeSi_1-x―Ge_xMixed film (x is a numerical value representing the composition and takes a value between 0.05 <x <0.4)As this is formed, this Si _1-x ―Ge _x By doping the mixed film with an impurity element, the impurity concentration of the floating gate electrode is reduced to 5 × 10 5. ²⁰ Atom / cm ^Three And a step of forming the lower oxide film of the interlayer insulating film by thermally oxidizing the surface of the floating gate electrode.
[0022]
  According to a third aspect of the present invention, there is provided a semiconductor substrate of a first conductivity type, a source region and a drain region provided in the vicinity of a surface of the semiconductor substrate, a tunnel oxide film sequentially stacked on the semiconductor substrate,Formed on the tunnel oxide filmFloating gate electrode,It is formed on the floating gate electrode and consists of lower oxide film, nitride film, and upper oxide filmInterlayer insulation filmAnd formed on the interlayer insulating filmThe present invention relates to a method for forming a nonvolatile semiconductor memory device including a control gate electrode.
  And (a) the tunnel oxide filmOxide filmOn top, heat treatment using silicon-containing group IV hydrogen gasPolysilicon for floating gate electrodeAnd (b) after the first step,Polysiliconinside,The minimum concentration of germanium atoms in the floating gate electrode is 1 × 10 ^{twenty one} Atom / cm ^Three In order toA second step of implanting germanium ions by ion implantation, and (c) after the second step,PolysiliconinsideThe impurity concentration in the floating gate electrode is 5 × 10 ²⁰ Atom / cm ^Three To do this,A third step of doping an impurity element; and (d) after the third step, germanium ions and an impurity element were included.PolysiliconAnd (e) after the fourth step,Polysilicon to form the lower oxide layer of the interlayer insulation filmThermally oxidize the surface ofFirstWith 5 stepsWithIt is characterized by that.
[0024]
[Action]
  Mentioned aboveFirst1 and 2In the invention,Oxide film as tunnel oxide filmThe silicon-containing group IV hydrogen-based gas and the germanium-containing group IV-based gas are then heat-treated to form Si._1-x-Ge_xMixed crystal (x is a numerical value representing the composition and takes a value between 0.05 <x <0.4.)FormationFurthermore, the impurity concentration of the floating gate electrode is set to 5 × 10 ²⁰ Atom / cm ^Three Or more. Si formed at this time_1-x-Ge_xSince the mixed crystal contains germanium atoms having an atomic radius larger than that of silicon atoms, lattice distortion occurs in the silicon lattice. For this reason, as is well known, increasing the film thickness increases the strain energy and causes dislocations. For this reason, Si_1-x-Ge_xThe film thickness at which the mixed crystal grows has its own limit (the film thickness at this time is called the critical film thickness), and the critical film thickness can be controlled by the x composition of germanium. Si formed in this way_1-x-Ge_xThe crystal diameter of the mixed crystal is smaller than that of conventional polysilicon.
[0025]
  In the third invention, first,Oxide film to be tunnel oxide filmaboveFor floating gate electrodePolysilicoTheAfter formingThe minimum concentration of germanium atoms in the floating gate electrode is 1 × 10 ^{twenty one} Atom / cm ^Three In order toBy ion implantationPolysiliconGermanium ions are implanted inside. after that,Impurity concentration in floating gate electrode is 5 × 10 ²⁰ Atom / cm ^Three Polysilicon to make the aboveAn impurity element is doped therein. Subsequently, containing germanium ions and impurity elements.Da polysiliconAnneal. Formed in this wayPolysiliconSince germanium atoms are contained therein, the crystal diameter of polysilicon can be reduced. For this reason, even if high temperature heat treatment is performedPolysiliconBecause no grain boundaries are generated inside,PolysiliconWhenOxide film to be tunnel oxide filmInterface withPolysiliconWhenInterlayer dielectric underlayer oxide filmImpurity elements do not segregate at the interface part.
[0026]
【Example】
A structure of a non-volatile semiconductor memory device (hereinafter referred to as EEPROM) of the present invention that can be electrically rewritten according to the present invention and a method for forming the same will be described below with reference to the drawings. However, the drawings only schematically show the shape, size, and arrangement of each component to the extent that the present invention can be understood.
[0027]
[Formed by the forming method of the present inventionDescription of EEPROM structure]
  FIG.BookinventionFormed by the forming methodIt is sectional drawing for demonstrating the main structures of this EEPROM.
[0028]
First, a p-conductivity type semiconductor substrate (hereinafter referred to as a substrate) is used as the first conductivity-type semiconductor substrate 10. The substrate 10 has a specific resistance of, for example, 3 Ω · cm to 5 Ω · cm, and a crystal plane orientation of (100). A first impurity region 24 (hereinafter referred to as a source region) and a second impurity region 26 (hereinafter referred to as a drain region) are provided apart from each other in the upper surface (front surface) region of the substrate 10. . Further, a channel formation scheduled region 27 is formed between the source region 24 and the drain region 26.
[0029]
A first insulating film 12a (hereinafter referred to as a tunnel oxide film) and a first conductor layer 14a are formed on the substrate 10 in a region including the channel formation scheduled region 27 and a part of the source region 24 and the drain region 26. (Hereinafter referred to as a floating gate electrode), a second insulating film 21a (hereinafter referred to as an interlayer insulating film), and a second conductor layer 22a (hereinafter referred to as a control gate electrode) are laminated. It is provided.
[0030]
The floating gate electrode 14a is made of polysilicon containing germanium atoms for reducing the crystal diameter, and the concentration of germanium atoms at this time is a minimum of 1 × 10 6.^{twenty one}Atom / cm^Three It is as. Here, the small crystal diameter means a crystal diameter to such an extent that the surface of the first conductor layer is a plane that can be regarded as substantially flat. The interlayer insulating film 21a has a three-layer structure, and a lower oxide film 16a, a nitride film 18a, and an upper oxide film 20a are formed from the floating gate electrode 14a toward the control gate electrode 22a. ing.
[0031]
[No.1Explanation of Method of Forming EEPROM of Invention]
  Next, referring to (A) to (C) of FIG. 2, (A) to (C) of FIG. 3, and (A) to (B) of FIG.1The method for forming the EEPROM of the invention will be described.
[0032]
First, the p-conductivity type semiconductor substrate already described is used as the substrate 10. After the substrate 10 is cleaned using any suitable cleaning liquid to remove impurities adhering to the substrate 10, the cleaned substrate 10 is immediately placed in an optional suitable oxide film formation reactor (not shown). Carry in.
[0033]
Then, using a chemical vapor deposition (CVD) apparatus (not shown), oxygen (O₂ ) A gas is introduced and a treatment is performed at a heating temperature of about 900 ° C. for 20 minutes to form a first insulating film 12 (hereinafter referred to as a tunnel oxide film) on the substrate 10 (FIG. 2A). . This tunnel oxide film 12 is made of SiO.₂ The film thickness is about 110 mm, for example.
[0034]
Next, the structure of FIG. 2A is immediately carried into a rapid thermal processing-chemical vapor deposition apparatus (RTP-CVD apparatus) (not shown). The RTP-CVD apparatus used here is substantially the same as the apparatus (model number: Epsilon 1 manufactured by ASM) disclosed in Document II (“Monthly Semiconductor World, October 1990, P. 98-102”). Is used.
[0035]
In an embodiment of the present invention, the first conductor layer 14 (hereinafter, n⁺ This is referred to as a conductive floating gate electrode preliminary layer. ) Is formed (FIG. 2B). Here, the floating gate electrode preliminary layer 14 is also referred to as a Si—Ge mixed crystal film. The method for forming the Si—Ge mixed crystal film 14 at this time is as follows.
[0036]
In the RTP-CVD reactor, for example, disilane (Si₂ H₆ ) Gas about 30 sccm, germane (GeH_Four Gas) about 20 ccm and arsine (AsH)_Three ) About 0.5 sccm of gas is introduced, the substrate temperature is set at, for example, 590 ° C., and processing is performed for about 90 seconds. At this time, the pressure in the furnace is, for example, 0.9 Torr. In this way, arsenic (As) doped Si on the tunnel oxide film 12_1-x -Ge_x A mixed crystal film 14 is formed (FIG. 2B). At this time, Si_1-x -Ge_x The impurity concentration of arsenic (As) atoms in the mixed crystal film 14 is 1 × 10^{twenty one}Atom / cm^Three To the extent.
[0037]
Si_1-x -Ge_x X in the mixed crystal film 14 is a numerical value representing the composition and is set to a value between 0.05 <x <0.4. Here, Si_1-x -Ge_x The film thickness of the mixed crystal film 14 is about 100 nm (nanometers). The substrate temperature at this time is preferably set to a temperature in the range of 550 ° C. to 750 ° C.
[0038]
  Si formed by such a method_1-x-Ge_xThe mixed crystal film 14 is made up of a large number of fine crystals, and Si_1-x-Ge_xThe surface of the mixed crystal film 14 is a flat surface that can be regarded as a substantially flat surface. In the first embodiment, the example in which the arsine gas is introduced simultaneously with the disilane gas and the germane gas has been described. However, the present invention is not limited to this example.As the second invention,For example, as described below, Si_1-x-Ge_xArsenic may be doped into the mixed crystal film.
[0039]
Heat treatment is performed in the furnace using a mixed gas of disilane gas and germane gas, and Si is formed on the tunnel oxide film 12._1-x -Ge_x A mixed crystal film 14 is formed. Thereafter, the arsenic (As) atoms are replaced by Si using any suitable method._1-x -Ge_x Doping is performed in the mixed crystal film 14.
[0040]
Next, the structure shown in FIG. 2B is carried into an oxide film formation reactor (not shown).
[0041]
After that, oxygen (O₂ ) Supply gas and perform treatment for about 5 minutes at a heating temperature of 1000 ° C., for example._1-x -Ge_x A second insulating film 16 (hereinafter referred to as a lower oxide film) is formed on the upper surface (surface) of the mixed crystal film 14 ((C) of FIG. 2). At this time, the thickness of the lower oxide film 16 is set to about 5 nm.
[0042]
Next, a nitride film 18 is formed on the lower oxide film 16 by using, for example, a low pressure CVD (also referred to as LPCVD) method (FIG. 3A). The conditions for forming the nitride film 18 at this time are as follows. And
[0043]
Silane (SiH) in the reactor_Four ) Gas and ammonia (NH_Three ) Gas mixed with the gas (for example, the mixing ratio is 3: 1 (volume ratio)), for example, the processing is performed at a heating temperature of 700 ° C. for about 20 minutes to form a film thickness of about 10 nm on the lower oxide film 16. Nitride film 18 (Si_Three N_Four Film).
[0044]
Thereafter, an upper oxide film 20 is formed on the surface of the nitride film 18 formed in FIG. 3A using a pyrological (combustion) method (FIG. 3B). At this time, the thickness of the upper oxide film 20 is set to about 3 nm. Here, the lower oxide film 16, the nitride film 18, and the upper oxide film 20 are collectively referred to as an interlayer insulating film 21.
[0045]
Next, the control gate electrode preliminary layer 22 is formed on the upper oxide film 20 using any suitable method to obtain the structure shown in FIG. The material of the control gate electrode spare layer 22 is, for example, polysilicon.
[0046]
Next, a part of the control gate electrode preliminary layer 22 is masked by using any suitable method, and parts other than the part masked by the photoetching and dry etching methods are removed from the control gate electrode preliminary layer 22 to the surface of the substrate 10. The structure shown in FIG. 4 (A) is obtained by etching away until is exposed. At this time, the portions remaining on the substrate 10 are taken as a control gate electrode 22a, an upper oxide film 20a, a nitride film 18a, a lower oxide film 16a, a floating gate electrode 14a, and a tunnel oxide film 12a.
[0047]
Next, the tunnel oxide film 12a, the floating gate electrode 14a, the interlayer insulating film 21a, and the control gate electrode 22a are masked using, for example, a positive resist material (not shown), and ions are implanted into the surface of the substrate 10. Then, an activation process is performed to form n on the surface of the substrate 10.⁺ A conductive type source region 24 and drain region 26 are formed (FIG. 4B). The EEPROM is completed through these steps.
[0048]
[Description of Method for Forming EEPROM of Third Invention]
Next, a method for forming the EEPROM of the third invention will be described with reference to FIGS.
[0049]
  Until the tunnel oxide film 12 is formed on the substrate 10,1It is the same as the process of the invention. Therefore, detailed description is omitted.
[0050]
In this embodiment, a first conductor layer 13 made of polysilicon is formed on the tunnel oxide film 12 (FIG. 5A). Hereinafter, the first conductor layer 13 is referred to as a polysilicon layer. At this time, the thickness of the polysilicon layer 13 is set to about 0.1 μm.
[0051]
Next, germanium ions (Ge) are implanted into the polysilicon layer 13 by ion implantation.⁺ ) (FIG. 5B). At this time, the concentration of germanium (Ge) atoms is set to a minimum of 1 × 10^{twenty one}Atom / cm^Three And
[0052]
Next, an impurity element is doped using any suitable method (FIG. 5C). The impurity element at this time is, for example, phosphorus (P), and the concentration of phosphorus is 1 × 10.^{twenty one}Atom / cm^Three To the extent.
[0053]
Thereafter, in order to adjust crystal distortion generated during ion implantation, the heating temperature is set to about 560 ° C., and annealing is performed for about 40 minutes. However, it is necessary to change the heating temperature and time depending on the Ge concentration.
[0054]
  Subsequent steps are1Since it is the same as the process after (C) process of FIG. 2 of invention, detailed description is abbreviate | omitted.
[0055]
Next, a grain diameter in the floating gate electrode with respect to the impurity concentration will be described with reference to FIG.
[0056]
FIG. 6 is a diagram showing the relationship between the crystal (grain) diameter and the impurity concentration in the floating gate. In the figure, curve I represents the crystal (grain) diameter when the floating gate electrode is doped with phosphorus (P) (conventional example), and curve II represents the floating gate electrode in which Ge is introduced into the polycrystalline Si of this embodiment. The grain diameter when phosphorus is doped inside is shown. The sample used for the measurement at this time is a polysilicon floating date electrode doped with phosphorus in the conventional example. In this example, after implanting germanium ions into the floating gate electrode by an ion implantation method, phosphorus is implanted. A doped floating gate electrode is used. And it is the value which performed the heat processing (950 degreeC, 1 hour) in nitrogen gas about each sample, and measured the grain diameter using the Nomarski optical microscope.
[0057]
As can be understood from FIG. 6, in the conventional curve I, the crystal diameter grows larger as the impurity concentration of phosphorus increases. In particular, the phosphorus concentration is 1 × 10²⁰Atom / cm^Three The grain diameter is about 0.42 μm and the phosphorus concentration is 5 × 10.²⁰Atom / cm^Three Then, the grain diameter is about 0.6 μm. Furthermore, the phosphorus concentration is 1 × 10^{twenty one}Atom / cm^Three Then, the grain diameter is about 0.95 μm.
[0058]
On the other hand, in this example, the phosphorus concentration is 1 × 10.¹⁹Atom / cm^Three In this case, the grain diameter is almost the same as that of the conventional example (curve I), but the phosphorus concentration is 1 × 10.^{twenty one}Atom / cm^Three Then, the grain diameter becomes rather small. That is, in the embodiment of the present invention, the concentration of phosphorus is 6 × 10¹⁹Atom / cm^Three The grain diameter is about 0.2 μm and the phosphorus concentration is 5 × 10²⁰Atom / cm^Three Then, the grain diameter is about 0.15 μm. Furthermore, the concentration of phosphorus is 1 × 10^{twenty one}Atom / cm^Three Then, the grain diameter is about 0.14 μm. The following can be considered from the results of FIG.
[0059]
In the conventional floating gate electrode doped with phosphorus, a grain boundary is generated in the polysilicon crystal, and high-concentration phosphorus atoms are segregated at the crystal grain boundary, so that the grain diameter increases in proportion to the phosphorus concentration of impurities.
[0060]
In contrast, in this embodiment, since Ge atoms are introduced into the polycrystalline Si, the polycrystalline Si forms a Si—Ge mixed crystal film. For this reason, germanium atoms have a larger crystal radius than silicon atoms, which increases lattice distortion in the silicon lattice. Therefore, since the thickness of the Si—Ge mixed crystal film does not grow beyond the critical thickness, the size of the polysilicon crystal (grain size) is considered to be smaller than that of the conventional polysilicon alone.
[0061]
In the above-described embodiments of the present invention, an example having a floating gate has been described. However, even when a gate electrode of a field effect transistor (MOSFET) having no floating gate is used, an oxide generated at the gate electrode / oxide film interface is used. It is also considered effective as a method for reducing ridge (Oxide Ridge).
[0062]
In this embodiment, an oxidation forming furnace is used as an apparatus for forming a lower oxide film. However, the present invention is not limited to this apparatus, and an RTP-CVD apparatus may be used.
[0063]
  The second1In the invention, Si_1-x-Ge_xDisilane gas was used as the silicon-containing group IV hydrogen gas when forming the mixed crystal film, and germane gas was used as the germanium-containing group IV gas. However, the gas is not limited to these gases. Silane (SiH_FourGas, methylsilane (Si (CH_Three) H_Three) Gas and trisilane (Si_ThreeH₈) One gas selected from among gases is used, while germanium fluoride (GeF) gas, germanium difluoride (GeF) is used instead of germane gas.₂) Gas and germanium tetrafluoride (GeF)_Four) One gas selected from gases may be used.
[0064]
  This second1In the invention, as the dopant gas, arsine (AsH_Four) Gas is used, but is not limited to this gas. For example, phosphine (PH_Three) Gas and diborane (B₂H₆) Gas may be used.
[0066]
【The invention's effect】
  As is clear from the above explanation,First1 andIn the forming method of the second invention,When forming the floating gate electrode,Since the Si—Ge mixed crystal is used, the crystal diameter of the polysilicon can be reduced. For this reason,Oxide film as tunnel oxide filmEven if a lower oxide film is formed on the polysilicon, the crystal diameter of polysilicon does not increase.Floating gate electrodeNo grain boundaries are generated inside. For this reason,Floating gate electrodeWhenOxide film as tunnel oxide filmInterface withFloating gate electrodeWhenLower oxide filmSince the interface with the surface is flattened, the film thickness is uniform and does not contain impurity elements.Oxide film and lower oxide film as tunnel oxide filmCan be formed. For this reason, the data retention characteristic of the EEPROM is remarkably improved.
[0067]
  Also,Si on the oxide film as the tunnel oxide film _1-x ―Ge _x Heat treatment for mixed film formationRapid thermal chemical vapor deposition (R)TPSince the (-CVD) apparatus is used, the wafer can be selectively heated in a short time. In addition, since the chamber of this device is small and the wafer can be carried into the furnace at a low temperature, there is little air entrainment, high purity and high quality.Si _1-x ―Ge _x Mixed filmCan be formed.
[0068]
  In the forming method of the third invention,For floating gate electrode on oxide film to be tunnel oxide filmPolysiliconTheAfter formingThe minimum concentration of germanium atoms in the floating gate electrode is 1 × 10 ^{twenty one} Atom / cm ^Three PolysiliconGe ions are implanted by ion implantation. after that,Impurity concentration in floating gate electrode is 5 × 10 ²⁰ Atom / cm ^Three Polysilicon to make the aboveDoping impurity elements inside,PolysiliconAnneal. For this reason, since the Ge ion atom is implanted into the polysilicon, the polysilicon crystal diameter can be reduced.PolysiliconThe inside grain boundary can be suppressed. Therefore,PolysiliconWhenOxide film to be tunnel oxide filmInterface withPolysiliconWhenInterlayer dielectric underlayer oxide filmAs a result, the data retention characteristic of the EEPROM is improved.
[Brief description of the drawings]
[Figure 1]BookIt is principal part sectional drawing of the non-volatile semiconductor memory device of invention.
FIG. 2 (A) to (C)1 andIt is process drawing provided in order to demonstrate the manufacturing process of EEPROM of 2nd invention.
FIGS. 3A to 3C are process diagrams for explaining the manufacturing process subsequent to FIG. 2; FIGS.
4A to 4B are process diagrams for explaining the manufacturing process subsequent to FIG. 3;
FIGS. 5A to 5C are process diagrams provided to explain a manufacturing process of the EEPROM of the third invention; FIGS.
FIG. 6 is a diagram for explaining the size of the crystal diameter with respect to the impurity concentration of phosphorus according to an embodiment of the present invention and a conventional example.
FIGS. 7A to 7B are cross-sectional views of the EEPROM before and after forming a conventional lower oxide film. FIGS.
FIG. 8 is a cross-sectional view of main parts of a conventional nonvolatile semiconductor memory device.

Claims (6)

A semiconductor substrate of a first conductivity type, a source region and a drain region provided apart near the surface of the semiconductor substrate, the semiconductor substrate on the formed tunnel oxide film, formed on the tunnel oxide film A non-volatile semiconductor comprising a floating gate electrode, an interlayer insulating film formed on the floating gate electrode and composed of a lower oxide film, a nitride film, and an upper oxide film , and a control gate electrode formed on the interlayer insulating film In a method for forming a storage device,
On the oxide film to be the tunnel oxide film, a heat treatment was performed using a mixed gas of a dopant gas to dope the silicon-containing group IV hydrogen-based gas and the germanium-containing group IV-based gas and impurity elements, wherein the floating gate electrode 5 × 10 ²⁰ atoms / cm ³ or more Si _1-x -Ge x mixed Gomaku (x impurity concentration a numerical value representing the composition 0.05 <x <0.4 value between And a process of forming as
The lower oxide layer of the interlayer insulating film, a step of forming by thermally oxidizing the surface of the floating gate electrode,
A method for forming a nonvolatile semiconductor memory device, comprising: A first conductivity type semiconductor substrate, a source region and a drain region provided in the vicinity of the surface of the semiconductor substrate, a tunnel oxide film formed on the semiconductor substrate, and formed on the tunnel oxide film A non-volatile semiconductor comprising a floating gate electrode, an interlayer insulating film formed on the floating gate electrode and composed of a lower oxide film, a nitride film, and an upper oxide film, and a control gate electrode formed on the interlayer insulating film In a method for forming a storage device,
On the oxide film as the tunnel oxide film, a heat treatment was performed using a mixed gas of a silicon-containing group IV hydrogen-based gas and the germanium-containing group IV-based gas, the floating gate electrode Si _1-x -Ge _x mixed film (x takes a value between a numerical value 0.05 <x <0.4, which represents the composition.) so as to form as an impurity element to said Si _1-x -Ge x mixed film A step of doping the floating gate electrode to have an impurity concentration of 5 × 10 ²⁰ atoms / cm ³ or more by doping ;
Forming the lower oxide film of the interlayer insulating film by thermally oxidizing the surface of the floating gate electrode;
A method for forming a nonvolatile semiconductor memory device, comprising: The method for forming a nonvolatile semiconductor device according to claim 1 ,
Nonvolatile semiconductor memory characterized in that the dopant gas is one gas selected from the group consisting of arsine (AsH ₄ ) gas, phosphine (PH ₃ ) gas and diborane (B ₂ H ₆ ) gas. Device forming method. The method for forming a nonvolatile semiconductor memory device according to claim 1,
Silane the silicon-containing group IV hydrogen-based gas (SiH _4), disilane (Si ₂ H _6), methylsilane _{(Si (CH 3) H 3} ) and trisilane selected from among gas group (Si ₃ H ₈₎ 1 One of the gas, germane said germanium-containing group IV-based gas (GeH _4), germanium tetrafluoride (GeF _4), selected from among a gas group difluoride germanium (GeF ₂₎ and germanium fluoride (GeF) A method for forming a nonvolatile semiconductor memory device, wherein one gas is used. In the formation method of the non-volatile semiconductor device according to any one of claims 1 to 3 ,
The heat treatment, rapid thermal processing - chemical vapor deposition method for forming (RTP-CVD) nonvolatile semiconductor memory device which is characterized in that using the apparatus. A semiconductor substrate of a first conductivity type, a source region and a drain region provided apart near the surface of the semiconductor substrate, the semiconductor substrate on the formed tunnel oxide film, formed on the tunnel oxide film Nonvolatile semiconductor memory comprising a floating gate electrode, an interlayer insulating film formed on the floating gate electrode and composed of a lower oxide film, a nitride film, and an upper oxide film, and a control gate electrode formed on the interlayer insulating film In the method of forming the device,
(A) a first step of forming polysilicon for the floating gate electrode by performing heat treatment on the oxide film to be the tunnel oxide film using a silicon-containing group IV hydrogen-based gas;
(B) After the first step, a second step of implanting germanium ions into the polysilicon by an ion implantation method so that the concentration of germanium atoms in the floating gate electrode is a minimum of 1 × 10 ²¹ atoms / cm ^3. When,
(C) a third step of doping an impurity element into the polysilicon after the second step so that the impurity concentration in the floating gate electrode is 5 × 10 ²⁰ atoms / cm ³ or more ;
(D) a fourth step of annealing the polysilicon containing the germanium ions and the impurity element after the third step;
(E) after it said fourth step, to form a lower oxide film of the interlayer insulating film, a fifth step you thermally oxidizing the surface of said polysilicon,
Forming method of the nonvolatile semiconductor memory device, characterized in that it comprises a.

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