JPH03266471A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enhance a semiconductor device of this design in reliability by a method wherein crystal grains whose grain diameter is 10 times as larger as the thickness of a silicon film are contained in the silicon film, and the phosphorus or arsenic concentration in the silicon film is as specified. CONSTITUTION:A field oxide film 102 is formed on an N-type Si substrate 101 whose crystal face orientation is (100), and an Si film 103 is deposited thereon while doping with phosphorus. The Si film 103 is kept in an amorphous state immediately after it is deposited. In succession, an SiO2 film 104 is formed on the surface of the Si film, and an Si film 105 is deposited under the same condition with the Si film 103 and thermally treated in a nitrogen atmosphere to be polycrystallized and to activate impurities. At this point, crystal grains whose grain diameter is 10 times as large as the thickness of a silicon film are contained in the silicon film, and phosphorus or arsenic contained in the silicon film concerned is set higher than 8X10<20>cm<-3> but lower than 2X10<21>cm<-3> in concentration. By this setup, an LSI device can be improved in reliability.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an MO3 type semiconductor device having high breakdown voltage and high reliability, and a method for manufacturing the same.

[Conventional technology]

One of the technologies that has supported the development of today's LSI is polycrystalline silicon (Si) electrode/wiring formation technology. Since the polycrystalline Si film has extremely high resistance immediately after film deposition, it is doped with impurities by ion implantation or thermal diffusion in subsequent steps to obtain conductivity. In MOS type nonvolatile memories, etc., the surface of the first polycrystalline Si film formed by the above method is thermally oxidized to form an insulating film made of silicon dioxide (S i O2), and then a second insulating film is formed on this insulating film. The second polycrystalline Si film is formed by the same method as the first polycrystalline Si film to constitute a transistor or a capacitor. Related to this type of semiconductor device manufacturing method, IEICE Technical Research Report No. 18
4, 1985, pages 43 to 48.

[Problem to be solved by the invention]

However, there was a problem in that the M-edge breakdown voltage of the thermal oxide film of polycrystalline S1 formed by the above-mentioned conventional technique was significantly inferior to that of the thermal oxide film on a single-crystal Si substrate. When a leakage current of 10-"A/cm" occurs, the dielectric strength voltage is at most 8.8 MV/cm, and the original oxide film is
Interlayer lf between floating gate and control gate of E P ROM! ! When used on the lamina, there is a remarkable #!
There was a bad relationship. In order to improve the reliability of EEF ROM, it is necessary to use the dielectric strength voltage of the native oxide film of 9°5 MV.
/ cm or more is desirable. In addition, in the conventional example, the phosphorus concentration in the Si film is 7×1020
There is also the disadvantage that when the voltage exceeds cm-3, the dielectric strength deteriorates rapidly. This is thought to be due to the following two reasons. ■Electric field concentration on the unevenness existing at the polycrystalline Si/S i○2 interface. There are many irregularities on the surface of polycrystalline Si after film deposition. The height of these irregularities is about 10 nm for polycrystalline Si with a film thickness of 200 nm, which is widely used in ordinary LSIs.As a result of the electric field being locally concentrated on these irregularities, the S
Dielectric breakdown of the iO2 film occurs. In order to reduce this electric field concentration to a practically negligible level, the height of the above-mentioned irregularities must be set to 5n.
It was necessary to keep it below m. Furthermore, due to the unevenness, polycrystalline Si may be left behind in the 5in2 film without being oxidized, causing current leakage. To solve this problem, for example, the deposition of the Si film was performed at 550'C.
A method has also been proposed in which the unevenness on the surface of the Sl film is reduced by performing the process at a lower temperature than conventionally in the range of 75° C. and making the Si film in an amorphous state during film deposition. However, simply by smoothing the surface of the polycrystalline S1 film, a high dielectric strength voltage could not be obtained. ■Incorporation of impurities into the oxide film. Impurities in the polycrystalline Si film, particularly impurities segregated at grain boundaries, are taken into the 5in2 during oxidation, resulting in generation of levels and an increase in leakage current. Note that in nonvolatile memories, it is also necessary to consider the influence of impurities in polycrystalline silicon on the underlying gate oxide film. However, in the prior art, no consideration was given to this problem, and the impurity concentration in the polycrystal was constant in the film thickness direction. An object of the present invention is to form an oxide film on a polycrystalline Si film with a high dielectric strength equivalent to that of a thermal oxide film formed on a single-crystalline Si substrate, and to provide a highly reliable semiconductor device and its manufacturing method. It is about providing.

[Means to solve the problem]

The above object is to provide a semiconductor device including a silicon film containing impurities, wherein the silicon film contains crystal grains with a grain size of at least 10 times the film thickness, and the phosphorus or arsenic concentration in the silicon film is This is achieved by setting the film density to be 8 x 1020 cm-'' or more and 2 x 102 L cm-' or less. Further, the above-mentioned film formation can be achieved by, for example, the following steps: (1) forming the first Si film; (2) The deposition temperature of the first Si film is 550° C. or less, and the deposition is carried out in an amorphous state. (3) The first (7) The concentration of phosphorus in the Si film is 8XI.
This is achieved by setting Q"cm-' or more and 2 x 1020ctm-' or less.

[Effect]

According to the above manufacturing method, the unevenness of the interface between the first Si film and the SiO2 film and the interface between the SiO2 film and the second Si film is 5 nm or less, and is extremely smooth. Therefore, there is no local electric field concentration caused by the unevenness of the polycrystalline Si film, which occurs in the conventional technology.Furthermore, the crystal grain size of the present Si film is about 10 times larger than that of the conventional polycrystalline Si film.
Since the film is deposited while doping with phosphorus, the concentration of phosphorus that segregates at grain boundaries is small. Therefore, due to oxidation, S
The amount of phosphorus incorporated into the iO□ film is reduced. Therefore, polycrystalline S x S x O with high dielectric strength
It becomes possible to form a z-polycrystalline Si structure.

【Example】

Example 1 First, a first example of the present invention will be described in detail with reference to FIG. This implementation was created using the following steps. First, an n-type S with a resistivity of 0.100m and a plane orientation of (100)
A field oxide film 102 was formed on the surface of the i-substrate 101 by a well-known selective oxidation technique. Next, the first Si film 103 is coated with disilane (
SIZHG) and phosphine (PH, ) were deposited to a thickness of 200 nm at 525° C. while doping with phosphorus by low pressure chemical vapor deposition (LPCVD). Si film 103
is amorphous immediately after film deposition. When depositing the Si film 103, nitrogen was used as a diluent gas. This is because since the flow rate of PH is small, it can be easily controlled by using diluent gas. Furthermore, the use of a diluent gas has the effect of improving the uniformity of film thickness and concentration among wafers within the same batch. In addition to nitrogen, an inert gas such as helium or argon may be used as the diluent gas. This Si film 103 was processed using well-known lamination techniques and dry etching techniques to form a first electrode. Next, 20 nm of S was deposited on the surface of the Si film using a thermal oxidation method.
x Oz till O4 was formed. Oxidation is 950
The experiments were carried out at a temperature of 0.degree. C. in an argon gas atmosphere containing 10% oxygen. Note that during this oxidation, the first Si film transitions from an amorphous state to a polycrystalline state, and at the same time, the activation of impurities is completed. Subsequently, a second Si layer with a thickness of 200 nm is
A film 105 was deposited under the same conditions as the first Si film 103. Then, heat treatment was performed in a nitrogen atmosphere at 650° C. for 20 minutes to polycrystallize the second Si film and activate impurities. Thereafter, the second Si film was processed to form a second electrode. FIG. 1 shows the relationship between the dielectric strength voltage of the MO3 type capacitor formed by the above method and the phosphorus concentration in the first Si film. Here, the dielectric strength voltage was evaluated by the applied electric field strength when a leakage current of 10-"A/cm2 occurred. According to this method, the dielectric strength voltage can be accurately measured without the influence of voltage drop. In the measurement, a positive voltage was applied to the second electrode 105 using the first electrode 103 as a reference.In this case, the phosphorus concentration in the second Si film was 8x1020c.
It was set as m-'. The dielectric strength improves as the phosphorus concentration in the first Si film increases, and when the phosphorus concentration increases to 7X1020 cm-'
10.0MV/cm, and conventionally about 8.8MV/cm
However, S formed on a single crystal Si substrate
It showed a value equivalent to that of the iO2 film. The feature of the present invention is that the phosphorus concentration is further increased to 8×IQ”cm.
Even if the voltage exceeds -', the dielectric strength voltage should not deteriorate. This was not possible with the prior art. Note that the phosphorus concentration in the first Si film is 2X1020am""
If this is the case, the segregation of phosphorus cannot be ignored, making it unsuitable for practical use. Even when nitrogen was used instead of argon as the diluent gas when oxidizing the first Si film 103, the same results as in FIG. 1 were obtained. However, the dielectric strength voltage was smaller than that in FIG. 1 for each phosphorus concentration value. Therefore, as the diluting gas, an inert gas such as argon or neon is more desirable than nitrogen. For comparison, FIG. 1 also shows the results of the conventional method. Conventional method (a) uses SiH4 as the raw material gas and the temperature is 630°C.
That is, after depositing a first Si film with a thickness of 200 nm in a polycrystalline state and then forming a 10 m thick SiO2 film by LPCVD, phosphorus ions are implanted at 40 keV to form a SiO2 film.
After removing 2 membranes. Oxidation was carried out at a temperature of 950° C. in an argon atmosphere containing 10% oxygen. Conventional method (b) is
The Si film deposited in conventional method (a) was deposited at 525° C., that is, in an amorphous state. In addition, conventional method (a), conventional method (
b) In both cases, the deposition of the second 81 film was according to the method of the invention. As is clear from the figure, regardless of whether the first Si film is deposited in a polycrystalline or amorphous state, if phosphorus doping is performed after the film is deposited, a high dielectric breakdown voltage cannot be obtained. The highest value was 8.8MV/cm. Also, Si
When the phosphorus concentration in the film exceeded 7.times.10.sup.20 cm.sup.-', a rapid deterioration in breakdown voltage occurred. According to this embodiment, using 5i2HG and PH3, 8
By depositing the first and second Si films in an amorphous state while doping X 1020 cm or more of phosphorus, the effect of improving the dielectric breakdown voltage of the SiO film between the Si electrodes is obtained. be. Note that the same effect can be obtained even if a film formed by the CVD method is used as the 5in2 film. Embodiment 2 FIG. 3 shows a schematic cross-sectional view of a second embodiment of the present invention. This example is a batch erasing type EEPROM, which was created according to the procedure shown below. First, p-type Si with resistivity 10ΩCm and plane orientation (100)
A field oxide film 202 was formed on the surface of the substrate 201 by a well-known selective oxidation technique. Next, the Si substrate was oxidized in an oxygen atmosphere to form a gate oxide film 203 having a thickness of 15 m. Next, using Si, H, and PH as raw material gases, 52
A first Si film 204 was deposited to a thickness of 200 nm at 5°C. Si
The phosphorus concentration in the film is lXl0"cm-'. Next, the first Si film 204 was processed to form a floating gate using a known technique. Next, the first Si film 204 was processed at a temperature of 950°C for 10
The first Si film 2 is grown in an argon atmosphere containing % oxygen.
The surface of 04 was oxidized to form a 20 m thick Si○2 film 205. Subsequently, a second Si film 206 is deposited to a thickness of 200 nm in the same manner as the first Si film, and then a second Si film 206 is deposited using a known technique.
The i-film was processed and used as a control gate. Thereafter, phosphorus and arsenic ions are sequentially implanted to form source and drain regions 207. A glabellar oxide film 208 was formed by the LPCVD method, a connection hole was opened in this, and an Al film 209 was deposited to form an arched wiring. The dielectric strength voltage of the Si*2 film 205 between the floating gate 2o4 and the control gate 206 of the EEPROM formed by this method was improved by more than 25% compared to the conventional method. Along with this, the charge retention time of the floating gate has been improved by an order of magnitude. In this example, when depositing the first Si film 204, the phosphorus concentration in the film was varied from O to I as the film deposition progressed.
Experiments were also conducted in which the temperature was gradually increased to X 1020 cm-'. In this case, S i O, I! of the film 205!
Although the edge seat pressure was the same as in the above method, the withstand voltage of the gate oxide film 203 was improved by 20%, and the variation in threshold voltage during erasing was reduced from 2V to 1V. According to this embodiment, the floating gate and control gate of the bulk erase type EEPROM are deposited in an amorphous state using 5i2HG and PH while doping with phosphorus, thereby significantly improving charge retention characteristics. It has the effect of improving. In Examples 1 and 2, when depositing the first and second Si films, phosphine was used as the doping gas and phosphorus was introduced as an impurity, but the same result could be obtained even if arsine was used as the doping gas and arsenic was introduced. The effect of this can be obtained. Effect of the Invention 1 According to the present invention, a Sin film having a high dielectric strength voltage can be formed on a polycrystalline Si film. This makes it possible to improve the reliability of the LSI device. Furthermore, since the conventional thermal diffusion and ion implantation are no longer necessary, the LSI device manufacturing process can be greatly simplified.

[Brief explanation of drawings]

FIG. 1 is a curve diagram showing the relationship between impurity concentration in a Si film of a semiconductor device and dielectric strength voltage in an embodiment of the present invention and a conventional example, and FIGS. FIG. 2 is a cross-sectional view of the device. Explanation of symbols 101, 201-Si substrate, 102, 202-field oxide film, 203 mountain gate oxide film, 103.20
4...First Si film, 104.205...SiO2 film, 105.206-...Second (7) Si film, 207
...Diffusion layer, 208...Interlayer oxide film, 209...
・A1 membrane. Figure 1 Figure 2

Claims (1)

[Claims] 1. In a semiconductor device comprising a silicon film containing impurities, the silicon film contains grains with a particle size of at least 1 film thickness.
0 times or more crystal grains, and the phosphorus or arsenic concentration in the silicon film is 8 x 10^2^0 cm^-^3 or more,
A semiconductor device characterized in that the size is 2×10^2^1 cm^-^3 or less. 2. The semiconductor device according to claim 1, further comprising an insulating film made of silicon dioxide formed on the silicon film. 3. The semiconductor device according to claim 2, wherein a second silicon film is formed on the insulating film. 4. The semiconductor device according to claim 2 or 3, wherein the unevenness of the interface between the silicon film and the insulating film is 5 nm or less. 5. A semiconductor device comprising a polycrystalline silicon thermal oxide film having a dielectric strength of 9.5 MV/cm or more when a leakage current of 10^-^2 A/cm^2 occurs. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a MOS type nonvolatile memory. 7. The semiconductor device according to claim 1, wherein the impurity concentration in the lower region of the silicon film is lower than the impurity concentration in the interior or upper region. 8. A method for manufacturing a semiconductor device in which a first silicon film is deposited on a semiconductor substrate having an arbitrary step while doping with impurities, and then an insulating film made of silicon dioxide is formed on the first silicon film. A semiconductor device characterized in that the first silicon film is deposited by a low pressure chemical vapor deposition method using a source gas containing disilane or trisilane and phosphine at a temperature of 450° C. or higher and 550° C. or lower. manufacturing method. 9. Manufacturing a semiconductor device according to claim 8, wherein a second silicon film is deposited on the insulating film using the same type of raw material gas and in the same temperature range as that used for depositing the first Si film. Method. 10. Claims 8 to 9, characterized in that one or both of the first and second Si films are deposited using arsine as a raw material gas instead of phosphine.
A method of manufacturing the semiconductor device described above. 11. Claim 8, wherein the insulating film is a silicon dioxide film formed by oxidizing the first silicon film.
10. The method of manufacturing a semiconductor device according to 9. 12. The method of manufacturing a semiconductor device according to claim 8, wherein a portion of the oxidation of the first silicon film is performed in an oxygen atmosphere diluted with an inert gas such as argon or neon. 13. The method of manufacturing a semiconductor device according to claim 8, wherein the insulating film is a silicon dioxide film formed by chemical vapor deposition.