JP3643096B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
[Industrial application fields]
Invention relates to a method for manufacturing a thin film semiconductor equipment which is integrated disclosed herein. The invention disclosed herein relates to a method for manufacturing an active matrix type liquid crystal display equipment of.
[0002]
[Prior art]
Conventionally, an active matrix type liquid crystal display device is known. This has a configuration in which a thin film transistor is arranged on each of the pixel electrodes arranged in units of several hundreds of thousands on a glass substrate. The thin film transistor disposed in each of the pixel electrodes has a function of controlling electric charges entering and exiting each pixel electrode.
[0003]
In addition, a configuration in which a thin film transistor circuit (referred to as a driver circuit) for driving a thin film transistor disposed on a pixel electrode is integrated on the same glass substrate is also known. This is called a peripheral integrated active matrix type.
[0004]
[Problems to be solved by the invention]
In the case of manufacturing such an active matrix liquid crystal display device, there is a phenomenon that some of thin film transistors integrated on a glass substrate become defective in operation.
[0005]
As a result of intensive studies on this problem, the present inventors have obtained the following findings.
[0006]
When an integrated semiconductor device such as an active matrix liquid crystal display device is manufactured, film formation by sputtering or plasma etching is used by plasma CVD in forming an insulating film or wiring.
[0007]
FIG. 3 shows an approximate relationship between the ion energy (relative value) and the number of ions (relative value) when plasma is generated. In general, there are not a few high-energy ions that cause plasma damage as shown by the oblique lines in FIG.
[0008]
On the other hand, there is a fact that an insulating film formed by plasma CVD or sputtering is not dense and has a low withstand voltage of about several tens of volts or less. In addition, since the substrate used is glass or quartz which is an almost perfect insulator, there is a problem that it is very easily charged.
[0009]
Here, a state as shown in FIG. 4 is considered. FIG. 4B shows one step in manufacturing a thin film transistor indicated by a symbol as shown in FIG. FIG. 4B shows a situation where an interlayer insulating film 31 is formed.
[0010]
Here, it is assumed that the interlayer insulating film 31 is formed by plasma CVD or sputtering. During this film formation, ions having high energy as shown in FIG. 3 naturally collide with the sample.
[0011]
Generally, there is no conduction between the source (S) electrode and the gate electrode (G). Therefore, although locally, a state in which the potential difference between the source (S) electrode and the gate (G) electrode instantaneously reaches several tens to several hundreds V during film formation is realized. There is.
[0012]
The source electrode and the gate electrode are disposed via the active layer 32 and the gate insulating film 30. On the other hand, as described above, the breakdown voltage of the gate insulating film 30 formed by the CVD method or the sputtering method is several tens of volts or less. Therefore, in the above situation, the gate insulating film 30 is electrically destroyed.
[0013]
As a result, the thin film transistor becomes defective. In order to solve this problem, when the insulating film 31 is formed, the source electrode and the gate electrode may be electrically short-circuited so as to be equipotential. However, in the state where the final operation is performed, the source electrode and the gate electrode should not be directly electrically short-circuited.
[0014]
Therefore, in the process shown in FIG. 4B, it is necessary to keep the source electrode and the gate electrode in an electrically shorted state until the final stage and to cut the source electrode and the gate electrode in the final stage. . However, such a process increases the number of processes. Increasing the number of processes is not preferable from the viewpoint of production yield and production cost.
[0015]
[Problems to be solved by the invention]
An object of the invention disclosed in this specification is to provide a technique for solving the problem of destruction of a semiconductor device in a process as illustrated in FIG. That is, it is an object of the present invention to provide a technique for preventing a semiconductor device being fabricated from being destroyed by a pulsed high potential applied from plasma (these high potentials are applied locally and instantaneously). . It is another object of the present invention to realize the above technique without adding a special manufacturing process.
[0016]
[Means for Solving the Problems]
One of the inventions disclosed in this specification includes a step of forming the first wiring 100 extending to the gate electrode 101 of the thin film transistor, as shown in FIG. Forming a first insulating film 206 on the wiring, forming a second wiring 102 connected to the source region 211 of the thin film transistor on the insulating film, and forming a second insulating film 206 on the second wiring. 2 and a step of forming a conductive pattern 214 on the second insulating film, and the first and / or the second wiring has a wiring pattern (FIG. 6). Alternatively, the first and / or the second wiring is cut (see FIG. 2E) simultaneously with the formation of the conductive pattern.
[0017]
In the above configuration, each insulating film may be formed in multiple layers.
[0018]
The structure of another invention is a manufacturing process of an active matrix circuit (see FIG. 1), as shown in FIG. Forming a first insulating film 206 on one wiring, forming a second wiring 102 orthogonal to the first wiring on the first insulating film,
A step of forming a second insulating film 207 on the second wiring, and a step of forming a conductive pattern 214 on the second insulating film, the first and / or the second A wiring pattern (see FIG. 6 or FIG. 7) is formed on the wiring, and the first and / or the second wiring is cut (see FIG. 2E) simultaneously with the formation of the conductive pattern. Features.
[0019]
According to another aspect of the invention, there is provided a step of forming a wiring constituting an active matrix circuit, a step of forming an insulating film on the wiring, and a step of forming a conductive pattern on the insulating film, The wiring has a wiring pattern, and the wiring having the wiring pattern is cut when the conductive pattern is formed.
[0020]
For example, when the wiring pattern as shown in FIG. 6 or 7 is formed on the short-circuit wiring shown by 100 or 114 in FIG. 1, the patterning of the pixel electrode 214 (see FIG. 2) is performed. In this case, the wiring pattern is separated from the wirings 101 and 102 arranged in a matrix.
[0021]
According to another aspect of the invention, there is provided a step of forming a wiring constituting an active matrix circuit, a step of forming an insulating film on the wiring, and a step of forming a conductive pattern on the insulating film, The wiring has a wiring pattern, and the wiring pattern is separated from the wiring constituting the active matrix circuit when the conductive pattern is formed.
[0022]
[Action]
In the process shown in FIG. 2, wirings 100 and 114 for connecting the wirings are formed, and each wiring is short-circuited before patterning of the pixel electrode.
[0023]
By doing so, it is possible to suppress a phenomenon in which a local high voltage is applied to the insulating film of the semiconductor device being manufactured in the plasma process. Further, by adopting a step of cutting this short-circuited portion when patterning the pixel electrode, it is possible to obtain a configuration in which the number of manufacturing steps is not particularly increased.
[0024]
In addition, by providing the wiring patterns 100 and 114 that connect the wirings with the wiring patterns shown in FIGS. 6 and 7, the pulse potential that propagates through the wirings 100 and 114 can be reduced or eliminated during the manufacturing process.
[0025]
【Example】
[Example 1]
In this embodiment, in the configuration of the active matrix type liquid crystal display device as shown in FIG. 1, the portions indicated by 103, 104, and 105 are removed by etching when patterning the pixel electrodes (not shown in FIG. 1). It is characterized by doing.
[0026]
In this embodiment, a process of separating the source wiring and the gate wiring arranged in the active matrix region and connected to each other in the final stage will be described.
[0027]
The pixel electrode is formed in the final process, and there is no processing process using plasma after the formation. Therefore, the pixel electrode formation process can be called the final process as a process using plasma.
[0028]
In this embodiment, before the pixel electrode is formed, for example, the gate wiring 101 and the source wiring 102 are connected by a short-circuit wiring indicated by 109 (this wiring is formed simultaneously with the formation of the gate wiring 101). Leave it in the state.
[0029]
That is, each wiring is in an electrically shorted state until the final process in which plasma is used. By doing so, it is possible to prevent the thin film transistor being fabricated from being destroyed by a high potential pulse induced by plasma.
[0030]
For example, the gate wiring 101 and the source wiring 102 are connected in a film forming process of the ITO film constituting the pixel electrode. That is, the gate electrode 110 and the source electrode 211 of the thin film transistor 106 are connected and have the same potential.
[0031]
Accordingly, even if a local high voltage is unavoidably applied, several tens of minutes are provided between the gate electrode 110 and the source electrode 211 (provided extending from the source wiring 102 in FIG. 1) of the thin film transistor 106. A situation where a voltage of V or higher is applied can be avoided.
[0032]
In the patterning process for forming the pixel electrode, the circuit can be completed by cutting (dividing) the wiring at a portion indicated by 103. In FIG. 1, regions indicated by 104 and 105 are shown as other portions where the wiring is cut.
[0033]
With the structure shown in FIG. 1, all of the gate wirings 101 and 112 and further the source wirings 102 and 108 can be made equipotential during the manufacturing process. And the problem which an unnecessary potential difference produces in the film-forming process and etching process using plasma and discharge can be solved.
[0034]
FIG. 2 is a cross-sectional view showing a part of the structure shown in FIG. 2 shows a cross-sectional manufacturing process diagram of the thin film transistor 106 in the configuration shown in FIG. 1 and a cross-sectional manufacturing process diagram indicated by AA ′ of the short-circuit wiring 100 extending from the gate wiring 101. And a manufacturing process diagram of a cross section indicated by BB ′ of the short-circuit wiring 114 extending from the source wiring 102 are shown on the same drawing. (Actually, the cross-section shown in FIG. 2 is not obtained as a whole.)
[0035]
The manufacturing process shown in FIG. 2 will be described below. First, as shown in FIG. 2A, a silicon oxide film (not shown) is formed on a glass substrate 201 as a base film. The configuration as shown in FIG. 1 is arranged on the glass substrate 201.
[0036]
Next, an amorphous silicon film is formed to a thickness of 500 mm by plasma CVD or low pressure thermal CVD. The film thickness of this amorphous silicon film may be about 200 to 2000 mm. Then, this is subjected to laser light irradiation and / or heat treatment. By doing so, a crystallizable silicon film (not shown) is obtained.
[0037]
Then, the crystalline silicon film (not shown) is patterned to form an active layer of the thin film transistor indicated by 202 in FIG. Next, a silicon oxide film 203 functioning as a gate insulating film is formed to a thickness of 1000 mm by plasma CVD or sputtering.
[0038]
Further, an aluminum film (not shown) containing scandium in an amount of 0.2 wt% is formed by sputtering to a thickness of 5000 mm. The reason why the scandium is contained in a trace amount in the aluminum film is to suppress the occurrence of hillocks and whiskers in the subsequent process (particularly the process in which heating is performed). Hillocks and whiskers are horn-like or stab-like projections formed by abnormal growth of aluminum.
[0039]
Next, an aluminum film (not shown) is patterned. Thus, the gate wiring 101 and the gate electrode 110 extending from the gate wiring 101 are formed. At the same time, a short-circuit wiring 100 extending from the gate wiring 101 is simultaneously formed.
[0040]
Although not shown in FIG. 2, a short-circuit wiring indicated by 109 in FIG. 1 is also formed simultaneously in this step. The gate wiring 101, the gate electrode 110 extending from the gate wiring, and the shorting wiring 100 extending from the gate wiring 101 are referred to as a first-layer wiring.
[0041]
As will be described in detail in another embodiment, a pattern for reducing or eliminating the discharged or induced high potential pulse is disposed on the short-circuit wiring.
[0042]
Next, anodization is performed in the electrolytic solution using the gate electrode 110, the gate wiring 101, and the short-circuit wirings 100 and 109 extending from the gate wiring as anodes. In this step, anodic oxide films 204 and 205 shown in FIG. 2A are formed.
[0043]
This anodized film is formed to a thickness of 500 mm. This anodic oxide film is effective for suppressing the generation of hillocks and preventing the occurrence of a short circuit between wirings. In this way, the state shown in FIG.
[0044]
In this anodizing step, an electrolytic solution obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia is used. In this electrolytic solution, an aluminum pattern is used as an anode and platinum is used as a cathode, and a current is passed between both electrodes.
[0045]
Next, impurity ions are implanted in the state of FIG. In this step, the source region 211 and the drain region 212 are formed in a self-aligning manner. (Fig. 2 (B))
[0046]
Next, a silicon oxide film or a silicon nitride film is formed as a first interlayer insulating film 206 to a thickness of 5000 mm by plasma CVD. As the interlayer insulating film, a laminated film of a silicon oxide film and a silicon nitride film or a silicon oxynitride film can be used. Note that the silicon oxynitride film is formed by a plasma CVD method using a mixed gas of TEOS gas and N ₂ O gas as a gas source.
[0047]
Next, contact holes are formed. This contact hole is formed by dry etching. In recent years, pattern miniaturization has progressed, and in accordance with this, dry etching that can utilize anisotropic etching tends to be frequently used.
[0048]
Here, even when dry etching is used, destruction of the thin film transistor in the middle of production by a high potential pulse induced from plasma is suppressed. This is because, for example, a high potential difference is suppressed from being applied to the gate insulating film 203 because the respective wirings and electrodes are connected and have the same potential.
[0049]
Next, a three-layer film of a titanium film, an aluminum film, and a titanium film for forming a second-layer wiring is formed. The three-layer film is formed by sputtering. Also at this time, the occurrence of a high potential difference between each wiring and electrode is suppressed.
[0050]
When the three-layer film is formed, it is patterned. In this manner, the source wiring 102 (extending to contact the source region 211), the drain electrode 113, and the shorting wiring 114 extending from the source wiring 102 are formed. (Fig. 2 (B))
[0051]
These electrodes and wirings are called second-layer wirings. The positional relationship between these wirings and electrodes is as shown in FIG.
[0052]
As is apparent from FIG. 2, a first-layer wiring (in FIG. 1, indicated by a solid line) including a gate electrode 110 extending from the gate wiring 101 (see FIG. 1) and a wiring 100 extending from the gate wiring 101. And a second-layer wiring (indicated by a dotted line in FIG. 1) composed of the source wiring 102 and the wiring 114 extending from the source wiring are vertically separated by the interlayer insulating film 206. Become.
[0053]
2B is obtained, a silicon oxide film or a silicon nitride film is formed as the second interlayer insulating film 207. (Fig. 2 (C))
[0054]
When the second interlayer insulating film 207 is formed, all electrodes and wirings are short-circuited. Therefore, generation of an unnecessary potential difference due to the influence of plasma can be suppressed. Further, it is possible to suppress the occurrence of defects due to local high voltage application.
[0055]
Further, a contact hole 208 for connecting the source electrode 113 and a pixel electrode 214 (see FIG. 2E) to be formed later is formed.
[0056]
At the same time, an opening 209 for cutting the short-circuit wiring 100 extending from the gate wiring 101 which is the first-layer wiring at a region 105 (see FIG. 2E) is formed.
[0057]
At the same time, an opening 210 for cutting the short-circuit wiring 114 extending from the source wiring 102 which is the second-layer wiring at a region 104 (see FIG. 2E) is formed. (Fig. 2 (C))
[0058]
These open grooves are also formed by dry etching. Also in this step, since each wiring and electrode are connected and have the same potential, the influence of a high potential induced between each wiring and electrode from plasma can be suppressed.
[0059]
As can be seen from FIG. 2C, openings 209 and 210 reaching the first layer wiring 100 and the second layer wiring 114 are formed in this step.
[0060]
Next, an ITO film 213 for forming the pixel electrode is formed by sputtering. Also in the formation of the pixel electrode, since each wiring and electrode have the same potential, it is possible to suppress an unnecessary potential difference between each wiring and between electrodes due to the influence of plasma.
[0061]
In particular, in the state where the gate wiring 101 which is the first layer wiring indicated by the solid line in FIG. 1 and the second layer wiring 102 indicated by the dotted line are short-circuited, the interlayer insulating film and the pixel electrode are formed. is important. By performing film formation (and dry etching) in such a state, a state in which a high voltage is applied between the first layer wiring and a region electrically connected therewith and the second layer wiring is suppressed. can do.
[0062]
As a result, for example, a situation where a high voltage is applied between the gate electrode 110 and the active layer 202 described above can be avoided. That is, application of a high voltage to the gate insulating film 203 can be suppressed.
[0063]
Next, the ITO film 213 is patterned. This patterning is also performed by dry etching. After the ITO etching, the wirings 100 and 114 are further etched. That is, the wirings 100 and 114 are removed by etching in the regions 105 and 104 in FIG.
[0064]
Thus, the wirings 100 and 114 are cut (divided) in the areas 105 and 104.
[0065]
FIG. 2 shows a state in which the wiring is divided at the areas indicated by 104 and 105 in FIG. In addition, the wiring 109 in the region indicated by 103 is divided at the same time in the same process.
[0066]
Thus, the circuit configuration of the pixel region of the active matrix liquid crystal display device is completed.
[0067]
In this embodiment, in the process of using plasma, each wiring or electrode that functions as an antenna is electrically shorted to have the same potential. Therefore, even when a high potential is locally induced from plasma, it is possible to suppress the destruction of the thin film transistor being manufactured due to the high potential.
[0068]
[Example 2]
This embodiment relates to a structure of a pixel region of an active matrix liquid crystal display device having an equivalent circuit as shown in FIG. FIG. 5A illustrates a state in which the structure having the equivalent circuit illustrated in FIG.
[0069]
In FIG. 5, 502 is a gate wiring, and 501 is a source wiring. The gate wiring and the source wiring are arranged in a matrix, and pixel electrodes as indicated by 512, 513, and 514 are arranged in a region surrounded by the two wirings.
[0070]
The configuration shown in FIG. 5 is a circuit configuration as shown in FIG. 5B when the gate wiring 502 and the capacitor line 503 cross over the M-type semiconductor layer (active layer). .
[0071]
As is clear from FIG. 5B, the circuit does not operate when the gate wiring 502 and the capacitor line 503 are directly connected. The gate wiring 502 and the capacitor line 503 are formed by patterning the same conductive film.
[0072]
In such a configuration, when an insulating film is formed to cover the gate wiring 502 and the capacitor line 503, a high voltage may be applied between the two wirings. As apparent from FIG. 5B, when a high voltage is applied between the gate wiring 502 and the capacitor line 503, the transistors and MOS capacitors formed between them are destroyed.
[0073]
Therefore, in the configuration shown in this embodiment, until the pixel electrode 513 (this pixel electrode is formed last) is formed, the gate line 502 and the capacitor line 503 are connected at a portion indicated by 500. 500 regions are cut when the pixel electrode 513 is patterned.
[0074]
With such a structure, it is possible to prevent a high voltage from being applied between the gate wiring 502 and the capacitor line 503 without particularly increasing the number of manufacturing steps.
[0075]
Example 3
This embodiment relates to the short-circuiting wires 109 and 114 shown in FIG.
[0076]
The pulsed high potential induced by the plasma is generated by local abnormal discharge. Therefore, the place where the pulsed high potential is induced is also an unspecified local region.
[0077]
When the active matrix region has a large area, it is conceivable that a high potential pulse induced from plasma propagates over a long distance through the wiring. In such a case, there is a concern about the influence of the propagating high potential pulse even if each wiring or electrode has the same potential.
[0078]
The present embodiment relates to a configuration that is effective in such a case. In this embodiment, a pattern as shown in FIG. 6 is formed on a part of the short-circuit wiring indicated by 109, 114, and 100.
[0079]
FIG. 6A shows a wiring pattern for reducing or eliminating the high potential pulse waveform propagating through the wiring 601 at a portion indicated by 602. This wiring pattern is for colliding a pulse at a portion indicated by 602 and discharging the energy there.
[0080]
It is effective to arrange the pattern as shown in FIG. 6A in the middle of the short-circuit wiring indicated by 100 or 114 or at the terminal portion. This is effective in preventing the high potential pulse from reciprocating the wiring many times.
[0081]
FIG. 6B illustrates a wiring 604 in which a discharge pattern 605 is disposed surrounded by a solid wiring 603 having a ground potential.
[0082]
It is effective to arrange such a pattern at the terminal portion of the short-circuit wiring indicated by 100 or 114. It is also useful to dispose in an area between the active matrix area and the peripheral drive circuit area.
[0083]
In FIG. 7, two wirings 701 and 703 are connected by a wiring pattern as indicated by 702. Such a structure has a function in which a high potential pulse propagating through the wirings 701 and 703 collides with a pattern portion 702 and is discharged there.
[0084]
It is effective to provide the pattern as shown in FIG. 7 at the terminal portion of the short-circuit wiring indicated by 100 or 114 or a portion away from the active matrix region. By providing a pattern as shown in FIG. 7, it is possible to suppress the high potential pulse from being propagated in the active matrix circuit indefinitely.
[0085]
【The invention's effect】
By utilizing the invention disclosed in this specification, it is possible to prevent a semiconductor device being manufactured from being broken by a pulsed high potential induced from plasma. In particular, this can be realized without adding a special manufacturing process.
[Brief description of the drawings]
FIG. 1 shows an outline of a configuration of an active matrix liquid crystal display device.
FIG. 2 illustrates a process for manufacturing an active matrix circuit.
FIG. 3 shows the energy distribution of ions in plasma.
FIG. 4 illustrates a conventional manufacturing process of a thin film transistor.
FIG. 5 illustrates an example of an active matrix circuit.
FIG. 6 is a diagram showing a wiring pattern.
FIG. 7 is a diagram showing a wiring pattern.
[Explanation of symbols]
101 Gate wiring 102 Source wiring 103 Cutting area 104 Cutting area 105 Cutting area 106 Thin film transistor 107 Liquid crystal 108 Source wiring 109 Short wiring 110 Gate electrode 112 Gate wiring 211 Drain area

Claims (6)

Forming a plurality of first wirings extending to the gate electrodes of the plurality of thin film transistors and a first short-circuiting wiring connecting the first wirings;
Forming a first insulating film on the first wiring and the first short-circuit wiring;
A plurality of second wirings connected to source regions of the plurality of thin film transistors and a second short-circuiting wiring connecting the second wirings are simultaneously formed on the first insulating film;
Forming a second insulating film on the second wiring and the second short-circuit wiring;
Forming an opening reaching the first short-circuit wiring in the first insulating film and the second insulating film;
Forming an opening reaching the second short-circuit wiring in the second insulating film;
A method for manufacturing a semiconductor device, comprising forming a conductive pattern on the second insulating film,
The first short-circuit wiring and the second short-circuit wiring are made of a film containing aluminum,
The conductive pattern is made of an ITO film,
Cutting of patterned and the first and second short-circuit wiring of the conductive pattern, have lines by dry etching,
A method for manufacturing a semiconductor device, wherein the first and second short-circuit wirings are simultaneously cut when the conductive pattern is formed by patterning. In claim 1,
At least one wiring of the first wiring and at least one wiring of the second wiring are connected by a third short-circuit wiring,
The method of manufacturing a semiconductor device, wherein the third short-circuit wiring is cut simultaneously with the first and second short-circuit wirings when the conductive pattern is formed by patterning. In claim 2 ,
The method for manufacturing a semiconductor device, wherein patterning of the conductive pattern and cutting of the first to third short-circuit wirings are performed by dry etching. In any one of Claims 1 thru | or 3 ,
The method for manufacturing a semiconductor device, wherein the first insulating film includes a silicon oxide film, a silicon nitride film, or a silicon oxynitride film formed by a plasma CVD method. In any one of Claims 1 thru | or 4 ,
The method for manufacturing a semiconductor device, wherein the second insulating film is a silicon oxide film or a silicon nitride film formed by a plasma CVD method. In any one of Claims 1 thru | or 5 ,
The method for manufacturing a semiconductor device, wherein the conductive pattern is an ITO film formed by a sputtering method.

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