KR100480192B1 - Method of manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

TFTs with improved reliability are disclosed. The interlayer dielectric film forming the TFTs is composed of a silicon nitride film. Other interlayer dielectric films also consist of silicon nitride. The stress in the silicon nitride film forming such an interlayer dielectric film is set between -5 x 10 ⁹ and 5 x 10 ⁹ dyn / cm ² . This can suppress the difficulty in peeling and forming contact holes of the interlayer dielectric films. Moreover, hydrogen evolution from the active layer can be suppressed. In this way very reliable TFTs can be obtained.

Description

Semiconductor device and manufacturing method

Background of the Invention

1. Field of Invention

The present invention relates to a thin film transistor structure and a method of manufacturing the same.

2. Description of related technology

Thin film transistors (TFTs) fabricated on glass substrates or insulating surfaces are known. TFTs of this kind have been especially developed for use in active matrix liquid crystal displays.

In an active matrix liquid crystal display, millions of pixel electrodes are arranged in rows and columns, and TFTs are connected to these pixel electrodes. Charges entering and exiting the pixel electrodes are controlled by respective TFTs.

The manufacture of this type of active matrix liquid crystal display requires a technique for producing tens of thousands of TFTs on glass substrates or quartz substrates that are at least several square centimeters.

Today's technology makes it impossible to produce single crystal silicon thin films on glass or quartz substrates that are at least several square centimeters. Therefore, generally manufactured silicon films are represented by an amorphous silicon film, a polycrystalline silicon film, and a crystalline silicon film.

When an amorphous silicon film is used, the P-channel type cannot be executed. Also, high speed operation cannot be achieved. Therefore, it is impossible to manufacture a peripheral driver circuit required to operate at several MHz or more from TFTs using an amorphous silicon film.

On the other hand, when a crystalline silicon film characterized by a polycrystalline and crystalline silicon film is employed, the P-channel TFT can be put to practical use. Thus, CMOS circuits can be made. In addition, high speed operations over several MHz are possible. Using these characteristics, the peripheral driver circuit can be integrated with the active matrix circuit on the same substrate.

However, TFTs using crystalline silicon films suffer from reliability problems and property changes. These deteriorate the quality of the displayed image.

These reliability and property change problems are caused by the unstable elements included in the processing step for creating contact holes as well as the unstable elements included in the state of the crystalline silicon film forming the active layer.

It is generally known that a silicon oxide film is used as the interlayer dielectric film in the TFTs. However, the silicon oxide film has problems as described below.

The silicon oxide film exhibits a low etching rate during the dry etching process. To get the actual etch rate, it is necessary to increase the self-bias voltage to about 600V. This often causes electrostatic discharge damage due to the voltage induced across the multilayer metallization when conductive wires are formed.

Moreover, since the etching process is performed using the increased self bias voltage, the etching process tends to be unstable. Thus, it is difficult to ensure sufficient processing margin.

For example, by devising etching conditions, it is difficult to gradually taper the ends of the contact holes.

Generally, when an active layer of a TFT is formed using a crystalline silicon film, it is necessary to hydrogenate the active layer. That is, chemically bound dangling bonds of silicon in the crystalline silicon film are neutralized with hydrogen to stabilize electrical characteristics.

Regardless of the type of TFTs, it is necessary to form an interlayer dielectric film after the formation of the active layer.

When the silicon oxide film is used as an interlayer dielectric film, since only a weak barrier to hydrogen exists in the silicon oxide film, a problem arises in that hydrogen contained in the active layer becomes free easily. This greatly destabilizes the TFT characteristics.

When the silicon oxide film is used as the interlayer dielectric film, it is difficult to detect the end point of etching when the etching is a dry etching process. Generally, quartz jigs are used as holders or stages for holding the substrate.

In this case, during the dry etching process, the silicon oxide component is released from the quartz jig to the vicinity of the etching. This makes it difficult to detect the end point of silicon oxide film etching.

In particular, the detection of the silicon oxide component in the surroundings makes it difficult to clearly detect the end point of the silicon oxide film etching.

This means that the number of unstable elements in the manufacturing process increases.

Summary of the Invention

It is an object of the present invention to provide a TFT that exhibits stable characteristics and can be manufactured with high yield by eliminating difficulties in the manufacture of TFTs.

It is still another object of the present invention to provide an active matrix display device which can stably display high quality images and can be manufactured with high yield.

The semiconductor device disclosed herein includes an active layer composed of a semiconductor, a silicon oxide film formed on the active layer, and a multilayer silicon nitride film formed on the first dielectric film. The silicon oxide film acts as a gate insulating film. The silicon nitride film acts as an interlayer dielectric film.

The present invention also provides a semiconductor device composed of TFTs including an active layer composed of a crystalline silicon film and interlayer dielectric films all made of silicon nitride.

When the silicon nitride film is used as the interlayer dielectric film, the following advantages can be obtained.

First, the dry etching rate is high. In addition, the self bias voltage can be set to a low value of approximately 1500V. Thus, etching can be made stable. Moreover, large processing margins can be obtained.

In addition, there is a high barrier to hydrogen, and the release of hydrogen contained in the active layer can be prevented. As a result, the characteristics of the TFT are aged to a smaller extent than before.

In addition, the relative dielectric constant is high. Therefore, capacitors can be easily formed using an interlayer dielectric film. In particular, in an active matrix liquid crystal display, it is necessary to connect an auxiliary capacitor to the outputs of TFTs arranged in pixels. It is advantageous to form these auxiliary capacitors from the silicon nitride film forming interlayer dielectric films.

Preferably, in the present invention disclosed herein, the quality of the silicon nitride film forming the interlayer dielectric films is set so that the internal stress lies in the range of -5 x 10 ⁹ to 5 x 10 ⁹ dyn / cm ² .

This is important to prevent peeling of the film when the multilayer structure is formed. This is also important for preventing peeling of the conductive wires formed on the interlayer dielectric film. Moreover, this is important for preventing disconnection and bad contacts of the contact electrodes due to stress.

In particular, in the case where ITO electrodes generating pixel electrodes are formed on the interlayer dielectric films, the above-described condition is important for preventing peeling of the ITO electrodes.

These limitations on stress become more important when the area of the active matrix area is increased. As the area of the observation screen increases, the area of the active matrix area also increases.

The silicon nitride films forming the interlayer dielectric film are advantageously designed such that the internal stress lies in the range of -5 x 10 ⁹ to 5 x 10 ⁹ dyn / cm ² , and all silicon nitride films are compressively stressed. This makes the direction of the stress acting uniform for all the interlayer dielectric films, which is effective in actually preventing the interlayer dielectric films from peeling off. In addition, bad contacts and disconnections in the contact electrodes and the conductive wirings can be effectively prevented.

Similarly, advantages arise even when all interlayer dielectric films are compressively stressed.

Moreover, it is advantageous that the deviations in the internal stresses of the various silicon nitride layers forming the interlayer dielectric films are suppressed to be less than ± 50%.

In addition, it is advantageous to use a silicon oxide film which forms an interlayer dielectric film such that the etching rate for 1/10 buffered hydrofluoric acid is in the range of 30 to 1500 mW / min.

The present invention also provides a method of manufacturing a semiconductor device using a silicon nitride film, comprising the step of forming a silicon nitride film by chemical vapor deposition. In this method, the internal stress of the silicon nitride film grown by injecting hydrogen into the deposition atmosphere is in the range of -5 x 10 ⁹ to 5 x 10 ⁹ dyn / cm ² , with respect to 1/10 buffered hydrofluoric acid. The etching rate is characterized in that it is in the range of 30 to 1500 Pa / min.

Example 1

The present invention relates to processing steps for manufacturing thin film transistors (TFTs) arranged in pixels of an active matrix liquid crystal display.

Processing steps of this embodiment for manufacturing TFTs are shown in Figs. 1A to 3B. First, as shown in FIG. 1A, a silicon oxide film is formed as a buffer film 102 on a glass substrate 101 with a thickness of 3000 kPa by plasma chemical vapor deposition (CVD) or sputtering. . The buffer film may also be composed of silicon oxide.

The substrate is not limited to the glass substrate 101. Quartz substrates or other substrates (eg, semiconductor substrates) on which a suitable dielectric film is deposited may also be used. In an integrated circuit having a multilevel metallization or a multilayer structure, a suitable insulating film can be used as the substrate.

Then, a silicon film (not shown) is deposited which will later form the active layer of TFTs. In this embodiment, a 500 Å thick amorphous silicon film is formed by plasma CVD. The amorphous silicon film can be made by LPCVD.

Thereafter, heat treatment and laser irradiation are performed to crystallize the amorphous silicon film, thereby obtaining a crystalline silicon film (not shown).

After the crystalline silicon film is obtained, it is patterned to form the active layer 103 of the TFTs. The silicon oxide film 104 serving as the gate insulating film is deposited to a thickness of 1000 kPa by plasma CVD.

The metal material or silicon material for forming the gate electrode is deposited as a film. This film is then patterned to produce gate electrodes 105 and scan lines (also known as gate lines) 106. Although not explicitly shown, the gate electrodes 105 are typically implemented to extend from the scan lines 106.

Silicon materials that are heavily doped and have reduced resistivities can be used as the material of the gate electrodes 105 and the scan lines 106. In addition, metal materials represented by aluminum and molybdenum and various silicon materials may be employed.

In this way, the state shown in Fig. 1A is obtained. Under this condition, dopant ions are implanted to create source and drain regions. In this embodiment, phosphorus (P) ions are implanted by plasma doping to produce N-channel TFTs.

After impurity implantation, laser light or other strong light irradiation is performed to anneal and activate the region into which the impurity has been implanted. This treatment step can use a method that depends on the heat treatment.

In this way, source regions 11, drain regions 13, and channel forming regions 12 are formed in a self-aligning method.

Thereafter, as shown in Fig. 1B, a silicon nitride film is deposited as the first interlayer dielectric film 107 to a thickness of 3000 mV by plasma CVD. The thickness of this silicon nitride film can be set between approximately 3000 and 5000 kPa. One example of the conditions under which the silicon nitride film is grown is given in Table 1 below.

Table 1

The etch rate given in Table 1 is the value obtained when the wet etchant LAL500 manufactured by Hashimoto Kasei Corporation is used. The internal stress of the film can be found by changing the hydrogen content.

Table 1 shows the deposition conditions in which hydrogen is not added to the atmosphere for comparison. The internal stress and the etching rate allow to consider that the silicon nitride film grown in the atmosphere in which no hydrogen is added cannot be mentioned as the silicon nitride film.

The active layer 103 is hydrogenated when this silicon nitride film is grown. That is, hydrogen generated by decomposition of hydrogen and ammonia mixed in the atmosphere is activated by plasma energy and eroded by the crystalline silicon film forming the active layer 103. This anneals the crystalline silicon film forming the active layer so that the film is hydrogenated.

As described above, the silicon nitride film provides a barrier against hydrogen. Therefore, it can be said that the formation of the first interlayer dielectric film 107 acts to limit hydrogen in the active layer 103.

Thereafter, contact holes 108 are generated in the first interlayer dielectric film 107 by a dry etching method (FIG. 1C).

The dry etching method used in this processing step is a reactive ion etching (RIE) method using a mixed gas of CF ₄ and O ₂ as an etchant gas.

In this step, excessive etching can be prevented by using the silicon oxide film 104 as an etch stopper.

Thereafter, contact holes 109 extending from the silicon oxide film 104 are produced by a wet etching method. In other words, lower portions of the contact holes 108 where the silicon oxide film 104 is exposed are etched to form the contact holes 109.

In this embodiment, the wet etching is performed using an etchant which is a mixture of hydrofluoric acid, ammonia fluoride, and a surfactant.

This removal of the silicon oxide film 104 to create the contact holes 109 can be performed without using a mask. In particular, the resist mask used to form the contact holes 108 may be used as it is.

Optionally, if no resist mask is present, the contact holes 109 can be formed in a self-aligning manner by using the contact holes 108 formed previously.

In general, the etching rate of the silicon nitride film on the HF based etchant is lower than that of the silicon oxide film by about 10 or more. Therefore, etching of the silicon oxide film hardly causes a problem during the above-described steps.

In this embodiment, wet etching is used to form the contact holes 109. Methods according to dry etching may also be used. In this case, contact holes 109 are formed following the formation of the contact holes 108. However, in the dry etching step, the etchant gas must be replaced with CHF ₃ (FIG. 1 (D)).

After obtaining the state shown in Fig. 1D, the source wirings 110 which make contact with the source electrode or the source regions are made from a suitable metal material (Fig. 2A).

Thereafter, a silicon nitride film is formed as the second interlayer dielectric film 111 by a thickness of 3000 kPa by plasma CVD. The thickness of the silicon nitride film forming the second interlayer dielectric film 111 can be set between 2000 and 5000 kPa (FIG. 2B).

The second interlayer dielectric film 111 is grown under the same conditions as the first interlayer dielectric film 107. If the film thickness changes, only the conditions associated with the film thickness are corrected.

Thus, contact holes 112 are formed in the silicon nitride films forming the first interlayer dielectric film 107 and the second interlayer dielectric film 111 (FIG. 2C).

This dry etching is performed under the same conditions as the formation of the contact holes 108 shown in Fig. 1C. However, since the etching depths are different, preparation experiments need to be performed to determine the etching time.

Also during this step, the silicon oxide film 104 can be used as an etching stopper.

In this way, the state shown in Fig. 2C is given. Thereafter, the silicon oxide film 104 exposed at the lower portions of the contact holes 112 is etched by a wet etching method. As a result, the contact holes 113 are generated. These contact holes 113 may also be formed by dry etching.

After obtaining the state shown in Fig. 2D, an ITO film forming the pixel electrode is formed by a sputtering method and patterned to form the pixel electrodes 114 (Fig. 3A).

The final protective film 115 is also formed of a silicon nitride film (Fig. 3 (B)).

An orientation film (not shown) for orienting the liquid crystal material is formed on the protective film 115 and is oriented.

In this way, TFTs arranged in the pixel portions of the active matrix liquid crystal display are completed.

In these TFTs, a silicon nitride film is used as the interlayer dielectric film so that contact holes having a high regeneration force can be generated using a dry etching process.

Since the silicon nitride film used as the interlayer dielectric film acts to limit the hydrogen present in the active layer, instability and aging of the characteristics of the TFTs can be suppressed.

Example 2

This embodiment is similar to the configuration described in Embodiment 1 except that lightly doped drain (LDD) regions are arranged in the TFTs. The processing sequence in this embodiment is shown in Figs. 4A to 4D, 5A to 5D, and 6A to 6B. This embodiment has the processing conditions and details as used in the first embodiment.

First, the silicon oxide film 402 is formed as a buffer film on the glass substrate 401 with a thickness of 3000 kPa. Subsequently, an amorphous silicon film (not shown) is grown by plasma CVD. The amorphous silicon film is crystallized by a combination of laser light irradiation and heat treatment to obtain a crystalline silicon film (not shown).

The crystalline silicon film described above is patterned to form an island of a region 403 (Fig. 4 (A)), which will later be an active layer of the TFT.

After the active layer 403 is formed, a silicon oxide film 404 serving as a gate insulating film is formed to a thickness of 1000 占 by plasma CVD.

An aluminum film (not shown) for forming the gate electrode is formed to a thickness of 4000 kPa by sputtering.

This aluminum film contains 0.1 weight percent scandium to prevent the occurrence of low hillocks and whiskers in later processing steps. These hillocks and whiskers are needle-like raised and pointed portions formed by abnormal growth of aluminum in the heat treatment step.

After growing an aluminum film (not shown), it is patterned to form gate electrodes 405. At the same time scan lines 406 are formed.

Thereafter, anodization is performed to form the porous anodic oxide films 407 and 408. The porous anodic oxide films 407 and 408 are formed by performing anodization in an electrolytic solution using the anodes composed of the aluminum film pattern portions 405 and 406 and the cathode of platinum. In this embodiment, an aqueous solution containing 3% oxalic acid is used as the electrolytic solution.

During this anodization process, the porous anodic oxide film can be grown up to several micrometers by controlling the anodization time. In this embodiment, this porous anodic oxide film is grown to a thickness of 5000 kPa.

Thereafter, anodization is again performed using an ethylene glycol solution containing 3% tartaric acid as the electrolytic solution. As a result of this processing step, anodization films 409 and 410 are formed. This anodic oxide film is barrier type and has a dense property.

The growth distances of the dense anodic oxide films 409 and 410 can be controlled by the applied voltage. In this embodiment, the film thickness is set to 700 mm 3. This anodic oxide film can be grown up to about 3000 GPa.

When the thickness of this dense anodic oxide film is increased, the increased thickness allows the formation of an offset gate region. When the effective offset gate region is formed, it is necessary to set the thickness of the anodic oxide film to 2000 GPa or more.

Since the electrolyte solution enters the porous dense anodic oxide films 409 and 410, this film is produced in the state shown in Fig. 4A.

After obtaining the state shown in Fig. 4A, the exposed silicon oxide film 404 is removed. The porous anodic oxide films 407 and 408 are selectively removed using a mixed acid of acetic acid, nitric acid, and phosphoric acid.

Thereafter, impurity ions are implanted. In this embodiment, P-type ions are implanted to form each N-channel TFT. In this processing step, the source region 41, the channel forming region 42, the slightly doped (LDD) region 43, and the drain region 44 are formed by the self-aligning method (FIG. 4B).

After implantation of the impurity ions described above, laser light or other strong light is irradiated to anneal and activate the impurity implanted regions.

The first interlayer dielectric film 412 is formed. The silicon nitride film 412 is formed of a first interlayer dielectric film 412 having a thickness of 3000 kPa by plasma CVD. The hydrogen content of the atmosphere in which the silicon nitride film is grown is controlled so that the stress in the film lies within -5 x 10 ⁹ to 5 x 10 ⁹ dyn / cm ² .

During this processing step, the active layer 403 is hydrogen-passivated at the same time.

In this way, the state shown in Fig. 4B is obtained. Thereafter, contact holes 413 are created by a dry etching method (FIG. 4C).

In this way, the state shown in Fig. 4C is obtained. The contact holes 414 are formed in the silicon oxide film 411 by wet etching. Contact holes can also be created by dry etching.

Therefore, the state shown in Fig. 4D is derived. Thereafter, as shown in FIG. 5A, source electrodes 415 and source wirings 415 contacting the source regions are formed. In this embodiment, these electrodes or wires are made of a titanium / aluminum / titanium laminated film (Fig. 5 (A)).

Thereafter, a 3000 nm thick silicon nitride film is formed as the second interlayer dielectric film 416 by plasma CVD. This silicon nitride film is grown under the same conditions as the first interlayer dielectric film 412 (Fig. 5 (B)).

Contact holes 417 that extend through the silicon nitride films 412 and 416 are formed by a dry etching method (FIG. 5C).

Thereafter, wet etching is performed to form contact holes 418 leading to the drain region 44. Contact holes 418 may also be produced by a dry etching method.

In this way, contact holes extending through the first and second interlayer dielectric films 412 and 416 to the drain regions 44 may be formed (FIG. 5D).

Thereafter, an ITO film for forming pixel electrodes is formed and patterned to produce pixel electrodes 419 as shown in Fig. 6A.

It is formed as the final protective film of the silicon oxide film 420, and thus obtains the state shown in Fig. 6B.

In the TFT described in this embodiment, a slightly doped (LDD) region 43 is arranged between the channel forming region 42 and the drain region 44 to mitigate the electric field strength between these two regions. This region is commonly referred to as the LDD region and is effective in lowering the OFF current.

The TFTs described in this embodiment can have an excellent function in maintaining charge stored in the pixel electrodes 419. This function is useful for displaying higher quality images.

Example 3

This embodiment relates to a configuration in which a black matrix is disposed on a TFT panel substrate. The processing sequence for this embodiment is shown in Figs. 7A to 7C. First, a silicon oxide film or a silicon nitride film is formed on the glass substrate 701 as the buffer film 702.

Thereafter, an active layer serving as a crystalline silicon film is formed. In FIG. 7A, the islands of the regions 703-705 form an active layer. As will be apparent later, the regions indicated by 703, 704, and 705 become drain regions, channel forming regions, and source regions, respectively.

Thereafter, a silicon oxide film that functions as the gate insulating film 706 is formed. Using metal material or silicon material, gate electrodes 707 and scan lines (gate lines) 708 are formed.

Under this condition, impurity ions are implanted to form the source region 705, the drain region 703, and the channel forming region 704 by a self-aligning method.

A silicon nitride film is formed as the first interlayer dielectric film 709. Contact holes are formed in the first interlayer dielectric film 709 by a dry etching method.

Thereafter, source electrodes or source wirings 710 are formed from a suitable metal material. The silicon nitride film is formed as the second interlayer dielectric film 711.

Thereafter, contact holes 712 leading to the drain region 703 are formed by a dry etching method. In this way, the state shown in Fig. 7A is obtained.

After obtaining the state shown in FIG. 7A, a black matrix (BM) material is deposited into the film. This black matrix material can be a titanium film, chromium film, or a titanium / chromium deposited film.

This black matrix material film is patterned to form black matrices 713 and 715. At the same time, an electrode 714 in contact with the drain region 713 is formed. That is, the electrode 714 is made of a material such as a black matrix (Fig. 7B).

After obtaining the state shown in FIG. 7B, a silicon nitride film is formed as the third interlayer dielectric film 716 having the same film quality as both the first interlayer dielectric film 709 and the second interlayer dielectric film 711. . This silicon nitride film has a thickness of 500 kPa (Fig. 7 (C)).

A contact hole reaching the electrode 714 is formed. The pixel electrode 717 is formed of ITO. The silicon nitride film is formed as the final protective film 718 (FIG. 7C).

In the configuration described in this embodiment, an overlap between the black matrix 713 and the pixel electrode 717 forms an auxiliary capacitor. The silicon nitride film has a high relative dielectric constant of about 6 to 7. Therefore, it is advantageous to use the third interlayer dielectric film 716 made of silicon nitride as the dielectric of the capacitor. The relative dielectric constant of the silicon oxide film is approximately four.

Example 4

This embodiment is similar to the third embodiment except for the configuration in which the black matrix is arranged on the TFT substrate. First, a silicon oxide film 702 is formed on the glass substrate 701 as a buffer layer. Thereafter, active layers 703-705 are formed. In addition, a silicon oxide film 706 that functions as a gate insulating film is deposited.

The gate electrode 707 and the scan line 708 are formed of a suitable metal material or silicon material. Thereafter, a silicon nitride film is deposited as the first interlayer dielectric film 709. Contact holes are formed in the first interlayer dielectric film 709 by a dry etching method. In this embodiment, the contact holes are formed in the source region 705 and the drain region 703.

After forming contact holes in the first dielectric layer 709, the source electrode 710 and the drain electrode 800 are formed of the same material.

Thereafter, a silicon nitride film is deposited as the second interlayer dielectric film 711. The contact hole 801 is formed in the second interlayer dielectric film by dry etching. During this processing step, electrode 800 acts as an etch stopper.

In this way, the state shown in Fig. 8A is obtained. Thereafter, the material forming the black matrix is deposited as a film and patterned to form the black matrix portions 713 and 715 as well as the portion 804 serving as the extractor electrode (Fig. 8 (B)).

Thereafter, a silicon nitride film is formed of the third interlayer dielectric film 716. Contact holes reaching the electrode 804 are created, and pixel electrode formations 717 of ITO are formed. Then, the silicon nitride film 718 is formed as a final protective film (FIG. 8C).

Example 5

This embodiment relates to a configuration in which a black matrix is arranged on a TFT substrate and a pixel electrode is in direct contact with the drain region.

The processing sequence for this embodiment is described in Figs. 9A to 9D. First, a silicon oxide film 902 is formed on the glass substrate 901 as a buffer film. Thereafter, an active layer 903-905 is formed from the crystalline silicon film. Thereafter, a silicon oxide film 90 serving as a gate insulating film is deposited.

Gate electrodes 906 and scan lines 907 are formed simultaneously from a suitable metal or silicon material. The silicon nitride film is formed as the first interlayer dielectric film 908.

After formation of the first interlayer dielectric film 908, contact holes for gaining access to each source region 903 are formed by a dry etching method. Each source electrode 909 is formed of a suitable metal material.

After formation of the source electrode 909, a silicon nitride film is deposited as the second interlayer dielectric film 910. In this way, the state shown in Fig. 9A is obtained.

After obtaining the state shown in Fig. 9A, black matrix (BM) films 911 and 912 are formed of titanium, chromium, or titanium / chromium deposition films. In this way, the state shown in Fig. 9B is obtained.

After obtaining the state shown in FIG. 9B, a silicon oxide film or a silicon nitride film is formed as the third interlayer dielectric film 913. Thereafter, the contact holes 914 are formed by a dry etching method to be in the state shown in Fig. 9C.

Thereafter, pixel electrodes 915 are formed from ITO. The silicon nitride film is deposited as the final protective film 916.

Also, in the configuration described in this embodiment, the overlap between each pixel electrode 915 and the black matrix films 911 and 912 forms a capacitor in which a dielectric is formed by the interlayer dielectric film 913.

Example 6

This embodiment relates to a configuration including an active layer composed of a semiconductor, a silicon oxide film formed on the active layer, and a multilayer silicon nitride film formed on the first dielectric layer. The silicon oxide film acts as a gator insulating film. The silicon nitride film acts as an interlayer dielectric film. The multilayers in the interlayer dielectric film are designed such that the lower layer has a higher etch rate.

The processing sequence for this embodiment is explained in Figs. 1A to 1D, Figs. 2A to 2D, and Figs. 3A to 3B. Processing conditions of the processing order are similar to those of the first embodiment unless otherwise specified. This embodiment is characterized in that the interlayer dielectric films 107 and 111 made of silicon nitride have different etching rates.

In particular, the interlayer dielectric film 107 has a smaller etching rate, while the interlayer dielectric film 111 has a higher etching rate.

This can suppress the tendency for the diameter to increase internally when each contact hole 112 is created. That is, the tendency for the hole to be conical can be suppressed.

This configuration is advantageous when interlayer dielectric films are formed in multiple layers and contact holes are needed to extend through the multiple layers.

Difficulties in the manufacture of TFTs can be eliminated by the use of the invention disclosed herein. TFTs with stable characteristics can be obtained with high production yield. In addition, active matrix liquid crystal displays that provide a stable display of high quality can be manufactured with high yield.

1A to 1D illustrate processing steps for manufacturing a TFT.

2A to 2D illustrate processing steps for manufacturing a TFT.

3A and 3B illustrate processing steps for manufacturing a TFT.

4A to 4D illustrate processing steps for manufacturing a TFT.

5A to 5D illustrate processing steps for manufacturing a TFT.

6A to 6D illustrate processing steps for manufacturing a TFT.

7A to 7C illustrate processing steps for manufacturing a TFT.

8A to 8C illustrate processing steps for manufacturing a TFT.

9A to 9D illustrate processing steps for manufacturing a TFT.

* Description of the symbols for the main parts of the drawings *

11 source region 12 channel forming region

13: drain area

Claims (13)

In a semiconductor device, An active layer comprising a semiconductor material; A silicon oxide film formed on the active layer; A plurality of silicon nitride films formed on the silicon oxide film, The silicon oxide film functions as a gate insulating film, and the plurality of silicon nitride films functions as interlayer dielectric films, Internal stresses of the plurality of silicon nitride films act in the same direction. In a semiconductor device, An active layer comprising a semiconductor material; A silicon oxide film formed on the active layer; A plurality of silicon nitride films formed on the silicon oxide film, The silicon oxide film functions as a gate insulating film, and the plurality of silicon nitride films functions as interlayer dielectric films, Internal stresses of the plurality of silicon nitride films act in the same direction, Each of the plurality of silicon nitride films has an internal stress of −5 × 10 ⁹ to 5 × 10 ⁹ dyn / cm ² . In a semiconductor device, A substrate having an insulating surface; A thin film transistor formed on the insulating surface; A first interlayer insulating film including silicon nitride formed on the thin film transistor; A second interlayer insulating film including silicon nitride formed on the first interlayer insulating film, The internal stresses of the first and second interlayer insulating films act in the same direction. In a semiconductor device, A substrate having an insulating surface; A thin film transistor formed on the insulating surface; A first interlayer insulating film including silicon nitride formed on the thin film transistor; A second interlayer insulating film including silicon nitride formed on the first interlayer insulating film, Wherein the internal stresses of the first and second interlayer insulating films act in the same direction, each having an internal stress of −5 × 10 ⁹ to 5 × 10 ⁹ dyn / cm ² . The method according to any one of claims 1 to 4, And all the interlayer insulating films in the semiconductor device include silicon nitride. The method according to any one of claims 1 to 4, Deviations in the internal stresses of the plurality of silicon nitride films and the first and second interlayer insulating films are within ± 50%. The method according to any one of claims 1 to 4, And the etching rates of the plurality of silicon nitride films and the first and second interlayer insulating films are different. The method according to any one of claims 1 to 4, And the etching rate of the upper layers of the plurality of silicon nitride films or the first and second interlayer insulating films is greater than the etching rate of the lower layers of the plurality of silicon nitride films or the first and second interlayer insulating films. The method according to any one of claims 1 to 4, Wherein the plurality of silicon nitride films and the first and second interlayer insulating films each exhibit an etching rate of 30 to 1500 A / min for 1/10 buffered hydrofluoric acid. The method according to any one of claims 1 to 4, And a capacitor, wherein one of the plurality of silicon nitride films and the first and second interlayer insulating films function as a dielectric film of the capacitor. The method according to any one of claims 1 to 4, And the active layer of the active layer and the thin film transistor each contain hydrogen. In the method of manufacturing a semiconductor device using a silicon nitride film, The silicon nitride film has an internal stress of −5 × 10 ⁹ to 5 × 10 ⁹ dyn / cm ² and includes hydrogen in such a manner that it exhibits an etching rate of 30 to 1500 A / min for 1/10 buffered hydrofluoric acid. Forming a silicon nitride film by chemical vapor deposition (CVD) in a semiconductor. The method according to any one of claims 1 to 4, And all of the plurality of silicon nitride films and the first and second interlayer insulating films have internal stresses acting in the compression direction.

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