JPH09199474A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a construction to ensure formation of a contact in a semiconductor device and to satisfy a requirement of fine pattern formation. SOLUTION: A silicon oxide film 104 which functions as a gate insulating film is formed on an active layer 103. Further, a silicon nitride film is formed as an interlayer insulating film 107. Then, an opening 108 is formed by dry etching which can cope with fine pattern formation at this time. Further, the silicon oxide film 104 exposed at the bottom of the opening 108 is etched to form an opening hole 109 by wet etching which can be performed without damaging the active layer 103 at this time. As the silicon oxide film 104 can be thin, the problem of isotropic etching in wet etching (the problem that etching progresses in a horizontal direction) can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The invention disclosed in this specification is
The present invention relates to a configuration in which formation of a contact portion of a semiconductor device is particularly devised. Specifically, the present invention relates to a configuration capable of reliably forming a contact and further simplifying the manufacturing process.

[0002]

2. Description of the Related Art Conventionally, a thin film transistor formed on a glass substrate or an appropriate insulating surface has been known. Such a thin film transistor requires an etching process with high processing accuracy as the pattern becomes finer. In particular, it is required to devise a method of forming contacts.

[0003]

The method of forming a contact hole in the active layer can be broadly classified into a dry etching method and a wet etching method.

In the method based on the dry etching method, anisotropic etching can be performed in the vertical direction, so that the size of the opening can be reduced and the deep opening (elongated opening) can be obtained.
Can be formed. This is very effective when forming a fine pattern.

However, the dry etching method has a problem in that it is difficult to finish the etching when the etching has proceeded for a predetermined distance. In general, when forming a contact hole reaching the active layer, it is currently difficult to finish the etching when the active layer is exposed.

In dry etching, the ratio of etching rates between different films (called a selection ratio)
There is a problem in that it is difficult to increase. That is, there is a problem that it is difficult to finish the etching when the etching of the predetermined film is finished.

The above problems cause overetching of the active layer.

Further, the dry etching method has a problem that plasma damage occurs in some overetching. For example, if a portion of the surface of the active layer is overetched to some extent, plasma damage occurs on the surface of the active layer, and it becomes difficult to make contact at that portion later. (Ohmic contact is lost)

Further, as a method of improving the characteristics of the thin film transistor, there is a method of reducing the thickness of the active layer to several hundred Å or less. Turn into. Also, due to excessive etching,
There is another problem that the active layer itself is removed by etching.

On the other hand, the method by wet etching is
By properly selecting the etchant, it is possible to increase the selection ratio depending on the material to be etched. That is, it is easy to set etching conditions that have a large etching rate for a certain material and a small etching rate for another certain material.

Therefore, for example, it is relatively easy to selectively remove only the insulating film on the active layer.

Further, in the wet etching method,
It has a remarkable feature that it does not damage the semiconductor layer.

On the other hand, however, the wet etching method is an isotropic etching method, and therefore, when a deep opening is formed, a phenomenon occurs in which the inside is cut away in the lateral direction. As a result, it becomes difficult to form a very fine pattern.

As described above, the dry etching method is advantageous in forming a fine pattern, but has a problem that selective etching is difficult. There is also a problem that plasma damage is given to the semiconductor layer.

On the other hand, the wet etching method is effective for selective etching and has the significance of not damaging the semiconductor layer. However, there is a problem that miniaturization is disadvantageous.

An object of the invention disclosed in this specification is to provide a method for manufacturing a thin film transistor which can surely make contact with the active layer of the thin film transistor and can realize miniaturization. Moreover, it aims at solving the said subject at the same time, without making a manufacturing process complicated.

Still another object is to manufacture a thin film transistor with a high production yield.

[0018]

One of the inventions disclosed in the present specification is, as shown in FIG. 1 showing a specific structure thereof, an active layer 103 made of a semiconductor and formed on the active layer. At least a first insulating film 104 and a second insulating film 107 formed on the first insulating film are provided, and the second insulating film 107 is formed by a dry etching method using the first insulating film as an etching stopper. A step of forming an opening 108 in the insulating film; and a step of etching the first insulating film exposed at the bottom of the opening by a wet etching method to form an opening 109 reaching the active layer. It is characterized by

As shown in the concrete structure of FIG. 2, another structure of the present invention is such that an active layer 103 made of a semiconductor, a first insulating film 104 formed on the active layer, and the first insulating film 104. At least an N layer (N = 2 in this case) insulating films 107 and 111 formed on the insulating film, and insulating the N layer by a dry etching method using the first insulating film as an etching stopper. A step of forming an opening 112 in the film, and a step of etching the first insulating film exposed at the bottom of the opening by a wet etching method to form an opening 113 reaching the active layer. Is characterized by.

In the above structure, the insulating films 107 and 111
Is a silicon nitride film. The first insulating film 104 is a silicon oxide film. The first insulating film is an insulating film that functions as a gate insulating film.

Another structure of the present invention includes an active layer, a silicon oxide film functioning as a gate insulating film formed on the active layer, and a silicon nitride film formed on the silicon oxide film. A step of forming an opening in the silicon nitride film by the first etching method and exposing the silicon oxide film at the bottom thereof, and a step of opening the silicon oxide film exposed at the bottom of the opening by the second etching method. And exposing the active layer at the bottom thereof.

Further, in the above structure, the first etching method is an etching method having a vertical anisotropy, and the second etching method is an etching method having an isotropic property.

In particular, the first etching method is a dry etching method, and the second etching method is a wet etching method.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION As shown in FIG.
When forming and printing the contact hole for the first contact hole, first, the opening 108 is formed by the dry etching method. By using the dry etching method here, it is possible to deal with a fine pattern. Particularly, since the interlayer insulating film 107 has a certain thickness of several thousand Å or more, it is effective to form the openings by the dry etching method.

Here, the interlayer insulating film 107 is made of a silicon nitride film and the insulating film 104 (gate insulating film) is made of a silicon oxide film.
Etching can be terminated when 04 is exposed. That is, the insulating film 104 made of a silicon oxide film can function as an etching stopper.

Thus, the state shown in FIG. 1C is obtained. Next, by using a wet etching method, the opening 109 can be formed and a contact hole reaching the source region 11 of the active layer 103 can be formed.

At this time, by reducing the film thickness of the insulating film 104, it is possible to suppress the problem caused by the demerit of isotropic etching. That is, it is possible to prevent the open hole from being greatly engraved.

Further, the etching damage to the active layer 103 can be suppressed, and the contact formed in a later step can be made reliable.

[0029]

【Example】

[Embodiment 1] This embodiment relates to a manufacturing process of a thin film transistor arranged in a pixel portion of an active matrix type liquid crystal display device.

1 to 3 show steps of manufacturing the thin film transistor of this embodiment. First, as shown in FIG. 1A, a silicon oxide film 300 is formed as a base film 102 on a glass substrate 101.
A film is formed to a thickness of 0 °. This silicon oxide film is plasma C
The film is formed by the VD method or the sputtering method.

As the substrate, in addition to the glass substrate 101, a quartz substrate or a substrate (for example, a semiconductor substrate) on which an appropriate insulating film is formed can be used. Further, in an integrated circuit having a multilayer wiring or a multilayer structure, an appropriate insulating film can be used as a base.

A silicon oxynitride film may be used as the base film 102. The silicon oxynitride film can be formed by a plasma CVD method using silane, oxygen, and N ₂ O.

Next, a silicon film (not shown) for forming an active layer of the thin film transistor is formed later. here,
A 500Å thick amorphous silicon film is formed by plasma CVD. As a method for forming the amorphous silicon film, a low pressure thermal CVD method may be used.

Then, heat treatment and laser light irradiation are performed to crystallize the amorphous silicon film to obtain a crystalline silicon film (not shown).

After obtaining the crystalline silicon film, patterning is performed to form the active layer 103 of the thin film transistor. Then, the silicon oxide film 104 that functions as a gate insulating film
A film is formed to a thickness of 00Å by the plasma CVD method.

This silicon oxide film 104 also functions as an etching stopper when a contact hole is formed later.

A silicon oxynitride film can be used as the gate insulating film. However, it is preferable to use a silicon oxide film in order to increase the difference in etching rate from that of the interlayer insulating film (which will later be composed of a silicon nitride film).

Further, a silicide material for forming a gate electrode is formed and further patterned to form a gate electrode 105 and a scanning line (also called a gate line) 106. Generally, the gate electrode 105 is provided so as to extend from the scanning line 106.

As a material for forming the gate electrode and the scanning line, a material selected from silicon doped with impurities at a high concentration to reduce resistance, various silicide materials, and metal materials typified by aluminum and molybdenum are used. You can

Thus, the state shown in FIG. 1A is obtained. In this state, impurity ions are implanted to form a source region and a drain region. Here, P (phosphorus) ions are implanted by a plasma doping method in order to manufacture an N-channel thin film transistor.

After the implantation of the impurity ions, laser light or strong light irradiation is performed to anneal and activate the region where the impurity ions are implanted. This step may utilize a method by heating.

In this way, the source region 11, the drain region 13 and the channel forming region 12 are formed in a self-aligned manner.

Next, as shown in FIG. 1B, a silicon nitride film is formed as the first interlayer insulating film 107 to a thickness of 3000 Å by the plasma CVD method. The thickness of this silicon nitride film is about 3000 to 5000Å.

Next, a contact hole 108 is formed in the first interlayer insulating film 107 by using the dry etching method. (Fig. 1 (C))

The dry etching in this step uses the RIE method (reactive ion etching method) using a mixed gas of CF ₄ and O ₂ as an etching gas. In this dry etching, by adjusting the conditions, the ratio of the etching rates of the silicon nitride film and the silicon oxide film can be set to about 5: 1. That is, the etching rate of the silicon nitride film is 5% higher than that of silicon oxide.
It can be doubled.

As described above, the silicon nitride film 107 to be etched and the silicon oxide film 104 existing as a base thereof are formed.
And a large selection ratio can be obtained. That is, the etching rate of the silicon oxide film can be made relatively small as compared with the etching rate of the silicon nitride film. Then, the silicon oxide film 104 can function as an etching stopper.

In this step, it is possible to obtain the significance that the contact can be formed in the fine pattern obtained by the dry etching method, and at the same time, it is possible to prevent the etching damage to the active layer.
(The etching can be stopped before the etching reaches the active layer 103)

Thus, the state shown in FIG. 1C is obtained. In this state, the silicon oxide film 104 is shown as if it has not been etched at all, but in reality, the etching has progressed to some extent.

Next, by wet etching, the contact hole 1 extending from 108 to the silicon oxide film 104.
09 is formed. In other words, the contact hole 108
Is further etched (the silicon oxide film 104 is exposed), and subsequently a contact hole 109 is formed.

Here, wet etching is performed using an etchant in which hydrofluoric acid, ammonium fluoride and a surfactant are mixed.

The method using the wet etching method has a great significance that the active layer is hardly damaged. Further, since the thickness of the silicon oxide film 104 is not as thick as 1000 Å (thinner as compared with the interlayer insulating film), the problem caused by isotropic etching does not pose a problem.

The contact hole 109 can be formed by removing the silicon oxide film 104 without using a mask. That is, contact hole 1
The resist mask used for forming 08 can be used as it is.

Further, even if there is no resist mask, the opening 109 can be formed in a self-aligned manner by utilizing the contact hole 108 already formed.

Generally, for a hydrofluoric acid type etchant, the etching rate of the silicon nitride film is about 1/10 or less as compared with the etching rate of the silicon oxide film.
In the above steps, etching of the silicon nitride film poses almost no problem.

Thus, the state shown in FIG. 1D is obtained.
By doing this, it is possible to respond to miniaturization,
Moreover, there is no etching damage to the active layer 103, and the contact hole 109 can be formed by a method that does not complicate the manufacturing process.

After obtaining the state shown in FIG. 1D, a source wiring 110 that contacts the source electrode or the source region is formed using an appropriate metal material. Thus, FIG.
The state shown in FIG.

Next, a silicon nitride film is formed as the second interlayer insulating film 111 by plasma CVD to a thickness of 3000 Å. The thickness of the silicon nitride film forming the second interlayer insulating film may be selected from 2000Å to 5000Å.
(FIG. 2 (B))

Next, contact holes are formed in the first interlayer insulating film 107 and the second interlayer insulating film 111 by dry etching. (Fig. 2 (C))

The conditions of this dry etching are shown in FIG.
It is performed under the same conditions as the formation of the contact hole 108 shown in (C). However, since the thickness to be etched is different, it is necessary to perform a preliminary experiment to determine the etching time.

Also in this step, the first interlayer insulating film 1 in which the etching rate of the silicon oxide film 104 is the silicon nitride film
07 and the second interlayer insulating film 111, the silicon oxide film 104 can function as an etching stopper because it is small.

Thus, the state shown in FIG. 2C is obtained. Then, the silicon oxide film 104 exposed at the bottom of the contact hole 112 is etched by a wet etching method. In this way, the contact hole 113 is formed. (Fig. 2 (D))

This wet etching process is shown in FIG.
The conditions are the same as those in the step shown in (D).

After obtaining the state shown in FIG.
As shown in (A), an ITO film for forming a pixel electrode is formed by a sputtering method, and further patterned to form a pixel electrode 114.

Further, a final protective film 115 is formed. The protective film 115 is composed of a silicon oxide film.

Although not shown, an alignment film for aligning the liquid crystal is formed on the protective film 115, and an alignment treatment is further performed.

Thus, the thin film transistor arranged in the pixel portion of the active matrix type liquid crystal display device is completed. This thin film transistor has a structure capable of surely making contact with the source and drain regions. In addition, a manufacturing method that can cope with the miniaturization is adopted. Further, it has the significance that the above steps can be realized without particularly complicating the manufacturing process.

[Embodiment 2] This embodiment shows an example in which an LDD (lightly doped drain) region is arranged in a thin film transistor in the structure shown in Embodiment 1. 4 to 6 show the manufacturing process of this embodiment. The manufacturing conditions and details of the portions common to the first embodiment are the same as those in the first embodiment.

First, a silicon oxide film 402 is formed as a base film on a glass substrate 401 to a thickness of 3000 Å. Then, an amorphous silicon film (not shown) is formed by the plasma CVD method. Further, the amorphous silicon film is crystallized by a method using both heat treatment and laser light irradiation to obtain a crystalline silicon film (not shown).

By patterning the above-mentioned crystalline silicon film, an island-shaped region which will be an active layer of a thin film transistor after that shown by 403 in FIG. 4A is formed.

After forming the active layer 403, a silicon oxide film 404 functioning as a gate insulating film is formed by plasma CVD to a thickness of 1000 Å. The silicon oxide film also functions as an etching stopper in the contact hole forming process to be performed later.

Further, an aluminum film (not shown) forming the gate insulating film is formed to a thickness of 4000 Å by the sputtering method.

This aluminum film contains scandium in an amount of 0.1% by weight in order to prevent hillocks and whiskers from being generated in the subsequent steps. Hillocks and whiskers are a phenomenon in which needle-shaped or pin-shaped protrusions are formed due to abnormal growth of aluminum in the heating process.

After forming an aluminum film (not shown),
The gate electrode 405 is formed by patterning. At the same time, the scan line 406 is formed.

Next, anodic oxidation is performed to form porous anodic oxide films 407 and 408. The porous anodic oxide films 407 and 408 are
It is formed by performing anodic oxidation using the patterns 405 and 406 made of aluminum with platinum as a cathode and as an anode. Here, an aqueous solution containing 3% of oxalic acid is used as the electrolytic solution.

In this anodizing step, by controlling the anodizing time, it is possible to grow a porous anodized film up to about several μm. Here, 5000Å
This porous anodic oxide film is grown to a thickness of.

Next, an anodic oxidation is performed again using an ethylene glycol solution containing 3% tartaric acid as an electrolytic solution. In this step, anodic oxide films 409 and 410 are formed. This anodic oxide film has a dense barrier type film quality.

Anodized film 409 having this dense film quality
And 410 can control their growth distance by the applied voltage. Here, the film thickness is 700 Å.
This anodic oxide film can grow up to about 3000 Å.

When the thickness of the dense anodic oxide film is increased, the offset gate region can be formed later by the thickness. In order to form an effective offset gate region, the film thickness of this dense anodic oxide film should be 2
It is necessary to be 000Å or more.

The anodic oxide film 4 having this dense film quality
The electrolytic solutions 09 and 410 are formed in the state shown in FIG. 4A because the electrolytic solution enters the porous anodic oxide film.

After obtaining the state shown in FIG. 4A, the exposed silicon oxide film 404 is removed. Further, by using a mixed acid composed of acetic acid, nitric acid and phosphoric acid, a porous anodic oxide film 407 is formed.
And 408 are selectively removed.

Next, impurity ions are implanted. Here, P ions are implanted in order to form an N-channel thin film transistor. In this step, the source region 41, the channel formation region 42, and the low concentration impurity region 43
(LDD region) and drain region 44 are formed in a self-aligned manner. (FIG. 4 (B))

After the above-mentioned impurity ion implantation, laser light or intense light irradiation is performed to anneal and activate the region into which the impurity ions have been implanted.

Then, a first interlayer insulating film is formed. This first interlayer insulating film has a two-layer structure. Specifically, it is composed of a 500 Å thick silicon oxide film 411 and a 3000 Å thick silicon nitride film 412.

First, a 500 l thick silicon oxide film 411 is formed by plasma CVD. Further, a 3000 Å thick silicon nitride film 412 is formed by plasma CVD. Thus, the first interlayer insulating film is obtained. The silicon oxide film 411
The film thickness of is preferably not more than 1/5 of the film thickness of the silicon nitride film 412.

The silicon oxide film 411 functions as an etching stopper in a contact hole forming process which will be performed later.

Thus, the state shown in FIG. 4B is obtained. Next, a contact hole 413 is formed by a dry etching method.
To form This dry etching is performed by the same method as that shown in the first embodiment. (FIG. 4 (C))

In the step of forming the contact hole 413, since the silicon oxide film 411 functions as an etching stopper, it is possible to prevent the active layer 403 from being damaged during dry etching.

Thus, the state shown in FIG. 4C is obtained. Further, a contact hole 414 is formed in the silicon oxide film 411 by wet etching. In this step, it is not necessary to use a new mask. Since the silicon oxide film is as thin as 1000 Å, the problem of side etching, which is a problem in isotropic etching, is not a special problem.

Thus, the state shown in FIG. 4D is obtained. Next, as shown in FIG. 5A, a source wiring 415 which is in contact with the source electrode 415 or the source region is formed.
In this embodiment, this electrode or wiring is composed of a laminated film of a titanium film, an aluminum film and a titanium film.

Next, 300 is formed as the second interlayer insulating film 416.
A 0Å thick silicon nitride film is formed by the plasma CVD method. (FIG. 5 (B))

Next, a contact hole 417 is formed through the silicon nitride films 412 and 416 by dry etching. (FIG. 4 (C))

In this step, the silicon oxide film 411 functions as an etching stopper. Therefore, as a result of this step, the state shown in FIG.

Next, by wet etching, the contact hole 418 reaching the drain region 44 is formed.
To form

In this step, since the thickness of the silicon oxide film 411 is 500 Å, the contact hole 418 can be formed with almost no problem of side etching. Further, when forming the contact hole 418, there is a significant significance in the process that no new mask is required.

417 reaching the drain region 44
Since most of the contact holes indicated by 418 and 418 are formed by dry etching, it is possible to sufficiently cope with the miniaturization of the pattern.

Thus, the state shown in FIG. 5D is obtained. In this way, a contact hole reaching the drain region 44 can be formed through the first and second interlayer insulating films.

Next, an ITO film which constitutes the pixel electrode is formed and further patterned to form the pixel electrode 419. (FIG. 6 (A))

Then, a silicon oxide film 420 is formed as a final protective film to obtain the state shown in FIG. 6 (B).

In the thin film transistor shown in this embodiment, a low concentration impurity region 43 having a function of relaxing the electric field strength between the channel forming region 42 and the drain region 44 is arranged between the two regions. This region is usually called an LDD region and is effective for reducing the OFF current value.

The thin film transistor described in this embodiment can have an excellent property of retaining the electric charge accumulated in the pixel electrode 419, and is useful in displaying a higher image quality.

By adopting the structure shown in this embodiment, it is possible to make reliable contact with the source region and the drain region.

[Embodiment 3] This embodiment relates to a structure in which a black matrix is arranged on the TFT panel substrate side. FIG. 7 shows a manufacturing process of this example. First, the glass substrate 701
A silicon oxide film or a silicon oxynitride film is formed thereover as a base film 702.

Next, an active layer made of a crystalline silicon film is formed. In FIG. 7A, island-shaped regions 703 to 705 are active layers. Next, a silicon oxide film is formed as a gate insulating film 706. Further, a gate electrode 707 and a scanning line (gate line) 708 are formed using a metal material or a silicide material.

By implanting impurity ions in this state, a source region 705, a drain region 703 and a channel forming region 704 are formed.

Further, a silicon nitride film is formed as the first interlayer insulating film 709. Then, the first interlayer insulating film 709
Forming a contact hole. This step is performed according to the method described in Example 1. That is, first, an opening up to the silicon oxide film 706 is formed by a dry etching method, and then a contact hole reaching the source region 705 is formed by a wet etching method.

After that, the source electrode or the source wiring 710 is formed with an appropriate metal material. Further, a silicon nitride film is formed as the second interlayer insulating film 711.

Thereafter, the drain region 7 is formed by a method combining dry etching and wet etching.
A contact hole 712 reaching 03 is formed. Thus, the state shown in FIG. 7A is obtained.

After obtaining the state shown in FIG. 7A, a material (not shown) forming BM (black matrix) is deposited. As a material forming the BM, a titanium film, a chromium film, or a laminated film of a titanium film and a chromium film can be used.

Then, the film made of the material forming the BM is patterned to form the BMs 713 and 715. At the same time, the drain region 703
An electrode 714 that contacts the substrate is formed. That is, the electrode 7
14 is composed of the material forming BM. (FIG. 7
(B))

After obtaining the state shown in FIG. 7B, a silicon oxide film or a silicon nitride film is formed as the third interlayer insulating film 716. Further, a contact hole reaching the electrode 714 is formed. This contact hole is formed by the electrode 714.
Serves as an etching stopper, so a method using dry etching may be used.

Next, a pixel electrode 717 made of ITO is formed. Then, a silicon oxide film is formed as the final protective film 718. (FIG. 7 (C))

[Embodiment 4] This embodiment relates to a structure in which a BM is arranged on the TFT substrate side with a structure different from that of the third embodiment. First, a silicon oxide film 702 is formed as a base film on the glass substrate 701. Further, active layers 703 to 705 are formed. Further, a silicon oxide film 706 which functions as a gate insulating film is formed.

Then, the gate electrode 707 and the scanning line 708 are formed by using an appropriate metal material or silicide material. Further, a silicon nitride film is formed as the first interlayer insulating film 709. Next, the first interlayer insulating film 70 is formed using a method combining dry etching and wet etching.
A contact hole is formed at 9. Here, contact holes are formed in the source region 705 and the drain region 703, respectively.

Also in this step, the first interlayer insulating film 70 is formed.
In the dry etching for 9, the silicon oxide film 70
6 can function as an etching stopper. That is, by making the silicon oxide film 706 function as an etching stopper, damage to the source region 705 and the drain region 703 can be prevented.

After forming contact holes in the first interlayer insulating film 709, the source electrode 710 and the drain electrode 800 are formed. The two electrodes are formed of the same constituent material.

Next, as a second interlayer insulating film 711, a silicon oxide film or a silicon nitride film is formed. Then, a contact hole 801 is formed in the second interlayer insulating film by dry etching. In this process, the electrode 800
Functions as an etching stopper.

Thus, the state shown in FIG. 8A is obtained. Next, a material forming the BM is formed into a film and then patterned to form parts 713 and 715 functioning as BM and a part 804 functioning as an electrode. (Fig. 8 (B))

Next, a silicon oxide film or a silicon nitride film is formed as a third interlayer insulating film 716. Further, a contact hole reaching the electrode 804 is formed, and a pixel electrode 717 is formed using ITO. After forming the pixel electrode, a silicon oxide film 718 is formed as a final protective film. (FIG. 8
(C))

(Embodiment 5) This embodiment relates to a structure in which a BM is arranged on the TFT substrate side and the pixel electrode is in direct contact with the drain region.

FIG. 9 shows the manufacturing process of this embodiment. First, a silicon oxide film 902 is formed as a base film on the glass substrate 901. Further, an active layer indicated by 903 to 905 is formed with a crystalline silicon film. Further, a silicon oxide film 90 which functions as a gate insulating film is formed.

Then, the gate electrode 906 and the scanning line 907 are simultaneously formed by using an appropriate metal material or silicide material. Further, a silicon nitride film is formed as the first interlayer insulating film 908.

After forming the first interlayer insulating film 908, a contact hole to the source region 903 is formed by a combination of dry etching method and wet etching method, and further the source electrode 909 is made of an appropriate metal material.
To form

After forming the source electrode 909, a silicon nitride film is formed as the second interlayer insulating film 910. Thus, the state shown in FIG. 9A is obtained.

When the state shown in FIG. 9A is obtained, the BM film 9
11 and 912 are formed. The BM film is composed of a titanium film, a chromium film, and a laminated film thereof. Thus, the state shown in FIG. 9B is obtained.

After obtaining the state shown in FIG. 9B, a silicon oxide film or a silicon nitride film 913 is formed as a third interlayer insulating film. Next, the contact hole 914 is formed.

The contact hole is formed by first forming the first interlayer insulating film 908 and the second interlayer insulating film 908 by a dry etching method.
The interlayer insulating film 910 and the third interlayer insulating film 913 are partially removed, and contact holes are formed therein.

In this state, since the silicon oxide film 90 serves as an etching stopper, the etching can be finished when the silicon oxide film 90 is exposed.

By using the wet etching method, the silicon oxide film 9 exposed at the bottom of the opening is formed.
Remove 0. In this way, the contact hole 914
To form Thus, the state shown in FIG. 9C is obtained.

Next, the pixel electrode 915 is formed with ITO. Further, a silicon oxide film is formed as the final protective film 916.

[0130]

By utilizing the invention disclosed in this specification, it is possible to provide a method for manufacturing a thin film transistor which can surely make contact with the active layer of the thin film transistor and can realize miniaturization. it can. At the same time, the above significance can be obtained without complicating the manufacturing process.

By utilizing the invention disclosed in this specification, a liquid crystal panel having a highly fine pattern can be obtained. At the same time, the problem of contact failure caused by using the dry etching method can be solved. Further, since the process is not complicated, it is possible to form a good contact and obtain a high production yield.

[Brief description of drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.

FIG. 2 illustrates a manufacturing process of a thin film transistor.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 illustrates a manufacturing process of a thin film transistor.

5A to 5C are diagrams illustrating a manufacturing process of a thin film transistor.

6A to 6C are diagrams illustrating a manufacturing process of a thin film transistor.

FIG. 7 illustrates a manufacturing process of a thin film transistor.

8A to 8C are diagrams illustrating a manufacturing process of a thin film transistor.

9A to 9C are diagrams illustrating a manufacturing process of a thin film transistor.

[Explanation of symbols]

 101 glass substrate 102 base film (silicon oxide film) 103 active layer (crystalline silicon film) 104 gate insulating film (silicon oxide film) 105 gate electrode 106 scanning line (gate line) 107 first interlayer insulating film 108, 109 contact Hole 110 Source electrode or source wiring 111 Second interlayer insulating film 112, 113 Contact hole 114 Pixel electrode 115 Final protective film (silicon oxide film)

Claims (8)

[Claims] 1. An active layer made of a semiconductor, a first insulating film formed on the active layer, and a second insulating film formed on the first insulating film. Forming a hole in the second insulating film by a dry etching method using the first insulating film as an etching stopper; and etching the first insulating film exposed at the bottom of the opening by a wet etching method. And a step of forming an opening reaching the active layer, the method for manufacturing a semiconductor device. 2. The active layer according to claim 1, wherein the active layer is formed of a silicon film, the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. Method for manufacturing semiconductor device 3. The silicon oxide film according to claim 2, wherein the film thickness is 5
A method for manufacturing a semiconductor device, which is less than 00Å. 4. An active layer made of a semiconductor, a first insulating film formed on the active layer, and an N layer insulating film formed on the first insulating film. Forming a hole in the N-layer insulating film by a dry etching method using the first insulating film as an etching stopper; etching the first insulating film exposed at the bottom of the opening by a wet etching method And a step of forming an opening reaching the active layer, the method for manufacturing a semiconductor device. 5. The active layer according to claim 4, wherein the active layer is composed of a silicon film, the first insulating film is a silicon oxide film, and each of the N insulating films is a silicon nitride film. Method for manufacturing semiconductor device 6. A first etching comprising: an active layer, a silicon oxide film formed on the active layer and functioning as a gate insulating film, and a silicon nitride film formed on the silicon oxide film. Forming a hole in the silicon nitride film by a method and exposing the silicon oxide film at the bottom thereof; and forming a hole in the silicon oxide film exposed at the bottom of the hole by a second etching method A step of exposing the active layer, and a method of manufacturing a semiconductor device. 7. The semiconductor device according to claim 6, wherein the first etching method is an etching method having a vertical anisotropy, and the second etching method is an isotropic etching method. Manufacturing method. 8. The method for manufacturing a semiconductor device according to claim 6, wherein the first etching method is a dry etching method and the second etching method is a wet etching method.