JP3260975B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming wiring and contact holes in a semiconductor integrated circuit or the like. The present invention relates to a wiring using a material containing aluminum as a main component (aluminum-based material). In the present invention, even if not otherwise specified, the expression “aluminum” includes the case where a trace amount of an additive is present.

[0002]

2. Description of the Related Art A material mainly composed of aluminum (aluminum-based material) is used for wiring of a semiconductor integrated circuit, and the surface of the aluminum-based material is anodized to form an anodic oxide film on the surface. A technique of increasing the strength of the aluminum-based material is known.
The aluminum-based material is added with a material such as silicon, copper, or scandium as needed according to heat resistance or the like, but is generally weak to heating. That is, abnormal heating (hillocks) of the crystal occurs by heating at several hundred degrees Celsius.

[0003] Such hillocks reduce the coverage of an insulator (interlayer insulator) provided between upper and lower wirings and cause a short circuit. Unfortunately, the step in which hillocks occur is often the step of forming an interlayer insulator. Usually, the interlayer insulating material is an atmospheric pressure CVD method, a low pressure CVD method.
And a vapor phase growth method such as a plasma CVD method. In such a film forming method, it is necessary to heat the substrate to an appropriate temperature. Generally, as the heating temperature is higher, an interlayer insulating film having better step coverage can be obtained. However, when an aluminum-based material wiring (hereinafter, referred to as an aluminum wiring) is exposed to a high temperature, hillocks are generated as described above. As a result, it has been difficult to form an interlayer insulating film having good step coverage.

When the dense and strong anodic oxide film is formed on the surface of the aluminum wiring by anodic oxidation, the above problems can be largely solved. That is, the anodic oxide inhibits deformation of the aluminum wiring inside and suppresses abnormal growth of the crystal. Therefore, the aluminum wiring covered with the anodic oxide was able to withstand film formation at a relatively high temperature. It has also been proposed to use an anodic oxide formed on the side surface to use it as a mask during doping. In this case,
A structure in which the region to be doped is away from aluminum by the thickness of the anodic oxide film (offset structure) can be obtained.

[0005]

However, the aluminum anodic oxide film (ie, aluminum oxide) formed for such a purpose is generally difficult to etch. Particularly preferred anodic oxide for hillock prevention is what is called a barrier type anodic oxide,
It was obtained by performing anodization by applying a high voltage in a neutral electrolytic solution, and was characterized by being dense and hard. Further, as described above, in order to suppress hillocks, it is necessary that the thickness of the anodic oxide film is 500 ° or more. Because of this dense, hard and thick feature,
Until now, there was no suitable etchant. Until now, a hydrofluoric acid-based etchant (such as a buffered hydrofluoric acid such as a mixture of hydrogen fluoride and ammonium fluoride) for etching silicon oxide and the like has been used because of the necessity of opening contact holes. , The etching was performed after the etching of the interlayer insulator was completed. However, with the hydrofluoric acid-based etchant, the surface of the aluminum wiring was significantly damaged, and as a result, a contact failure was likely to occur. (FIG. 6a)

In addition, since the etching rate of aluminum oxide is significantly lower than that of silicon oxide, the contact hole spreads laterally in the region of the interlayer insulator at the end of the etching, and becomes larger than the expected contact hole. Was. (FIG. 6B) Further, the hydrofluoric acid-based etchant etches not only silicon oxide but also a silicon semiconductor.
When the formation of the contact hole on the silicon semiconductor film and the formation of the contact hole on the aluminum wiring are performed simultaneously, there is also a problem that the silicon semiconductor film is etched when the formation of the contact hole on the aluminum wiring is completed. . (C in FIG. 6) These problems were the same when the interlayer insulator was silicon nitride. The present invention has been made in view of such a situation, and discloses an appropriate etching method, and proposes a more advanced semiconductor integrated technology.

In addition, heretofore, the anodic oxide coating has only been used as a mask material for preventing hillocks and obtaining an offset structure. The anodic oxide coating, particularly in the barrier type anodic oxide, has hardly been used for its characteristics of high withstand voltage and high dielectric constant, in addition to its characteristic of being dense and hard. Such features were suitable for producing capacitors in integrated circuits. The present invention also discloses a technique for forming a capacitor utilizing such characteristics.

[0008]

In order to solve the above-mentioned problems, it is necessary to separate the etching process of silicon oxide or silicon nitride as an interlayer insulator from the etching process of aluminum oxide as an anodic oxide. It is. The basic configuration of the present invention will be described below with reference to FIG. First, aluminum wirings 101 and 102 are present on a substrate, and the surfaces thereof are covered with anodic oxide films 103 and 104, respectively. An interlayer insulator 105 made of silicon oxide or silicon nitride is provided so as to cover them.
(Fig. 1 (A))

A photoresist 106 is applied to the entire surface, and the opening pattern 1 is formed by a known photolithography method.
07 and 108 are formed. (FIG. 1B) Thereafter, the opening is etched with a hydrofluoric acid-based etchant. In this case, the etching may be completed at the stage when the interlayer insulator is etched. This step may be performed by a dry etching method.
It is known that aluminum oxide is hardly etched by a known dry etching method.
For this reason, the etching of the interlayer insulating material may be performed slightly. In particular, anisotropic etching is preferable because there is no side etching due to overetching. (Fig. 1 (C))

As a result, the opening 1 is formed on the aluminum wiring.
09 and 110 are formed. (FIG. 1D) Thereafter, a photoresist 111 is applied again on the entire surface, and the opening pattern 11 is formed by photolithography.
Form 2 In this case, as shown in the drawing, the size of the opening pattern 112 is preferably smaller than the size of the opening 109. Also, as shown in the opening 110 of the aluminum wiring 102 in the drawing, the opening provided in the previous step may not be provided with the opening pattern in this step. (FIG. 1 (E))

Thereafter, the opening pattern 112 is formed by an etchant for selectively etching aluminum oxide.
Anodic oxide film 103 is etched. At this time, if the size of the opening pattern 112 is equal to or larger than the size of the opening 109, the etching of the anodic oxide proceeds in the horizontal direction, and the step is undesirably increased. (FIG. 1 (F)) As a result, the contact hole 11 is
3 is formed. At this time, since the final contact hole 113 is just inside the opening 109, the step is gentle. (Fig. 1 (G))

Thereafter, the upper wirings 114 and 1 are formed of a metal material.
15 are formed. Regarding the contact hole 113,
Since the step is gentle, it is effective in preventing the disconnection of the wiring 114. In this case, in the region 116, the wiring 101 and the upper wiring 114 are in contact with each other through the contact hole 113, but in the region 117, the wiring 102
An anodic oxide film is present between the upper wiring 115 and the upper wiring 115, and this serves as a dielectric to form a capacitance (capacitor). As described above, according to the present invention, not only the formation of the contact hole but also the formation of the capacitor can be performed. (Fig. 1 (H))

Although not shown in the drawings, a contact hole formed in another material such as a silicon semiconductor can be formed in parallel with the present invention.
At this time, for example, an opening pattern is formed on the silicon semiconductor in the step of FIG. 1B, and in the step of FIG.
The interlayer insulator 105 may be etched to form a contact hole over the silicon semiconductor.

An important factor in the present invention is an etchant for selectively etching aluminum oxide. For this purpose, for example, a solution in which chromic anhydride and caustic soda are added by a few percent to a mixture of phosphoric acid and water is known. However, since this solution contains an alkali element, it is not suitable for use in manufacturing a semiconductor integrated circuit. In addition, since this solution is rich in water, heating during the etching process (typically 65 ° C.)
), Moisture evaporates, and the composition tends to change. For this reason, in a semiconductor manufacturing process that requires control at a level of several hundred millimeters, there is a problem in terms of reproducibility and stability, and there is a problem that practicability is extremely low.

As an etchant for compensating for such a defect, a solution containing at least phosphoric acid, acetic acid and nitric acid and containing chromic acid is suitable. In particular, in the above configuration, the volume mixing ratio is from 40 to 90 for phosphoric acid.
Acetic acid 10 to 100 and nitric acid 1 to 40 are good. Further, in the above configuration, chromic acid may be contained in the solution in an amount of 1 to 1
0% by weight may be added.

When the solution having the above structure is used as an etchant, only the anodic oxide film formed on the surface of a material containing aluminum as a main component can be selectively etched, and other materials such as silicon oxide, Silicon nitride,
Does not attack aluminum, silicon semiconductors, etc. Chromic acid is an oxidizing agent represented by CrO ₃ . When such an etchant is used, the etching is performed at 50 ° C.
It is desirable to carry out at the above temperature. This is to ensure a constant or higher etching rate. Generally, it is desirable to carry out at a temperature of 50C to 200C. A material generally called an oxidizing agent can be used instead of chromic acid. For example, a material represented by Fe ₂ O ₃ can be used.

[0017]

According to the present invention, good contact holes can be formed in aluminum wiring covered with anodic oxide. In addition, a capacitor can be formed using an anodic oxide. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0018]

【Example】

Embodiment 1 FIG. 2 shows this embodiment. First, the substrate 201
(Corning 7059, 10 mm × 10 mm) and a silicon oxide film 202 as a base oxide film of 1000 to 5000
A film was formed to a thickness of, for example, 4000 by plasma CVD.

Next, the amorphous silicon film is
A film was formed to a thickness of 500 °, for example, 800 ° by a plasma CVD method, and the film was crystallized by heating. Thus, a silicon semiconductor film having crystallinity was obtained. At the time of the heating step, a minute amount of a catalyst material for promoting crystallization of amorphous silicon such as nickel may be added. The crystallization may be performed by irradiation with a laser beam or an equivalent strong light. Furthermore, heating and intense light irradiation may be used in combination.

Next, an island-shaped crystalline silicon film is formed in the form of an active layer of the thin film transistor, and an active layer for forming a TFT is obtained. Further, a silicon oxide film to be the gate insulating film 203 was formed to a thickness of 1000 ° by a plasma CVD method. Next, an aluminum film containing 0.3% by weight of scandium was formed to a thickness of 5000 ° by a sputtering method.
This was patterned to form a gate electrode 205 and gate wirings 204 and 206. In this state, the gate electrode 205 and the gate wirings 204 and 206 are electrically connected, but it is not necessary that the gate wirings 204 and 206 be finally connected to the gate electrodes.

Next, the gate electrodes / wirings 204 to 206 were connected to the anode, and anodization was performed in an electrolytic solution to form dense oxide layers 207 to 209. This anodic oxide (aluminum oxide) film depends on the magnitude of the applied voltage, but needs to improve the device characteristics.
It is formed to a thickness of about 2500 °. In this step, an ethylene glycol solution containing 3% tartaric acid was used as an electrolytic solution and adjusted to a pH of about 7 with aqueous ammonia, and the voltage was gradually increased from 0 V and finally increased to 100 to 100 V.
This is performed by applying a voltage of 200V. In the process of increasing the voltage, the constant current method for keeping the flowing current constant is preferable.

Thereafter, an impurity (phosphorus in this case) is self-aligned in the island-like silicon region by ion doping using the gate electrode portion (gate electrode 205 and anodic oxide film 208 formed around it) as a mask. Injected.
The dose in this case is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / c.
m ² , the acceleration voltage is 60 to 90 kV, for example, 2 × 10 ¹⁵
Atomic atoms / cm ² and the accelerating voltage were 80 kV. As a result,
An N-type impurity region 210 into which phosphorus was introduced was formed. At this time, the anodic oxide 208 causes the N-type impurity region 2
The boundary 10 is formed at a position away from the gate electrode 205. That is, the gate electrode is in an offset state (offset gate structure). (Fig. 2 (A))

Next, a silicon oxide film 211 having a thickness of 3000 to 8000 °, for example, 5000 ° was formed as an interlayer insulating film by a plasma CVD method. (FIG. 2B) Then, the interlayer insulating film 211 and the gate insulating film 203 are etched to form contact holes 213 in the opening portions 212 and 215 and the source / drain regions 210.
214 were formed. Here, a dry etching method was used. Therefore, the anodic oxide 20 on the aluminum wiring
7 to 209 were hardly etched. In this step, a wet etching method may be used. (Figure 2
(C))

Thereafter, a photoresist 216 was applied to the entire surface, and an opening pattern 217 was formed by a known photolithography method. This opening pattern is for forming a contact hole to the gate wiring 204. At this time, as shown in FIG.
The size of 17 needs to be smaller than the opening 212 described above. Further, the opening 215 of the gate wiring 206 shown in FIG.
No opening pattern was provided in this step. This is for forming a capacitor using the anodic oxide film 209 as a dielectric in the opening 215. (FIG. 2 (D))

Thereafter, an opening pattern 217 is formed by an etchant for selectively etching aluminum oxide.
, The anodic oxide film 207 was etched. At this time, if the size of the opening pattern 217 is equal to or larger than the size of the opening portion 212, the etching of the anodic oxide proceeds in the horizontal direction, so that the step becomes large and the step of forming the metal film later is performed. However, such a problem does not occur because the hole pattern 217 is completely fitted in the hole 212 as shown in this embodiment. As an etchant, chromic acid was added to a mixture of phosphoric acid 30, acetic acid 60 and nitric acid 10
Only the one added was used. Through the above steps, a contact hole was formed on the gate wiring 204.

Thereafter, an aluminum film was formed to a thickness of 5000 ° by a sputtering method, and this was etched to form upper metal wirings / electrodes 218 and 219. As described above, in the opening 212, the upper metal wiring 2
18 and the gate wiring 204 are connected.
In No. 5, a capacitor was formed between the upper metal wiring 219 and the gate wiring 206 using the anodic oxide film 209 as a dielectric. The N-type impurity region 210 is connected to the upper wiring 218 via the contact holes 213 and 214.
219. As described above, according to the present invention, not only the formation of the contact hole but also the formation of the capacitor could be performed. (FIG. 2 (E))

Embodiment 2 FIG. 3 shows this embodiment. This embodiment shows a manufacturing process of an active matrix circuit used for a liquid crystal display device. First, in the same manner as in Example 1, a silicon oxide film was formed as a base film on a substrate to a thickness of 2000 mm by a plasma CVD method. Next, an amorphous silicon film was formed to a thickness of 500 ° by a plasma CVD method. Then, the silicon film was crystallized by heating, laser light irradiation, or strong light irradiation. The crystallized silicon film is etched to form island-like silicon regions 30.
1 was formed. Thereafter, a silicon oxide film to be the gate insulating film 302 was formed to a thickness of 1200 ° by a plasma CVD method.

Next, aluminum was formed to a thickness of 5000 ° by a sputtering method. Then, the aluminum film is etched to form a gate electrode 304,
Aluminum wirings 303 and 305 were formed. afterwards,
The gate electrode 304, the aluminum wirings 303, 30
Using 5 as an anode, anodic oxidation was performed in an electrolytic solution to form a dense anodic oxide layer. This anodic oxide layer has a thickness of 1000
It was formed to a thickness of Å. (FIG. 3 (A))

Thereafter, the silicon nitride film 306 is formed by a plasma CVD method using an NH ₃ / SiH ₄ / H ₂ mixed gas.
Was formed in a thickness of 1000 °. Further, a silicon oxide film 307 is formed by a plasma CVD method using TEOS and oxygen.
Was formed. Here, the thickness of the silicon oxide film is a gate electrode,
It depends on the height of the aluminum wiring. For example, as in this embodiment, the gate electrode 304 and the aluminum wiring 3
03,305 height is about 6000Å including silicon nitride film
In the case of Å, 2000Å to 1.2 μ which is 1/3 to 2 times that
m is preferred. Here, it was set to 6000 °. (FIG. 3
(B))

Next, this silicon oxide film 3 is subjected to anisotropic dry etching by a known RIE method.
07 was performed. By utilizing the difference between the etching rates of the silicon oxide film and the silicon nitride film, and by monitoring the composition of the etched gas,
This etching was terminated when the etching reached the silicon nitride film 306. Through the above steps, substantially triangular insulators (sidewalls) 308 to 31 are provided on the side surfaces of the gate electrode 304 and the aluminum wirings 303 and 305.
0 remained.

Then, an impurity (here, phosphorus) was implanted into the island-shaped silicon region 301 in a self-aligned manner by using the gate electrode portion as a mask by an ion doping method. In this case, the dose is 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms cm ² , and the acceleration voltage is 60 to 90 kV, for example, 1 × 10 ¹⁵ atoms / c.
m ² and the acceleration voltage were 80 kV. As a result, N-type impurity regions 311 and 312 into which phosphorus was introduced were formed. At this time, under the anodic oxide, the silicon nitride film, and the side wall of the gate electrode, phosphorus was not doped, and an offset region having a width of the thickness x was formed. (FIG. 3 (C))

Next, a silicon oxide film 313 was formed to a thickness of 5000 ° by plasma CVD as an interlayer insulating film. Then, the interlayer insulating film 313, the silicon nitride film 306, and the gate insulating film are etched, and the opening portions 314, 311 are formed.
17 and contact holes 315 and 316 to the source / drain regions 311 and 312 were formed. here,
The silicon oxide film and the silicon nitride film were etched using a hydrofluoric acid-based etchant. At this time, since the etching was terminated when the interlayer insulator, the silicon nitride film, and the gate insulating film were almost completely removed, the anodic oxide on the aluminum wiring was not etched as in Example 1. (FIG. 3 (D))

Thereafter, a photoresist is applied to the entire surface,
The opening 314 on the aluminum wiring 303 obtained in the previous step by a known photolithography method.
Further, an opening pattern was formed inside the. In this case, the size of the opening pattern is smaller than the size of the opening 314. Further, the opening 317 on the aluminum wiring 305 is formed.
Was not provided with an opening pattern. Thereafter, phosphoric acid 30 and acetic acid 6 for selectively etching aluminum oxide
The anodic oxide film was etched in accordance with the opening pattern using an etchant obtained by adding only 3 chromic acid to a mixed solution of 0 and 10 of nitric acid. As a result, a contact hole 318 was formed on the aluminum wiring. At this time, the final contact hole is just the opening 314.
, The step was gentle. (FIG. 3
(E))

Then, ITO (indium tin oxide)
Is formed by sputtering, and this is etched,
The pixel electrode 321 of the liquid crystal display device covers the opening 317.
Was formed. Here, an anodic oxide film was present between the aluminum wiring 305 and the pixel electrode 321, which served as a dielectric, and a capacitor was formed in the region 323. Thereafter, an aluminum film is formed to a thickness of 5000 ° by a sputtering method, and this is etched.
Upper wiring / electrodes 319 and 320 were formed. Region 322
Then, the aluminum wiring 303 is in contact hole 31
8 to the upper wiring 319. Further, the pixel electrode 321 was connected to the upper wiring 320. (FIG. 3
(E))

An outline of an active matrix circuit used in a liquid crystal display device or the like is shown in FIG. Basically, the current flowing into and out of one pixel 2 is controlled by the transistor 1. However, since the capacity of the pixel is small, an auxiliary capacitor 3 is usually provided for the purpose of reinforcing it. The capacitance formed in the region 323 of FIG. 3 is used for such a purpose. The storage capacitor 3 may be connected to the gate wiring of the pixel below it as shown in FIG.
As shown in (B), a wiring 4 dedicated to an auxiliary capacitor may be separately provided.

Embodiment 3 FIG. 4 shows this embodiment. This embodiment shows a manufacturing process of an active matrix circuit used for a liquid crystal display device. First, a silicon oxide film was formed as a base film to a thickness of 2000 mm on a substrate by a sputtering method. Next, an amorphous silicon film was formed to a thickness of 500 ° by a plasma CVD method and crystallized by means such as heating. Then, the crystallized silicon film was etched to form an island-shaped silicon region. afterwards,
A silicon oxide film to be the gate insulating film 403 was formed to a thickness of 1000 ° by a plasma CVD method.

Next, in the same manner as in Example 2, a gate electrode 405 and an aluminum wiring 404 and 406 each having an anodic oxide with a thickness of 1000 ° on the upper surface and side surfaces were formed. Further, a silicon nitride film having a thickness of 1000 .ANG.
5, formed on side surfaces of aluminum wirings 404 and 406. Then, an impurity (phosphorus in this case) is implanted into the island-shaped silicon region in a self-aligned manner by using the gate electrode portion as a mask by an ion doping method.
402 was formed. (FIG. 4 (A))

Next, a silicon oxide film 408 is formed to a thickness of 5000 ° by a plasma CVD method as an interlayer insulating film.
Interlayer insulating film 408, silicon nitride film 407, gate insulating film 4
03 was etched to form contact holes 410 and 411 to the openings 409 and 412 and the source / drain regions 401 and 402. Here, since the silicon oxide film and the silicon nitride film were etched using a hydrofluoric acid-based etchant, the anodic oxide on the aluminum wiring was not etched. The contact hole 411 and the opening 412 are once filled with a silicon nitride film in a subsequent step. (FIG. 4 (B))

Thereafter, a photoresist is applied to the entire surface,
An opening pattern was formed inside the opening 409 obtained in the previous step by a known photolithography method. In this case, the size of the opening pattern is smaller than the size of the opening 409. In addition, no opening pattern was provided in the opening 412 of the aluminum wiring 406. After that, the anodic oxide film was etched by the same etchant as that used in Example 2 according to the opening pattern. As a result, a contact hole 413 was formed on the aluminum wiring. (FIG. 4 (C))

Thereafter, an aluminum film is selectively formed by 500
A film was formed to a thickness of 0 ° by a sputtering method, and this was etched to form an upper wiring / electrode 414. In the region 417, the aluminum wiring 404 was connected to the upper wiring / electrode 414 through the contact hole 413.
(FIG. 4D) Thereafter, a passivation film 415 of silicon nitride was formed. Here, the silicon nitride film is formed by plasma CVD using a mixed gas of NH ₃ / SiH ₄ / H ₂ at 4000 ° C.
With a film thickness of At this stage, contact hole 4
11 and the opening 412 were entirely filled with the silicon nitride film 415.

Thereafter, the passivation film is etched by a wet etching method,
11. A contact hole and an opening were formed inside the opening 412. And ITO (indium tin oxide)
Is formed by sputtering, and this is etched,
The pixel electrode 416 of the liquid crystal display device covers the opening 412.
Was formed. Here, an anodic oxide film was present between the aluminum wiring 406 and the pixel electrode 416, and this became a dielectric, and a capacitor was formed in the region 418.

In this embodiment, after the contact hole 411 and the opening 412 once formed are further filled with silicon nitride, the contact hole and the opening are formed again. This is because when a multilayer film in which a silicon nitride film is formed on a silicon oxide film is etched by a wet etching method, the silicon oxide on the lower side is etched laterally because the etching rate of silicon oxide is higher than that of silicon nitride. This is to avoid the problem that

[0043]

According to the present invention, not only can a contact hole be reliably formed in a wiring covered with an anodic oxide film, but also an integrated circuit can be formed by using an anodic oxide film as a dielectric of a capacitor. Could be given new added value. Thus, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 shows a typical process of the present invention.

FIG. 2 shows a manufacturing process of a TFT in an example.

FIG. 3 shows a manufacturing process of a TFT in an example.

FIG. 4 illustrates a manufacturing process of a TFT in an example.

FIG. 5 shows an outline of an active matrix circuit.

FIG. 6 shows a problem seen in a conventional contact hole forming process.

[Explanation of symbols]

 101: an aluminum electrode or wiring 102: an aluminum electrode or wiring 103: anodized oxide film 104: anodized oxide film 105: interlayer insulation Object 106 Photoresist 107 Opening pattern 108 Opening pattern 109 Opening part 110 Opening part 111 ··· Photoresist 112 ····· Opening pattern 113 ····· Contact hole 114 ····· Upper wiring 115 ····· Upper wiring 116 ····· Contact area 117 Capacitor area

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-55-72060 (JP, A) JP-A-55-65581 (JP, A) JP-A-57-128951 (JP, A) 46568 (JP, A) JP-A-7-283166 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/306 H01L 21/3205-21/3213 H01L 21/768

Claims (5)

(57) [Claims] Forming a plurality of aluminum wirings, forming an anodic oxide on the surface of the aluminum wiring, forming an interlayer insulating film covering the anodic oxide, forming an interlayer insulating film on the aluminum wiring; Forming a first and a second opening, forming a third opening smaller than the first opening in the anodic oxide by etching inside the first opening; through the first and third opening to form a metal wiring connected to the aluminum wiring, covering the metal wiring and the second opening to form a silicon nitride film, said second opening Inside the hole, a fourth hole is formed in the silicon nitride film by etching to form the anodic oxide.
Exposing a region including the anodic oxide exposed in the fourth opening
A method for manufacturing a semiconductor device in which a pixel electrode is formed thereon, wherein a capacitance between the pixel electrode and the aluminum wiring is formed using the anode oxide as a dielectric. Of manufacturing a semiconductor device. 2. The solution according to claim 1, wherein the solution contains at least phosphoric acid, acetic acid, and nitric acid, and to which chromic acid is added, wherein the volumetric mixing ratio of phosphoric acid, acetic acid, and nitric acid is 40 to 40%. 90 to 90, acetic acid 10 to 100, nitric acid 1 to 40
The method of manufacturing a semiconductor device, wherein the anodic oxide is etched by an etchant, and the temperature of the etchant is 50 to 200 ° C. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the silicon nitride film is etched by wet etching. 4. The method according to claim 1, wherein
A method for manufacturing a semiconductor device, wherein the first and second openings are formed by dry etching. 5. The method according to claim 1, wherein:
A method for manufacturing a semiconductor device, wherein the silicon nitride film is formed by a plasma CVD method using a mixed gas of NH ₃ / SiH ₄ / H ₂ .