JP3618826B2 - Image signal processing apparatus and method - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an image signal processing apparatus and method for performing image processing such as filter processing on an image signal in a copying machine, a facsimile machine or the like.
[0002]
[Prior art]
A general digital image processing apparatus such as a copying machine or a facsimile apparatus has a plurality of portions for performing matrix processing such as a digital filter used for edge enhancement and smoothing processing. The matrix processing for this image signal will be described with reference to FIG. Here, an example using a 9 × 9 square matrix will be described. The image signal is basically transferred by a raster scan method in units of lines.
[0003]
In the figure, 601 is a currently transferred line (line N + 4). Reference numeral 602 denotes eight line buffers for delaying image signals for one line. Reference numeral 603 denotes eight flip-flops per line. The line N + 3 one line before is delayed by one line by the line buffer 602 and input to the main scanning direction delay flip-flop 603 simultaneously with the line N + 4 image signal. Similarly, line N + 2, line N + 1, line N, line N-1, line N-2, line N-3, and line N-4 are respectively delayed by one line by the line buffer 602, and thus synchronized with line N + 4. To the flip-flop 603 for main scanning direction delay. In this way, nine lines that form a 9 × 9 matrix and are continuous in the sub-scanning direction are created.
[0004]
Further, the above-mentioned nine lines of image signals are delayed by one pixel by a main scanning direction delay flip-flop 603 provided on each line. Accordingly, by using one pixel before the delay by the flip-flop 603 and eight pixels after the delay, nine pixels that are continuous in the main scanning direction forming a 9 × 9 matrix are created. The 9 × 9 pixels are respectively input to the arithmetic circuit 604, and after a predetermined calculation, are output as a line N image signal 605.
[0005]
The above description is about a matrix image processing unit in a general digital image processing apparatus. However, in recent digital image processing apparatuses, high-speed transfer of an image signal is indispensable due to a synergistic effect of improved processing capability and higher resolution. It is becoming. When realizing this high speed, the circuit speed cannot keep up with the matrix image processing configuration described above. Therefore, it is necessary to realize high-speed transfer of image signals using a low-speed matrix image processing unit.
[0006]
For this purpose, a method can be considered in which image signals that are serially transferred at high speed are rearranged in parallel to reduce the transfer speed. For example, in pixel parallel processing in which parallel processing is performed in units of pixels, the transfer speed is reduced by one-half if parallel processing is performed every two pixels, and the transfer speed is reduced by one-third if performed by three pixels. In addition, line division parallel processing, in which one line of image signal is divided into a plurality of lines in the line direction and parallel processing is performed, is also conceivable.
[0007]
When such parallel processing is used, relatively low-speed image processing is performed in parallel, resulting in high-speed image processing. Therefore, it is possible to cope with high-speed image signal transfer. It becomes.
[0008]
[Problems to be solved by the invention]
However, the circuit configuration when performing image processing using a matrix by the parallel processing becomes very complicated. The configuration is shown in FIG. Here, an example will be described in which parallel processing is performed for every four pixels in order to reduce the transfer rate to a quarter.
[0009]
As in FIG. 10, the input image line is a line N + 4 of 701, and four consecutive pixels in the main scanning direction of n, n + 1, n + 2, and n + 3 in the line N + 4 serial / parallel converted by the preprocessing are simultaneously input in parallel. Will be. Here, in order to perform the 9 × 9 matrix processing similar to the above to four pixels that are input in parallel, 32 line buffers 702 for generating nine lines in the sub-scanning direction are required. Therefore, the number of line buffers is four times that of the example of FIG.
[0010]
In addition, since the required capacity of each line buffer 702 is sufficient to divide one line into four, the total buffer capacity is the same as in FIG. However, the lineup of the normal line buffer rarely corresponds to the capacity, and as a result, the cost of the line buffer unit is considerably increased.
[0011]
Further, the part of the matrix image processing unit 105 that does not include the line buffer 702, that is, the part of the flip-flop unit 703 and the arithmetic circuit 704 is generally integrated into one chip as an ASIC. Considering one-chip implementation, this pixel parallel processing has a big problem with the number of input signal terminals. In other words, if it is an 8-bit image signal per input, the number of input terminals of the ASIC is
9 lines × 4 pixels parallel × 8 bits = 288 input terminals, making ASIC very difficult. As described above, there are two problems in the pixel parallel processing: the cost increase of the line buffer unit and the limitation to the ASIC.
[0012]
[Means for Solving the Problems]
The present invention has been made in view of the above points, and an object of the present invention is to enable complex image processing such as matrix calculation to be executed at high speed with a simple configuration.
[0013]
It is another object of the present invention to perform image processing on an image signal input for each line at high speed with a simple configuration.
[0014]
Another object of the present invention is to enable high-speed image processing in a digital copying machine, a facsimile machine, or the like.
[0015]
That is, the present invention provides an input means for inputting an image signal in parallel for each pixel by a plurality of pixels, and a conversion means for converting the image signal input from the input means into a plurality of lines and a parallel image signal for output. An image signal processing apparatus having processing means for performing image processing on each of a plurality of lines of image signals output in parallel from the conversion means.
[0016]
Further, the processing means according to the present invention performs the same image processing in parallel on each of the image signals of a plurality of lines, and the processing means according to the present invention converts the image signals of a plurality of lines. Each is delayed to form an image matrix, and matrix calculation is performed.
[0017]
The above objects and effects of the present invention and other objects and effects of the present invention will be apparent from the following description.
[0018]
【Example】
Hereinafter, the present invention will be described in detail using preferred embodiments. FIG. 1 shows the overall configuration. Reference numeral 101 denotes a CCD line sensor that reads an image on a paper surface and replaces the image with an electrical signal for each pixel by photoelectric conversion. The CCD line sensor unit will be described in more detail with reference to FIG.
[0019]
Reference numeral 201 denotes a photodiode portion that replaces the amount of light with an electric charge. The photodiode unit 201 has an array structure in which thousands are arranged to constitute a line sensor. Further, in order to transfer the accumulated charges at high speed, two pairs of CCDs indicated by 202, 203, 204, and 205 are formed on both sides of the photodiode portion 201 for a total of four lines. After the photodiode section 201 has passed a predetermined charging time, the pixel 1, pixel 5,..., Pixel 4n + 1 are in the CCD 202, the pixel 2, pixel 6,..., Pixel 4n + 2 are in the CCD 203, and the pixel 3, pixel 7,. In addition, the pixel 4, the pixel 8, and the pixel 4n + 4 are transferred from the photodiode unit 201 to the CCDs 202 to 205 like the CCD 205. Note that n is an integer of 0, 1, 2,. In the next cycle, each pixel in the CCDs 202 to 205 is shifted in the CCD line direction and output to the output units 206, 207, 208 and 209. Thus, the output of the CCD line sensor 101 is transferred as a parallel image signal in units of four pixels.
[0020]
The description returns to FIG. An analog / digital conversion unit 102 amplifies analog image signals output from the CCD line sensor 101 in parallel with four pixels, and converts them into four digital image signals. A shading processing unit 103 inputs a 4-pixel parallel digital image signal and performs black correction and white correction of the image signal in the line direction. At this stage, the image read by the CCD line sensor 101 is in the form of a normalized digital image signal.
[0021]
A next 104 is a pixel parallel / line parallel conversion unit for converting image data transferred by pixel parallel transfer for every four pixels into four lines in parallel by transferring four lines. The block diagram is shown in FIG.
[0022]
In order to convert the pixel parallel image signal 301 for every four pixels into four line parallel image signals 302, the pixel parallel / line parallel conversion unit 104 includes 16 line buffers LB. The timing of the conversion operation is shown in FIG. A signal indicating the image effective area in the line direction of the pixel parallel image signal is denoted by 401. Below that, the image signals of the N-th, N + 1-th, N + 2-th, and N + 3-th lines are in a state of four parallel pixels. The N-line 4-pixel parallel image signal is input to the line buffers LB00 to LB03. The serial N-th line image signal can be obtained by sequentially reading out the image signals from the line buffers LB00 to LB03. The N + 1, N + 2, and N + 3 lines are also converted into serial image signals using the line buffers LB10 to 13, 20 to 23, and 30 to 33. In this way, the pixel parallel image signal is converted into a serial image signal for each line by the pixel parallel / line parallel transfer conversion unit 104, and the image signals of the N line, N + 1 line, N + 2 line, and N + 3 line are simultaneously input. Parallel transfer at 1/4 speed. The effective image area is indicated by 402.
[0023]
As shown in FIG. 4, in the pixel parallel / line parallel conversion unit 104, when N to N + 3 line image signals are input, parallel output of N-4 to N-1 line image signals is performed in parallel therewith. Done. Therefore, for this parallel processing, each line buffer LB00 to LB33 has a capacity capable of storing image signals for two lines, and writes the next line in parallel with reading the image signal of the previous line. The configuration is possible. Note that two sets of the pixel parallel / line parallel conversion unit 104 in FIG. 3 may be provided and used alternately for writing and reading.
[0024]
After conversion to 4-line parallel transfer, the image processing unit 105 performs image processing. Here, various processes for handling an image as a matrix, such as edge enhancement and smoothing, and image processing for performing shadowing, italics, rotation, and the like of the image are included. Here, matrix image processing using a 9 × 9 square image matrix as one of several image processing will be described with reference to FIG.
[0025]
Matrix image processing is edge enhancement, smoothing, pattern matching in an area, and the like, and is a method that is relatively frequently used in image processing. Now, four lines of N + 4 line, N + 5 line, N + 6 line, and N + 7 line are input to the matrix image processing unit 105 as 501.
[0026]
The matrix image processing unit 105 is provided with eight flip-flops for each of eight line buffers 502 and four input lines and eight line buffers for delaying an image signal for one line. For example, because of 4-line parallel transfer, the image signal input via the same line one line before the N + 4 line image signal becomes N lines. Further, the image signal input via the same line one line before the image signal of N lines becomes N-4 lines. Therefore, the N line image signal is delayed by one line by the line buffer 502, and the N-4 line image signal is delayed by 2 lines by the line buffer 502, so as to delay the main scanning direction simultaneously with the N + 4 line image signal. Input to the flip-flop 503.
[0027]
Further, the N + 1, N + 2, N + 3 line image signals input one line before the N + 5, N + 6, N + 7 line image signals input to the remaining three input lines, respectively, and the N− input input two lines before. The image signals of the 3, N + 2, N−1 lines are output from the line buffer 502.
[0028]
As described above, by using the line buffer 502, all image signals for 12 lines from the N-4 line to the N + 7 line are input to the flip-flop 503 for delay in the main scanning direction in synchronization.
[0029]
That is, image signals for 12 lines continuous in the sub-scanning direction are formed. Then, four 9 × 9 matrices are generated from the 12-line image signals by shifting one line in the sub-scanning direction. That is, the image signal from the N-4 line to the N + 4 line is a matrix for processing the image signal of the N line, and the image signal from the N-3 line to the N + 5 line is a matrix for processing the image signal of the N + 1 line. N-2 to N + 6 line image signals are processed into a matrix for processing N + 2 line image signals, and N-1 to N + 7 line image signals are processed into a matrix for processing N + 3 line image signals. Each is used.
[0030]
That is, the image signals from the N-3 line to the N + 6 line can be shared by a plurality of matrices. Further, nine pixels in the main scanning direction are generated by using the pixels delayed by one pixel by the main scanning direction delay flip-flop 503, thereby generating nine pixels in the main scanning direction.
[0031]
The four 9 × 9 matrix pixels generated in this way are respectively input to four matrix calculation circuits 504, and after performing a predetermined matrix calculation, image signals of N line, N + 1 line, N + 2 line, and N + 3 line. It is output as 505. Thus, the matrix image processing process for the line parallel image signals of 4 lines is completed.
[0032]
After the image processing that is advantageous for the line parallel processing is completed, the line parallel / pixel parallel conversion unit 106 performs conversion again to pixel parallel transfer. That is, by switching to the pixel parallel transfer that is most frequently used in normal data transfer, a standard transfer image can be supplied to other units. The line parallel / pixel parallel conversion unit 106 performs the reverse operation of the pixel parallel / line parallel conversion unit 104 shown in FIG. It should be noted that the transfer is not limited to the 4-pixel parallel transfer, and can be transferred as a serial signal without parallel according to the transfer speed of the subsequent circuit. Similarly, it is possible to send out to the subsequent circuit having a low transfer rate by 8-pixel parallel transfer or 16-pixel parallel transfer.
[0033]
As described above, there is means for converting the image signal for each line into line parallel transfer, and after converting the transfer direction, processing such as matrix image processing is performed to convert it again into pixel parallel transfer. Thus, when processing four systems of 9 × 9 pixel matrices as shown in the above example, the number of line buffers as shown in FIG. 5 is the same as the four systems of parallel processing shown in FIG. It can be realized with the same eight as in the case of a simple one-line matrix processing that is not performed. In addition, the line parallel processing is also as follows with respect to the limit of the number of input terminals of the ASIC cited as a problem in the pixel parallel processing (assuming that it is an 8-bit image signal per input).
[0034]
12 lines × 8 bits = 96 number of input terminals Accordingly, the present invention is much more realistic than the 288 terminals of the pixel parallel processing shown in FIG.
[0035]
Although only the matrix image processing has been described here, the image processing is not limited to matrix processing, but various processing is performed. For example, it is effective in terms of processing time and circuit scale even when error diffusion processing for diffusing errors over a wide area or when rotating an image stored in a page buffer.
[0036]
In the configuration of the embodiment described above, the CCD line sensor 101 is provided with four lines of CCDs and outputs four lines of pixels 4n + 1, 4n + 2, 4n + 3, 4n + 4 (n is an integer of 0 or more) in parallel. An image signal is output from the line sensor 101 in parallel to four pixels.
[0037]
Accordingly, the pixel parallel / line parallel conversion unit 104 outputs the pixel parallel to the 4-pixel parallel image signal output from the CCD line sensor 101 in a 4-pixel parallel manner via the analog / digital conversion unit 102 and the shading processing unit 103. / Line parallel conversion is performed.
[0038]
However, as a CCD line sensor, an ODD / EVEN two-pixel parallel output or a pixel serial output may be used instead of a four-pixel parallel output.
[0039]
In this case, a pixel parallel conversion circuit is provided that takes in an image signal of 2-pixel parallel output or pixel serial output and converts it to 4-pixel parallel output. Then, the 4-pixel parallel image signal from the pixel parallel conversion circuit is introduced into the pixel parallel / line parallel conversion unit 104, converted into a line parallel image signal, and the same processing as described above is executed.
[0040]
(Other examples)
FIG. 6 shows another embodiment of the present invention.
[0041]
The configuration is basically the same as that in the above embodiment, but one line of image signal is output from the CCD line sensor 801 as serial data for each line. The image signal is converted into a normalized digital image signal by passing through the analog-digital conversion unit 802 and the shading processing unit 803. The line parallel conversion unit 804 collects the image signals input line by line for every two lines and outputs them as a two line parallel signal.
[0042]
FIG. 7 shows the configuration of the line parallel conversion unit 804. LB0 and LB1 are line buffers, and the capacity of these line buffers LB0 and LB1 can store image signals of two lines or more.
[0043]
FIG. 8 shows the timing of the conversion operation of the line parallel conversion unit 804.
[0044]
The line serial image signal 301 from the shading processing unit 803 is alternately written in the line buffers LB0 and LB1. That is, the N line image signal is written in the line buffer LB0, and the N + 1 line image signal is written in the line buffer LB1. A signal 901 indicates an effective area of the input image signal. After that, the N-line and N + 1-line image signals are transferred in parallel as line parallel signals 302 from the line buffers LB0 and LB1 at a speed approximately half that at the time of input.
[0045]
In parallel with this parallel transfer, image signals of N + 2 line and N + 3 line are written to the line buffers LB0 and LB1. The N + 2 line and N + 3 line image signals are transferred in parallel. A signal 902 indicates an effective area of an image signal to be transferred in parallel.
[0046]
The image signal that has been subjected to the two-line parallel conversion is subjected to image processing by an image processing unit 805. FIG. 9 shows the configuration of the image processing unit 805. Here, matrix image processing using a 9 × 9 square image matrix is performed as in the above example.
[0047]
The image processing unit 805 is provided with eight flip-flops in each of eight line buffers 902 for delaying an image signal for one line, two input lines, and eight line buffers. For example, because of 2-line parallel transfer, an image signal input via the same line one line before N + 4 lines becomes N + 2 lines. Therefore, the N + 2 line image signal is delayed by one line by the line buffer 902 and is input to the main scanning direction delay flip-flop 903 simultaneously with the N + 4 line image signal. Similarly, the image signals of all 10 lines from the N-4 line to the N + 5 line are input to the flip-flop 903 for delaying in the main scanning direction in synchronization. At this time, there are 10 lines of image signals, and this makes it possible to create two 9 × 9 matrices that are shifted by one line in the sub-scanning direction. That is, the image signals from the N-3 line to the N + 4 line can be shared by two matrices. Further, nine pixels in the main scanning direction are generated by using the pixels delayed by one pixel by the main scanning direction delay flip-flop 903, thereby generating nine pixels continuous in the main scanning direction.
[0048]
The two 9 × 9 matrix pixels generated in this way are input to two matrix operation circuits 904, respectively, and after performing a predetermined matrix operation, are output as N-line and N + 1-line image signals 905. As a result, the matrix image processing process for the two line parallel image signals is completed.
[0049]
After the image processing that is advantageous for the line parallel processing is completed, the line parallel / pixel serial conversion unit 806 converts the image data back to the original pixel trial transfer again. Standard transfer images can be supplied to this unit. The line parallel / pixel serial conversion unit 806 performs the reverse operation of the line parallel conversion unit 804 shown in FIG.
[0050]
As described above, it has means for converting the pixel serial image signal for each line into line parallel transfer, and after converting the transfer method, performs processing such as matrix image processing and converts it again into pixel serial transfer. As a result, when processing two systems of 9 × 9 image matrices, as shown in FIG. 9, the number of line buffers is eight, which is the same as in the case of mere one system matrix processing without performing two systems of parallel processing. Can be realized.
[0051]
Although only the matrix image processing has been described here, the image processing is not limited to matrix processing, but various processing is performed. For example, it is effective in terms of processing time and circuit scale even when error diffusion processing for diffusing errors over a wide area or when rotating an image stored in a page buffer.
[0052]
In addition, the matrix image processing is not limited to a 9 × 9 square image matrix, but can be applied to matrix image processing of other sizes, and the number of buffer memories and flip-flops can be applied to other sizes. Needless to say, the number of lines after line parallel or the like is appropriately changed according to the processing.
[0053]
【The invention's effect】
As described above, according to the present invention, an image signal for each line that is input in parallel for each of a plurality of pixels is converted into a parallel image signal for each of a plurality of lines , and each of the image signals for a plurality of lines that are output in parallel. Therefore, when image processing using image signals for a plurality of lines such as edge enhancement, smoothing, and pattern matching is performed, the image processing can be executed at high speed with a small circuit configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an image processing apparatus to which the present invention is applied.
FIG. 2 is a diagram showing a structure of a CCS line sensor.
FIG. 3 is a diagram illustrating a configuration of a pixel parallel / line parallel conversion unit.
FIG. 4 is a diagram illustrating a pixel parallel / line parallel conversion operation.
FIG. 5 is a diagram illustrating a configuration of an image processing unit.
FIG. 6 is a diagram showing a configuration of another embodiment of the image processing apparatus.
FIG. 7 is a diagram showing a configuration of a line parallel conversion unit.
FIG. 8 is a diagram illustrating a line parallel conversion operation.
FIG. 9 is a diagram illustrating a configuration of an image processing unit.
FIG. 10 is a diagram illustrating a configuration of a general matrix image processing unit.
FIG. 11 is a diagram showing a configuration of a conventional matrix image processing unit.
[Explanation of symbols]
101 CCD line sensor 104 pixel parallel / line parallel conversion unit 105 image processing unit 502 line buffer 503 flip-flop 504 arithmetic circuit

Claims (8)

Input means for inputting image signals in parallel by a plurality of pixels for each line;
Conversion means for converting the image signal input from the input means into a multi-line, parallel image signal and outputting it;
An image signal processing apparatus comprising: processing means for performing image processing on each of a plurality of lines of image signals output in parallel from the conversion means. 2. The image signal processing apparatus according to claim 1, wherein the processing unit performs the same image processing in parallel on each of the image signals of a plurality of lines. The image signal processing apparatus according to claim 1, wherein the processing unit delays the image signals of a plurality of lines to form an image matrix and performs matrix calculation. Input means for inputting image signals in parallel by a plurality of pixels for each line;
Conversion means for converting the image signal input from the input means into a multi-line, parallel image signal and outputting it;
A plurality of delay means for delaying each of a plurality of lines of image signals output in parallel from the conversion means;
An image signal processing apparatus comprising: processing means for performing matrix image processing on the image signals of a plurality of lines delayed by the plurality of delay means. 5. The image signal processing apparatus according to claim 4, wherein the processing unit performs the same matrix image processing in parallel on the image signals of a plurality of lines delayed by the plurality of delay units. The image signal processing apparatus according to claim 4, wherein the plurality of delay units form a plurality of image matrices. An input step of inputting an image signal in parallel by a plurality of pixels for each line;
A conversion step of converting the image signal input in the input step into a plurality of lines and a parallel image signal and outputting the image signal;
And a processing step of performing image processing on each of a plurality of lines of image signals output in parallel from the conversion step. The image signal processing method according to claim 7, wherein in the processing step, the same image processing is performed in parallel on each of the image signals of a plurality of lines.

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