JP3593647B2 - Multi-stage interleaved pattern generator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention is applicable when performing multi-stage interleaving (MIL), which is essential for avoiding burst errors in a data communication system or the like, or when performing de-interleaving of multi-stage interleaved data. The present invention relates to a multi-stage interleave pattern generator used in the present invention.
[0002]
Multistage interleaving (MIL) performs interleaving in multiple stages. Compared to normal interleaving with only one stage, correlated continuous data is further dispersed, and reception / reproduction for a burst error of a continuous block of data is performed. It is to improve data error correction or its correction capability.
[0003]
The multi-stage interleave (MIL) can be applied to a data recording / reproducing apparatus other than the data communication system, but the following description will be made by taking an example in which the multi-stage interleave (MIL) is applied to a data communication system.
[0004]
In order to perform multi-stage interleaving (MIL), transmission data is sequentially written to a memory address, and the written transmission data corresponds to the order pattern according to the order pattern generated by the multi-stage interleave pattern generator. By sequentially reading from the memory addresses, the order of the transmission data is dispersed and transmitted.
[0005]
The receiving-side multi-stage deinterleaving sequentially writes received data to memory addresses corresponding to the order pattern according to the order pattern generated by the multi-stage interleaving pattern generator, and sequentially writes the received data that has been written to the memory. A process of reading from the address and returning the received data in the discontinuous order to the original order is performed.
[0006]
In the multistage interleaving, the pattern of changing the order of transmission data (interleaving pattern) becomes more complicated than that of the interleaving of only one stage, and the size and density of recent LSIs, package boards (PCB) printed boards, etc. are increased. With the demand for low power consumption, reduction of the circuit scale and reduction of memories and the like have become important issues. Therefore, it is necessary to efficiently generate a complicated multi-stage interleave pattern.
[0007]
[Prior art]
FIG. 17 is an explanatory diagram of a conventional multi-stage interleave pattern generator. Conventionally, in the generation of a multi-stage interleave pattern, it has been considered difficult to implement a logic circuit without a memory in consideration of the complexity of the multi-stage interleave pattern, an enormous data length, a plurality of pattern types, and the like.
[0008]
Therefore, the multi-stage interleave pattern different depending on the data length and type of data to be transmitted is individually tabulated, a plurality of memories for storing each table are provided, and the multi-stage interleave pattern is read by reading the memory. I was taking it out.
[0009]
As shown in FIG. 17, the conventional multi-stage interleave pattern generator stores a multi-stage interleave pattern that differs depending on a data length and a pattern type into a plurality of (n) memories (RAM: Random Access Memory) 17-. 1 and read out from each memory 17-1 by a selector 17-2 to select and output a multi-stage interleave pattern.
[0010]
The different multi-stage interleave pattern data (MIL data) is stored in each memory 17-1 by designating a write position by a chip select (CS) signal and a write address signal.
[0011]
Then, one of the memories 17-1 is selected by the chip select (CS) signal, and the output data of the memory 17-1 is selected by controlling the selector 17-2 by the select (SEL) signal. , Sequentially read necessary multi-stage interleave pattern data by giving a read address, and extract different types of multi-stage interleave pattern data.
[0012]
Further, as another means, a multi-stage interleave pattern is obtained by a predetermined arithmetic expression based on the data length of data to be transmitted without using a plurality of memories such as a RAM for storing each multi-stage interleave pattern table. The calculated multistage interleave pattern can be generated by overwriting the memory every time.
[0013]
The former configuration in which each multi-stage interleave pattern table is stored in a memory requires an enormous memory capacity, and the latter configuration in which each multi-stage interleave pattern is generated by calculation is a digital signal processor (DSP). ) And the like, and the calculation is performed every time, so that the processing is delayed.
[0014]
[Problems to be solved by the invention]
The method of storing each multi-stage interleave pattern table in a memory cannot reduce the memory, and has a problem in miniaturization, high density, and low power consumption of an LSI and a package board (PCB) printed board.
[0015]
Also, a method of calculating and generating each multi-stage interleave pattern by a processor such as a digital signal processor (DSP) involves processing delay, which is fatal in data communication requiring high speed. Disadvantages.
[0016]
The present invention realizes a means for generating a multi-stage interleave pattern by using only a logic circuit without using a memory or a processor such as a digital signal processor (DSP) at all. It is an object of the present invention to enable power consumption and high-speed processing.
[0017]
[Means for Solving the Problems]
The multi-stage interleave pattern generator according to the present invention includes: (1) a count-up that outputs a count value at least up to the total number of data to be interleaved, and sequentially generates a bit pattern of the count value by a clock signal; And a multi-stage interleave pattern generator for symmetrically exchanging upper bits and lower bits output from the count-up unit.
[0018]
(2) The count-up section is constituted by an octal counter, and the multi-stage interleave pattern generation section exchanges the most significant bit and the least significant bit output from the count-up section and outputs them. It has the structure which does.
[0019]
(3) a binary counter operated by the carry signal output from the count-up unit in (1) or (2), and an output from the multi-stage interleave pattern generation unit in (1) or (2). And a synthesizing unit for outputting a bit pattern to which the output bits of the binary counter are added, on the lower side of the bit pattern to be performed.
[0020]
(4) The count-up unit is constituted by a hexadecimal counter.
(5) The count-up unit is constituted by a counter that counts up to an integer value of a power of two.
[0021]
(6) An L (L is an arbitrary integer) base counter for counting the carry signal output from the K-ary counter, wherein the count-up unit in the above (1) is a K (K is an arbitrary integer) counter. A multiplier for multiplying the value of the bit pattern output from the multi-stage interleave pattern generation unit according to (1) by the integer L, and an output value of the multiplier and an output value of the L-ary counter And an adder for adding.
[0022]
And (7) a second multi-stage interleave pattern generator for symmetrically exchanging higher-order bits and lower-order bits output from the L-ary counter, and the adder includes: The configuration is such that the value of the bit pattern output from the second multi-stage interleave pattern generator is added to the output value of the multiplier.
[0023]
(8) The count-up unit is configured to have a function of a count-up operation for generating a count value in ascending order and a function of a count-down operation for generating a count value in descending order. And a reverse determination unit for switching between a countdown operation and a countdown operation.
[0024]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is an explanatory diagram of a basic configuration of a multistage interleaved pattern generator according to the present invention. In FIG. 1A, 1-1 is a count-up unit, and 1-2 is a multi-stage interleave pattern generation unit.
[0025]
In a minimum basic configuration for performing multi-stage interleaving, the count-up unit 1-1 is configured by an octal counter, is set to an initial value “000 (0)”, counts up by a clock signal, and sequentially counts up to 000. The bit patterns of (0), 001 (1), 010 (2), 011 (3), 100 (4), 101 (5), 110 (6), and 111 (7) are output.
[0026]
The multi-stage interleave pattern generation unit 1-2 is configured by an MSB-LSB bit operation circuit that replaces the most significant bit MSB and the least significant bit LSB of the bit pattern output from the count-up unit 1-1.
[0027]
(B) of the figure shows the count-up unit 1-1 shown in (A) of the figure composed of three flip-flops Q0, Q1, and Q2, and the output bit of the flip-flop Q0 that outputs the least significant bit LSB; An example is shown in which the multi-stage interleave pattern generator 1-2 replaces the output bit of the flip-flop Q2 that outputs the most significant bit MSB with each other, and outputs a multi-stage interleave pattern. .
[0028]
The bit patterns sequentially output from the multi-stage interleave pattern generator 1-2 are 000 (0), 100 (4), 010 (2), 110 (6), 001 (1), 101 (5), 011 (3), 111 (7).
[0029]
A general procedure for performing multi-stage interleaving of eight data is as follows: first, eight data are arranged in two rows vertically and four rows horizontally, or 2 × 4 pieces of data are arranged vertically. , 4 × 2 data arranged side by side. Then, the four data arranged vertically or horizontally are further arranged two vertically and two horizontally to interleave.
[0030]
Here, a multi-stage interleave in which eight pieces of data are arranged vertically two pieces and four pieces horizontally and four pieces of data arranged horizontally are further arranged two pieces vertically and two pieces horizontally is expressed by the following equation: 8 (2 × 4 (2 × 2)). A multi-stage interleave in which eight pieces of data are arranged vertically four pieces and two pieces horizontally, and the four pieces of data arranged vertically are further arranged two pieces vertically and two pieces horizontally is expressed by the following equation: (4 (2 × 2) × 2).
[0031]
FIG. 2 is an explanatory diagram of the multi-stage interleaving of Expression: 8 (2 × 4 (2 × 2)) and Expression: 8 (4 (2 × 2) × 2). (A) of the figure shows the operation procedure of the multi-stage interleave by the equation: 8 (2 × 4 (2 × 2)), and (B) of the figure shows the operation procedure of the multistage interleave by the equation: 8 (4 (2 × 2) × 2). I have. It should be noted that the multistage interleaving pattern finally obtained is the same regardless of the operation procedure of any of the calculation formulas.
[0032]
In FIG. 2A, an interleave operation is performed on 8 (2 × 4) of the underlined part a of the equation: 8 (2 × 4 (2 × 2)), and as shown in FIG. The data of 7 is divided into data of 0 to 3 and data of 4 to 7 and two-dimensionally arranged.
[0033]
Next, when a horizontal interleave operation is performed on 4 (2 × 2) of the underlined part b of the expression: 8 (2 × 4 (2 × 2)), as shown in (A-2), the interleave operation starts from 0 as shown in (A-2). The data up to 3 are exchanged in the order of 0, 2, 1, and 3, and the data 4 to 7 are exchanged in the order of 4, 6, 5, and 7.
[0034]
Then, the data in the order of 0, 2, 1, 3 and the data in the order of 4, 6, 5, 7 arranged in the horizontal direction are output in the order of the vertical direction, so that 0, 4, 2, 6, 1 , 5, 3, 7 in this order.
[0035]
In the case of a multi-stage interleaving operation procedure using the equation: 8 (4 (2 × 2) × 2) shown in FIG. 8B, 8 (4 × 2) interleaving shown in FIG. When a two-dimensional array in which 0, 2, 4, 6 and 1, 3, 5, 7 are arranged in the direction is generated, and then vertical interleaving is performed as shown in (B-2), If a two-dimensional array in which 0, 4, 2, 6 and 1, 5, 3, 7 are arranged and the array is to be output in the vertical direction, the transmission order is 0, 4, 2, 6, 1, 5, 3, and 7. This pattern is the same as the multistage interleave pattern of (A) described above.
[0036]
As described above, the pattern obtained by the multi-stage interleave pattern generator shown in FIG. 1 described above is expressed by the following equation: 8 (2 × 4 (2 × 2)) and 8 (4 (2 × 2) × It is the same as the multi-stage interleave pattern of 2), and it is possible to generate the 0, 4, 2, 6, 1, 5, 3, 7 multi-stage interleave pattern by the logic circuit shown in FIG. .
The eight-stage multistage interleave pattern is the shortest basic pattern in the multistage interleave pattern.
[0037]
FIG. 3 is an explanatory diagram of a multistage interleaved pattern generator twice as long as the basic pattern. As shown in FIG. 2A, this pattern generator includes a basic pattern generation circuit including a count-up section 3-1 and a multi-stage interleave pattern generation section 3-2 as described above. It has a ternary counter 3-3 and a synthesizing unit 3-4.
[0038]
FIG. 2B shows an example of a configuration using an octal counter composed of three flip-flops Q0, Q1, and Q2 shown in FIG. 1 in the count-up unit 3-1 as a basic pattern generation circuit.
[0039]
The multi-stage interleave pattern generation unit 3-2 is configured by an MSB-LSB bit operation circuit that replaces the most significant bit MSB and the least significant bit LSB of the output bit of the count-up unit 3-1. It is similar to that shown in FIG.
[0040]
The binary counter 3-3 outputs “1” when a carry signal (CO: Carry Out) which is a carry signal from the most significant bit of the count-up unit 3-1 is input. The synthesizing unit 3-4 adds one bit output from the binary counter 3-3 to the least significant bit to the three-bit output output from the multi-stage interleave pattern generation unit 3-2, and outputs a 4-bit data. Output as a bit pattern.
[0041]
The multi-stage interleave pattern generator shown in FIG. 3B generates a 16-pattern-length multi-stage interleave pattern because an octal counter is used in the count-up unit 3-1. , A multi-stage interleaved pattern generation circuit having an arbitrary pattern length can be used.
[0042]
FIG. 4 is an explanatory diagram of a multi-stage interleave pattern having a length of 16 patterns. The figure shows an example in which a 16-pattern-length multistage interleave pattern is generated by an interleave operation using a calculation formula of 16 (4 (2 × 2) × 4 (2 × 2)).
[0043]
The multi-stage interleave pattern having a length of 16 patterns can be obtained by the calculation formula of 16 (8 (4 (2 × 2) × 2) × 2) or the formula: 16 (2 × 8 (4 ( The same pattern is generated by the calculation formula of 2 × 2) × 2)).
[0044]
First, an interleave operation is performed on 16 (4 × 4) of the underlined part a of the equation: 16 (4 (2 × 2) × 4 (2 × 2)) shown in FIG. As shown, data from 0 to 15 is divided into four data, 0 to 3, 4 to 7, 8 to 11, and 12 to 15, and two-dimensionally arranged.
[0045]
Next, an interleave operation is performed on 4 (2 × 2) of the underlined part b of the formula: 16 (4 (2 × 2) × 4 (2 × 2)), and the lines are arranged in the vertical direction as shown in (C). The order is changed for each of the four data.
[0046]
Next, an interleave operation is performed on 4 (2 × 2) of the underlined portion c of the formula: 16 (4 (2 × 2) × 4 (2 × 2)), and as shown in FIG. The order is changed for each of the four data lines.
[0047]
The multistage interleave pattern generated by these interleave operations is obtained by fetching and arranging data of a two-dimensional array shown on the right side of the arrow (D) in FIG. The patterns are 12, 2, 10, 6, 14, 1, 9, 5, 13, 3, 11, 7, and 15.
[0048]
On the other hand, the pattern generated from the count-up unit 3-1 and the multi-stage interleave pattern generation unit 3-2 shown in FIG. 3B becomes the pattern shown in FIG. The pattern of the output bits output from the synthesizing unit 3-4 that synthesizes the output bits of the interleave pattern generation unit 3-2 and the output bits of the binary counter 3-3 is as shown in FIG. 0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15 and the above-mentioned formula 16: (4 (2 × 2) × 4 ( 2 × 2)) matches the multi-stage interleave pattern generated by the interleave operation.
[0049]
FIG. 5 is an explanatory diagram of a second configuration example of the 16-pattern-length multistage interleaved pattern generator of the present invention. In FIG. 5A, 5-1 is a hexadecimal up counter, and 5-2 is a multi-stage interleave pattern generator.
[0050]
The hexadecimal up counter 5-1 includes four flip-flops Q0, Q1, Q2, and Q3, and outputs a bit pattern from a lower bit to a higher bit in this order. That is, the flip-flop Q0 outputs the least significant bit LSB, and the flip-flop Q3 outputs the most significant bit MSB.
[0051]
The multistage interleave pattern generation unit 5-2 replaces the output of the flip-flop Q0 of the hexadecimal up counter 5-1 with the position of the most significant bit, and shifts the output of the flip-flop Q1 to the position of the second most significant bit. In this case, the output of the flip-flop Q2 is replaced with the second least significant bit position, and the output of the flip-flop Q3 is replaced with the least significant bit position.
[0052]
The bit pattern output from the hexadecimal up counter 5-1 is as shown in FIG. The output bit pattern from the multi-stage interleave pattern generator 5-2 in which the output bits of the hexadecimal up counter 5-1 have been exchanged is as shown in FIG. The pattern matches the multi-stage interleave pattern shown in FIG.
[0053]
FIG. 6 is an explanatory diagram of a configuration example of a 32-stage multistage interleaved pattern generator according to the present invention. In FIG. 6A, 6-1 is a 32 decimal up counter, and 6-2 is a multi-stage interleave pattern generator.
[0054]
The 32-decimal up counter 6-1 is composed of five flip-flops Q0, Q1, Q2, Q3, and Q4, and outputs a bit pattern from a lower bit to a higher bit in this order. That is, the flip-flop Q0 outputs the least significant bit LSB, and the flip-flop Q4 outputs the most significant bit MSB.
[0055]
The multistage interleave pattern generation unit 6-2 replaces the output of the flip-flop Q0 of the 32-bit up counter 6-1 with the position of the most significant bit, and shifts the output of the flip-flop Q1 to the position of the second most significant bit. The output of the flip-flop Q2 is set to the same bit position as it is, the output of the flip-flop Q3 is replaced with the second least significant bit position, and the output of the flip-flop Q4 is replaced with the least significant bit position.
[0056]
The bit pattern output from the 32-bit up counter 6-1 is as shown in FIG. The output bit pattern from the multi-stage interleave pattern generation unit 6-2 in which the output bit of the 32-decimal up counter 6-1 has been replaced is as shown in FIG. 6C, and the order of the output bit pattern is as shown in FIG. The patterns are 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30, ... 7, 23, 15, 31.
[0057]
On the other hand, a multistage interleave pattern having a length of 32 patterns is generated as follows by an interleave operation of the formula: 32 (4 (2 × 2) × 8 (4 (2 × 2) × 2)).
[0058]
FIG. 7 shows a procedure for generating a 32-stage multistage interleaved pattern. First, an interleave operation is performed on 32 (4 × 8) of the underlined part a of the expression: 32 × (4 (2 × 2) × 8 (4 (2 × 2) × 2)) shown in FIG. Then, the two-dimensional array pattern shown in FIG.
[0059]
Next, when a vertical interleave operation is performed on 4 (2 × 2) of the underlined part b of the formula: 32 × (4 (2 × 2) × 8 (4 (2 × 2) × 2)), The two-dimensional array pattern shown in (C) is obtained.
[0060]
Next, a horizontal interleave operation is performed on 8 (4 (2 × 2) × 2) of the underlined portion c of the formula: 32 × (4 (2 × 2) × 8 (4 (2 × 2) × 2)). Then, a two-dimensional array pattern shown in FIG.
[0061]
Therefore, the generated multi-stage interleave patterns are 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30,. 23, 15, and 31. This pattern matches the pattern output from the multi-stage interleave pattern generator 6-2 shown in FIG.
[0062]
The 32-stage multistage interleave pattern is the same as the multistage interleave pattern obtained by another calculation formula. As other calculation expressions, Expression: 32 (2 × 16 (4 (2 × 2) × 4 (2 × 2))), Expression: 32 (16 (4 (2 × 2) × 4 (2 × 2)) × 2), Expression: 32 (4 (2 × 2) × 8 (2 × 4 (2 × 2))), Expression: 32 (8 (4 (2 × 2) × 2) × 4 (2 × 2) ), Expression: 32 (8 (2 × 4 (2 × 2)) × 4 (2 × 2)).
[0063]
As inferred from the aforementioned 32-pattern-length multi-stage interleaved pattern generator, the multi-stage interleaved pattern generator having a power-of-two pattern length can be configured as follows.
[0064]
FIG. 8 is an explanatory diagram of a multi-stage interleaved pattern generator having a pattern length of a power of two. 2 ^{n + 1} The binary up counter 8-1 is composed of n + 1 flip-flops Q0, Q1,..., Qn, and outputs a bit pattern from a lower bit to a higher bit in this order. That is, the flip-flop Q0 outputs the least significant bit LSB, and the flip-flop Qn outputs the most significant bit MSB.
[0065]
The multi-stage interleave pattern generation section 8-2 ^{n + 1} The output of the flip-flop Q0 of the binary up counter 8-1 is replaced with the position of the most significant bit, the output of the flip-flop Q1 is replaced with the position of the second most significant bit, and so forth. Are symmetrically exchanged with each other, the output of the flip-flop at the center position is kept at the same bit position, the output of the flip-flop Q (n-1) is replaced with the second lowest bit position, and the output of the flip-flop Qn is Replace with lower bit position.
[0066]
The multi-stage interleave pattern generator having a power-of-two pattern length configured in this manner is the same as a multi-stage interleave pattern generated by performing a multi-stage interleaving operation based on the above-described calculation formula. Generate the pattern of
[0067]
FIG. 9 is an explanatory diagram of a multistage interleaved pattern generator having a pattern length of an arbitrary integer product. In the figure, 9-1 is a first multi-stage interleave pattern generator, 9-2 is a second multi-stage interleave pattern generator, 9-3 is a multiplier, and 9-4 is a bit matching unit. , 9-5 are adders.
[0068]
The first multi-stage interleave pattern generator 9-1 generates a multi-stage interleave pattern of K pattern lengths, and the second multi-stage interleave pattern generator 9-2 generates L multi-stage interleave pattern generators. It is assumed that a multistage interleave pattern having a pattern length of?
[0069]
The second multi-stage interleave pattern generator 9-2 receives, as a clock signal, a carry signal output when the operation of the first multi-stage interleave pattern generator 9-1 is completely completed. , Operate the internal counter.
[0070]
Here, the first and second multi-stage interleave pattern generators 9-1 and 9-2 perform interleaving in as many stages as possible, and when only one stage can be interleaved, A one-stage interleave pattern is generated, and if the integer K or L does not have a divisor, that is, if interleaving is impossible, the bit pattern of the K- or L-ary up-count value is output as it is.
[0071]
As described later, although the integer K or L does not have a divisor, if K or L can be expressed as P × QR (P, Q, and R are integers), P × Q data are Assuming that the data exists, a multistage interleave operation is performed on P × Q data, and K or L multistage interleave patterns are extracted from the resulting multistage interleave patterns. (R patterns may be ignored or excluded) to generate a multi-stage interleaved pattern.
[0072]
The multiplier 9-3 adds the pattern length L of the second multi-stage interleave pattern generator 9-2 to the value of the bit pattern output from the first multi-stage interleave pattern generator 9-1. Multiply.
[0073]
The bit matching unit 9-4 sets the number of bits output from the second multi-stage interleave pattern generator 9-2 to the upper bit in order to match the number of bits output from the multiplier 9-3. 0 "is added.
[0074]
The addition unit 9-5 adds the bit pattern value output from the multiplication unit 9-3 and the bit pattern value output from the bit alignment unit 9-4, and outputs the bit pattern of the added value to the multi-stage Output as an interleave pattern.
[0075]
Hereinafter, as a specific configuration example of the K × L pattern multi-stage interleave pattern generator, a configuration example of a 12-stage multi-stage interleave pattern generator where K = 4 and L = 3 will be described. .
[0076]
FIG. 10 is an explanatory diagram of a configuration example of a multistage interleave pattern generator having a length of 12 patterns. In the figure, 10-1 is a quaternary up counter, 10-2 is a ternary up counter, 10-3 is an MSB-LSB operation circuit, 10-4 is a multiplier, 10-5 is a bit matching circuit, 10-6. Is an adder, and 10-7 is a counter load signal generation circuit.
[0077]
The quaternary up-counter 10-1 includes two flip-flops, outputs a 2-bit bit pattern to the MSB-LSB operation circuit 10-3, and outputs a carry signal to the ternary up-counter 10-2.
[0078]
The MSB-LSB operation circuit 10-3 performs an operation of exchanging the most significant bit MSB and the least significant bit LSB output from the quaternary up counter 10-1. The multiplier 10-4 includes a 1-bit shift circuit and an adder circuit (ADD), and multiplies the bit pattern value output from the MSB-LSB operation circuit 10-3 by "3"("11").
[0079]
The ternary up counter 10-2 counts up the carry signal output from the quaternary up counter 10-1 and outputs a 2-bit ternary count value to the bit matching circuit 10-5.
[0080]
The bit matching circuit 10-5 sets the bit of the bit pattern output from the ternary up counter 10-2 to the number of bits output from the multiplier 10-4 by two bits of "0" on the upper side in order to align the number of bits. I will add
[0081]
The adder 10-6 adds the value of the output bit pattern of the multiplier 10-4 to the value of the output bit pattern of the bit matching circuit 10-5, and outputs the bit pattern of the added value to the multistage interleave signal. Output as a pattern.
[0082]
The counter load signal generation circuit 10-7 counts the 12 bit patterns output from the adder 10-6, and resets the quaternary up counter 10-1 and the ternary up counter 10-2 after the counting is completed. To generate a counter load signal for restarting the counting operation.
[0083]
FIG. 11 is an explanatory diagram of a multistage interleave pattern having a length of 12 patterns. A multistage interleave pattern having a length of 12 patterns is generated as follows by an interleave operation of the formula: 12 (4 (2 × 2) × 3). Note that the multistage interleave pattern obtained by the other equations is also the same.
[0084]
First, when an interleave operation is performed on the underlined part 12 (4 × 3) of the equation: 12 (4 (2 × 2) × 3) in FIG. 11A, a two-dimensional operation shown in FIG. An array pattern is obtained. Next, when a vertical interleave operation is performed on 4 (2 × 2) of the underlined part b of the formula: 12 (4 (2 × 2) × 3), the two-dimensional array pattern shown in FIG. can get. Therefore, the generated multistage interleave patterns are 0, 6, 3, 9, 1, 7, 4, 10, 2, 8, 5, and 11.
[0085]
On the other hand, the bit patterns output from the quaternary up counter 10-1 and the MSB-LSB operation circuit 10-3 shown in FIG. 10 are as shown in FIG. The output of the multiplier 10-4 for multiplying the output value of the MSB-LSB operation circuit 10-3 by "3" is as shown in FIG.
[0086]
Further, the output value of the adder 10-6 for adding the output value of the multiplier 10-4 and the output value of the bit matching circuit 10-5 that has performed the bit matching process of the ternary up counter 10-2 is The result is as shown in FIG.
[0087]
The pattern of the output value of the adder 10-6 is 0, 6, 3, 9, 1, 7, 4, 10, 2, 8, 5, 11, and the multi-pattern having a 12-pattern length shown in FIG. Matches stage interleave pattern.
[0088]
In the multistage interleave pattern generator having a length of 12 patterns described above, the multistage interleave pattern is generated by setting K = 4 and L = 3. In general, the integer K or L has a further divisor, and A multi-stage interleaved pattern generator having a pattern length of an integer m (m = K × L) when interleaving is possible in the direction or the lateral direction is configured as follows.
[0089]
FIG. 12 is an explanatory diagram of a configuration example of such a multistage interleaved pattern generator having a K × L pattern length. In the figure, 12-10 is a K-ary up counter, 12-11 is an MSB-LSB operation circuit, 12-20 is an L-ary up counter, 12-21 is an MSB-LSB operation circuit, 12-3 is a multiplier, 12-12 -4 is a bit matching circuit, 12-5 is an adder, and 12-6 is a counter load signal generation circuit.
[0090]
The K-ary up counter 12-10 and the MSB-LSB operation circuit 12-11 constitute a first multi-stage interleave pattern generator, and the L-ary up counter 12-20 and the MSB-LSB operation circuit 12-21 These form a second multi-stage interleaved pattern generator.
[0091]
The L-ary up counter 12-20 receives the carry signal output from the K-ary up counter 12-10 and counts up. The MSB-LSB operation circuits 12-11 and 12-21 perform the above-described operation of exchanging upper bits and lower bits only when the integer K or L is a power of two.
[0092]
The multiplier 12-3 multiplies the bit pattern output from the MSB-LSB operation circuit 12-11 by the value of the integer L. The bit matching circuit 12-4 sets the upper bits to “bit” in order to match the number of bits of the bit pattern output from the MSB-LSB operation circuit 12-21 with the number of bits of the bit pattern output from the multiplier 12-3. Add 0 ".
[0093]
The adder 12-5 adds the bit pattern value output from the multiplier 12-3 and the bit pattern value output from the bit matching circuit 12-4, and outputs the bit pattern of the added value to the multi-stage Output as an interleave pattern.
[0094]
The counter load signal signal generation circuit 12-6 counts the number of m (= K × L) patterns output from the adder 12-5, and after completion of the counting, the K-ary up counter 12-10 and the L-ary up counter. A counter load signal for resetting the counter 12-20 and restarting the counting operation is generated.
[0095]
Next, a configuration example of a multistage interleaved pattern generator having a 20 × 16 pattern length, which is a product of integers each having a divisor of a power of 2 as described above, will be described. This pattern can be generated by a combination of a multi-stage interleave pattern generator having a length of 20 patterns and a multi-stage interleave pattern generator having a length of 16 patterns.
[0096]
A multistage interleave pattern having a 20 × 16 pattern length is generated by the following calculation formula. Formula: 320 (20 (4 (2 × 2) × 5 (3 × 2)) × 16 (4 (2 × 2) × 4 (2 × 2)))
[0097]
FIG. 13 is an explanatory diagram of a configuration example of a multistage interleaved pattern generator having a 20 × 16 pattern length based on the above calculation formula. In the figure, 13-10 is a multi-stage interleave pattern generator of 20 pattern lengths, 13-20 is a multi-stage interleave pattern generator of 16 pattern lengths, 13-30 is a multiplier (× 16 arithmetic) unit, 13-40 is an adder, and 13-50 is an output circuit.
[0098]
The multi-stage interleave pattern generation unit 13-10 having a length of 20 patterns generates a multi-stage interleave pattern for 20 (4 (2 × 2) × 5 (3 × 2)) patterns which are the vertical direction of the 20 × 16 interleave pattern. A multistage interleave pattern generator 13-11 for generating 4 (2 × 2) patterns in the vertical direction and a multistage for 5 (3 × 2) patterns in the horizontal direction. It comprises an interleave pattern generator 13-12, a multiplier (× 5 operation) unit 13-13, a bit matching circuit 13-14, and an adder 13-15.
[0099]
The 4-stage multistage interleave pattern generator 13-11 is composed of a quaternary counter and an MSB-LSB bit operation circuit, and the output results are 0, 2, 1, and 4.
[0100]
The 5-stage multi-stage interleaved pattern generator 13-12 generates a 5-stage multi-stage interleaved pattern, the specific circuit of which will be described with reference to FIG.
[0101]
When the multi-stage interleaving of the formula: 20 (4 (2 × 2) × 5 (3 × 2)) is actually performed, the result is 0, 10, 5, 15, 2, 12,. The output value of the multi-stage interleave pattern generator 13-11 having a length of 4 patterns is multiplied by "5"("101") by a multiplication (× 5 operation) unit 13-13.
[0102]
The multiplication (× 5 operation) unit 13-13 includes a circuit 13-13a for adding two bits of “0” to the upper bits of the input bits, and moving the input bits to the upper bits of two bits and adding “0” to the lower bits. It is composed of circuits 13-13b for adding two bits and adders 13-13c for adding the outputs of those circuits, and multiplies the value of the input bit by "5".
[0103]
The bit matching circuit 13-14 adds 2 bits of "0" to the upper side of the 3-bit output from the multi-stage interleaved pattern generator 13-12 having a length of 5 patterns, and multiplies (x5 operation). The number of output bits of the unit 13-13.
[0104]
An adder 13-15 adds the output value of the multiplication (× 5 operation) unit 13-13 and the output value of the bit alignment circuit 13-14, and outputs a 20-pattern-length multistage signal from the adder 13-15. Generate an interleave pattern. The processing up to this point is the generation processing of the multi-stage interleave pattern by the expression: 20 (4 (2 × 2) × 5 (3 × 2)).
[0105]
The 16-pattern-length multistage interleave-pattern generating unit 13-20 generates 16 (4 (2 × 2) × 4 (2 × 2)) patterns in the horizontal direction of the aforementioned 20 × 16 interleave pattern. The multi-stage interleave pattern generator generates a multi-stage interleave pattern, and includes a multi-stage interleave pattern generator 13-21 having a length of 16 patterns and a bit matching circuit 13-22.
[0106]
The multi-stage interleave pattern generator 13-21 having a length of 16 patterns is provided with a hexadecimal counter and an MSB-LSB bit operation circuit for exchanging upper and lower bits thereof, as in the above-described embodiment. , And the output result is 0, 8, 4, 12, 2, 10,....
[0107]
The bit matching circuit 13-22 adds 5 bits of "0" to the upper side of the 4-bit output of the multi-stage interleave pattern generator 13-21 having a length of 16 patterns to obtain a 9-bit output. To one input of the unit 13-40.
[0108]
Formula: 320 (20 (4 (2 × 2) × 5 (3 × 2)) × 16 (4 (2 × 2) × 4 (2 × 2)) multi-stage interleave pattern is actually calculated. Since the result is 0, 160, 80, 240, 32, 192,..., The output value of the adder 13-15 is multiplied by “16” by the multiplication (× 16 operation) unit 13-30. ("10000").
[0109]
The multiplication (× 16 operation) unit 13-30 shifts the output bits of the multi-stage interleave pattern generation unit 13-10 having a length of 20 patterns by 4 bits, and adds “0” to the lower bits by 4 bits. Thus, "16" can be multiplied, and the multiplication result is added to the other input of the adder 13-40.
[0110]
An adder 13-40 adds the output value of the multiplication (× 16 operation) unit 13-30 and the output value of the bit matching circuit 13-22, and outputs a 20 × 16 pattern length multi-value from the adder 13-40. A stage interleave pattern is generated.
[0111]
FIG. 14 shows a configuration example of the above-described five-stage multistage interleaved pattern generator 13-12. 14A, 14-1 is a ternary up counter, 14-2 is a binary up counter, 14-3 is a multiplier (× 2 operation) unit, 14-4 is a bit matching circuit, and 14-5 is a bit matching circuit. The adder 14-6 is a counter load signal generation circuit.
[0112]
The ternary up counter 14-1 sequentially outputs the bit patterns of 00 (0), 01 (1), and 10 (2), and the multiplier (× 2 operation) unit 14-3 outputs the ternary up counter 14-1. Is multiplied by "2" to output a bit pattern of 000 (0), 010 (2), 100 (4).
[0113]
The binary up counter 14-2 outputs "1" when a carry signal is input from the ternary up counter 14-1. The bit matching circuit 14-4 adds "0" to the upper bits of the output bit of the binary up counter 14-2 for two bits, and outputs a bit pattern of 000,001.
[0114]
The adder 14-5 adds the output value of the multiplication (× 2 operation) unit 14-3 and the output value of the bit matching circuit 14-4, and calculates 000 (0), 010 (2), 100 (4), The bit patterns of 001 (1) and 011 (3) are output.
[0115]
On the other hand, assuming that an interleave pattern having a pattern length of 5 is calculated by the formula: 5 (3 × 2), the order pattern of 0 to 4 is as shown in FIG. By extracting the numbers of the dimensional array in the vertical direction, patterns of 0, 2, 4, 1, and 3 are generated.
[0116]
Therefore, the pattern generated from the multi-stage interleave pattern generator shown in FIG. 14A matches the multi-stage interleave pattern according to the formula: 5 (3 × 2).
[0117]
The counter load signal generation circuit 14-6 counts the number of five patterns output from the adder 14-5, and resets the ternary up counter 14-1 and the binary up counter 14-2 after the counting is completed. To generate a counter load signal for restarting the counting operation.
[0118]
FIG. 15 is an explanatory diagram of a multi-stage interleaved pattern generator having a reverse pattern generation function according to the present invention. As shown in FIG. 15, the pattern generator includes a count-up / count-down unit 15-1, a multi-stage interleave pattern generation unit 15-2, and a reverse determination unit 15-3.
[0119]
The count-up and count-down unit 15-1 has a count-up and count-down operation function, and switches between a count-up operation and a count-down operation according to a signal from the reverse determination unit 15-3, and an ascending order pattern or a descending order pattern. Generate
[0120]
The multi-stage interleave pattern generation unit 15-2 performs an operation of exchanging upper bits and lower bits of the bit pattern output from the count-up and count-down unit 15-1.
[0121]
The reverse determination unit 15-3 determines whether a reverse instruction has been set, and outputs a signal of a count-down operation to the count-up and count-down unit 15-1 when the reverse instruction has been set.
[0122]
With this configuration, in addition to the above-described normal-order multi-stage interleave pattern, a multi-stage interleave pattern whose order is reversed can be generated by setting a reverse instruction setting.
[0123]
FIG. 16 shows a configuration example of a multi-stage interleave pattern generator having a function of generating a reverse pattern having an eight-pattern length. The multi-stage interleave pattern generator includes an octal up-down counter 16-1, It comprises an MSB-LSB operation circuit 16-2 and a reverse determination unit 16-3.
[0124]
The octal up / down counter 16-1 is set to 000 (0) at the time of up-counting and 111 (7) at the time of down-counting as an initial value. The MSB-LSB operation circuit 16-2 performs an operation of exchanging the most significant bit MSB output from the up / down counter 16-1 and the least significant bit LSB.
[0125]
The up-down counter 16-1 operates at the time of the down-counting operation. 0) are sequentially generated.
[0126]
The MSB-LSB operation circuit 16-2 exchanges the most significant bit MSB and the least significant bit LSB of the above-mentioned bit pattern and obtains 111 (7), 011 (3), 101 (5), 001 (1), 110 ( 6), 010 (2), 100 (4), 000 (0) patterns are sequentially generated.
[0127]
On the other hand, an arithmetic expression for generating a multi-stage interleaved pattern of a reverse pattern is represented by the following expression: R {8 (2 × 4 (2 × 2))}, where R ｛is This means an operation of replacing the multi-stage interleave pattern generated by the calculation formula in the reverse order.
[0128]
The multistage interleave pattern based on the equation: 8 (2 × 4 (2 × 2)) is 0, 4, 2, 6, 1, 5, 3, 7 as described in FIG. The reverse pattern obtained by reversing the order of this pattern is 7, 3, 5, 1, 6, 2, 4, 0, and matches the pattern output from the MSB-LSB operation circuit 16-2. Therefore, the output of the MSB-LSB operation circuit 16-2 is a reverse pattern of the eight-stage multi-stage interleave pattern.
[0129]
【The invention's effect】
As described above, according to the present invention, a complicated multi-stage interleave pattern is generated by a logic circuit such as a counter and a bit permutation operation circuit. Since processing by a processor is not performed, miniaturization, high density, and low power consumption of an LSI circuit and a package board of a multi-stage interleave pattern generator can be achieved. A stage interleave pattern can be generated at high speed.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of a basic configuration of a multistage interleaved pattern generator according to the present invention.
FIG. 2 is an explanatory diagram of 8 (2 × 4 (2 × 2)) and 8 (4 (2 × 2) × 2) multistage interleaving.
FIG. 3 is an explanatory diagram of a multi-stage interleaved pattern generator twice as long as the basic pattern according to the present invention.
FIG. 4 is an explanatory diagram of a multi-stage interleave pattern having a length of 16 patterns.
FIG. 5 is an explanatory diagram of a second configuration example of the multi-stage interleaved pattern generator having a length of 16 patterns according to the present invention.
FIG. 6 is an explanatory diagram of a configuration example of a multi-stage interleaved pattern generator having a 32 pattern length according to the present invention.
FIG. 7 is an explanatory diagram of a multi-stage interleave pattern having a length of 32 patterns.
FIG. 8 is an explanatory diagram of a multi-stage interleaved pattern generator having a power-of-two pattern length according to the present invention.
FIG. 9 is an explanatory diagram of a multistage interleaved pattern generator having a pattern length of an arbitrary integer product according to the present invention.
FIG. 10 is an explanatory diagram of a configuration example of a 12-pattern-length multistage interleaved pattern generator according to the present invention.
FIG. 11 is an explanatory diagram of a multistage interleave pattern having a length of 12 patterns.
FIG. 12 is an explanatory diagram of a configuration example of a K × L pattern multi-stage interleave pattern generator of the present invention.
FIG. 13 is an explanatory diagram of a configuration example of a multistage interleaved pattern generator having a 20 × 16 pattern length according to the present invention.
FIG. 14 is an explanatory diagram of a configuration example of a multi-stage interleaved pattern generator having a 5-pattern length according to the present invention.
FIG. 15 is an explanatory diagram of a multi-stage interleave pattern generator having a reverse pattern generation function according to the present invention.
FIG. 16 is an explanatory diagram of a configuration example of a multistage interleaved pattern generator having a function of generating a reverse pattern having an eight pattern length according to the present invention.
FIG. 17 is an explanatory diagram of a conventional multi-stage interleaved pattern generator.
[Explanation of symbols]
1-1 Count-up section
1-2 Multistage interleave pattern generator

Claims (3)

A multi-stage interleave pattern generator that outputs a count value at least up to the total number of data to be interleaved, and sequentially generates a bit pattern of the count value by a clock signal ,
A multi-stage interleaved pattern generator, wherein said count value is the product of positive integers K and L, and said integer K has a power of 2 ;
A K-ary counter that counts up each time a clock signal is input to the integer K value, an L-ary counter that counts up the carry signal output from the K-ary counter to the integer L value, A multi-stage interleave pattern generator for symmetrically exchanging higher-order bits and lower-order bits with respect to the output bit pattern; and a bit pattern output from the multi-stage interleave pattern generator. A multistage interleave pattern comprising: a multiplier for multiplying a value by the integer L; and an adder for adding an output value of the multiplier to a bit pattern value obtained from an L-ary counter. Generator. In the multistage interleave pattern generator in which the integer L has a divisor of a power of two, a second bit for symmetrically exchanging upper bits and lower bits output from an L-ary counter. A multi-stage interleave pattern generator, wherein the adder is configured to add a bit pattern value output from the second multi-stage interleave pattern generator and an output value of the multiplier. 2. The multi-stage interleaved pattern generator according to claim 1 , wherein: The K-base or L-base counter is configured to have a function of a count-up operation for generating a count value in an ascending order and a count-down operation for generating a count value in a descending order. multistage interleave pattern generator according to claim 1 or 2, further comprising a reverse determination unit for switching the count-down operation.

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