JP3589235B2 - Analog signal delay circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a delay circuit used for delaying an analog signal and suitable for being incorporated in an integrated circuit.
[0002]
[Prior art]
2. Description of the Related Art In a delay circuit provided inside a high-density integrated circuit (hereinafter abbreviated as LSI), a plurality of memory cells each including a switch and a capacitor are connected in parallel, and a voltage of an analog signal is sequentially stored in each memory cell. In some cases, the analog signal is delayed by reading out the accumulated analog signal after a predetermined time has elapsed.
[0003]
FIG. 13 is a circuit diagram of a conventional delay circuit. In the figure, M1 to Mn are n memory cells connected in parallel, in which the voltage of an analog signal is stored. The memory cell M1 includes an input switch SW1, a capacitor C1, and an output switch SW1 ', and the other memory cells M2 to Mn have the same configuration as the memory cell M1. A voltage follower including an operational amplifier OP is provided on the output side of the memory cells M1 to Mn. Note that Cp is a parasitic capacitance generated on the output side of the memory cells M1 to Mn.
[0004]
In the above configuration, when writing the input analog signal Vin, the input switches SW1 to SWn are sequentially turned on in the order of SW1, SW2,..., SWn, SW1,. The sample and hold is performed, and the voltage is stored in the capacitors C1 to Cn. Next, when the stored input analog signal Vin is read, the output switches SW1 ′ to SWn ′ are sequentially turned on in the order of SW1 ′ → SW2 ′ →... SWn ′ → SW1 ′. Input analog signals Vin are sequentially read.
[0005]
In this case, the input analog signal Vin is written to the memory cells M1 to Mn-1, and the input analog signal Vin is written to the memory cell Mn at the next sampling timing, and at the same time, the input analog signal delayed from the memory cell M1 is input. The signal Vin is read and output from the operational amplifier OP as an output analog signal Vout. That is, the memory cells M1 to Mn repeat the write operation and the read operation in a ring shape. Here, assuming that a sampling period (a period in which each switch is in an ON state) is Ts, a delay time Td is given by Td = (n-1) * Ts.
[0006]
[Problems to be solved by the invention]
By the way, when the delay circuit described above is configured inside the LSI, the values of the capacitors C1 to Cn are several pF, so that their impedance is high even in a low frequency region. Therefore, when the delay circuit receives low-frequency disturbance noise (for example, hum synchronized with the frequency of the commercial AC power supply), the voltage values of the capacitors C1 to Cn fluctuate. Therefore, low-frequency disturbance noise is superimposed on the input analog signal Vin read from the memory cells M1 to Mn. If the noise component exists in a higher frequency region than the band of the signal component, the noise component can be removed from the output analog signal Vout by a low-pass filter. Is within the signal band, it is difficult to remove noise components from the output analog signal Vout. Therefore, there is a problem that the SN ratio is deteriorated even if the delay circuit of the above-described type is configured inside the LSI.
[0007]
Further, the above-described delay circuit has a problem that the voltages stored in the capacitors C1 to Cn of the memory cells M1 to Mn cannot be accurately read due to the influence of the parasitic capacitance Cp.
For example, if the switch SW1 is turned on and the voltage is read from the capacitor C1 of the memory cell M1, and then the switch SW1 is turned off, the voltage of the parasitic capacitance Cp is determined according to the voltage stored in the capacitor C1. It becomes. In this state, the voltage of the parasitic capacitance Cp is Vs ′, the value of the parasitic capacitance Cp is Cb, in the memory cell M2, the value of the capacitor C2 is Ca, the voltage of the capacitor C2 before reading is Vs, and the voltage of the capacitor C2 after reading is Assuming that the voltage (the voltage actually read) is Vs ″, Vs ″ is given by the following equation.
Vs ″ = (CaVs + CbVs ′) / (Ca + Cb)
That is, the voltage that should be read as Vs originally changes to Vs ″ due to the action of the parasitic capacitance Cp. Moreover, since the value Cb of the parasitic capacitance Cp has a voltage dependency, the parasitic capacitance Cp also causes distortion of the output analog signal Vout.
[0008]
The present invention has been made in view of the above circumstances, and has as its object to provide a delay circuit that can remove low-frequency noise disturbance. Another object is to provide a delay circuit which is not affected by parasitic capacitance.
[0010]
[Means for Solving the Problems]
To solve the above problems, Claim 1 According to the invention described in (1), there is provided a delay circuit including a plurality of memory cells that store an analog signal by accumulating a charge in a capacitor, and generates an input current signal by converting an input voltage signal into a current. Voltage-current converting means, writing means for sequentially writing the input current signal to the plurality of memory cells, reading means for sequentially reading the input current signals stored from the plurality of memory cells in a writing order, Current voltage conversion means for converting the input current signal read by the reading means into a voltage to generate an output voltage signal.
[0012]
Claims 2 In the invention described in (1), the memory cell includes a first switch means having one end connected to the input terminal, and a second switch means provided between the output terminal and the other end of the first switch. Switch means, third switch means provided between the other end of the first switch means and one end of the capacitor, and a gate connected to one end of the capacitor and the other end of the capacitor A field effect transistor having a source and a drain connected between the other end of the first switch means.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
A. First embodiment
Hereinafter, a delay circuit according to an embodiment of the present invention will be described with reference to the drawings.
[0014]
1. Configuration of the first embodiment
FIG. 1 is a circuit diagram of a delay circuit according to the first embodiment of the present invention.
In the figure, M1 to Mn are memory cells, and each of the memory cells M1 to Mn is a capacitor C1 to Cn having one end grounded, and an input switch SW1 provided between the other end of the capacitors C1 to Cn and the input side. To SWn, and output switches SW1 ′ to SWn ′ provided between the other ends of the capacitors C1 to Cn and the output side. Here, the input switches SW1 to SWn are turned on when the control signals φ1 to φn are at a high level. The output switches SW1 ′ to SWn ′ are similarly turned on when the control signals φ1 ′ to φn ′ are at a high level. It is configured to be turned off when it is at a low level.
[0015]
Next, reference numeral 10 denotes an inverting circuit having a gain of 1, and its output impedance is set to low impedance. An input analog signal Vin is supplied to an input side of the inverting circuit 10, and memory cells M2, M4,... Mn are connected to the output side. Therefore, the inverted input analog signal Vin is supplied to the even-numbered memory cells M2, M4,... Mn, and the voltage is applied to the capacitors C2, C4,. Will be accumulated. On the other hand, to the odd-numbered memory cells M1, M3,... Mn-1, the input analog signal Vin is supplied at a low impedance from a buffer circuit (not shown). Therefore, in the odd-numbered memory cells M1, M3,... Mn-1, the voltage of the input analog signal Vin is applied to the capacitors C1, C3,. Will be accumulated.
[0016]
Next, 20 is an inverting circuit of gain 1 provided on the output side of the even-numbered memory cells M2, M4,... Mn. As described above, the inverted input analog signal Vin is written in the memory cells M2, M4,... Mn. However, since the inverted input analog signal Vin is again inverted and read by the inverting circuit 20, the polarity of the output signal of the inverting circuit 20 is It matches the polarity of the input analog signal Vin.
Next, SW0 is a switch, which is configured to conduct to the terminal Sa when the control signal φ0 is at a high level and to conduct to the terminal Sb when the control signal φ0 is at a low level. By the switch SW0, the output signals from the odd-numbered memory cells M1, M3,... Mn-1 and the output signals from the even-numbered memory cells M2, M4,. As a result, the two signals are combined, and an output analog signal Vout obtained by delaying the input analog signal Vin is generated.
Next, reference numeral 30 denotes a control circuit constituted by a shift register or the like. The control circuit 30 is configured to generate control signals φ1 to φn, φ1 ′ to φn ′, φ0 for controlling the switches SW1 to SWn, SW1 ′ to SWn ′, and SW0 based on the clock signal CLK. The frequency of the clock signal CLK is set to be at least twice as high as the signal band frequency of the input analog signal Vin. Further, a low-pass filter (not shown) capable of sufficiently removing a clock component is provided at a stage subsequent to the delay circuit. This low-pass filter has a flat frequency characteristic in the frequency band of the input analog signal Vin, and has a sufficient attenuation characteristic near the sampling frequency.
[0017]
With the above configuration, when the input analog signal Vin is written, each input switch is controlled to be sequentially turned on in the order of SW1, SW2,..., SWn, SW1, and so on, and the input analog signal Vin becomes the clock signal CLK. Samples are held synchronously. Next, when reading the input analog signal Vin, each output switch is controlled so as to be sequentially turned on in the order of SW1 ′ → SW2 ′ →... SWn ′ → SW1 ′. It is read out in synchronization with CLK. Thus, when the output analog signal Vout is generated, the clock component is removed by the low-pass filter.
[0018]
Therefore, the input analog signal Vin is written into the memory cells M1 to Mn while alternately repeating the normal rotation and inversion every sampling cycle, and the inverted input analog signal Vin is again inverted and read at the time of reading. In such a delay circuit, when low-frequency disturbance noise acts, the voltage stored in the capacitors C1 to Cn fluctuates. However, when reading the stored voltage from each of the memory cells M1 to Mn, the readout is performed while alternately repeating the normal rotation and inversion for each sampling cycle, so that the disturbance noise superimposed on the output analog signal Vout is modulated at the sampling frequency. It will be. Therefore, the disturbance noise in the signal band can be frequency-shifted to the vicinity of the sampling frequency, so that the disturbance noise can be removed by the above-described low-pass filter.
[0019]
2. Operation of the first embodiment
Next, the operation of the delay circuit according to the first embodiment will be described. FIG. 2 is a timing chart showing the operation of the delay circuit according to the first embodiment. Assuming that the input analog signal Vin shown in FIG. 2A is supplied to the delay circuit from the time t0, the control signal φ1 shown in FIG. 2B is supplied to the input switch SW1. As described above, since the switch SW1 is turned on when the control signal φ1 becomes high level, the input analog signal Vin during the period from time t0 to t1 is taken into the memory cell M1. Further, as shown in FIGS. 2B to 2E, the control signals φ2 to φn are obtained by shifting the control signal φ1 every sampling period. Therefore, writing is performed in the order of M1 → M2 →... Mn. However, the inverted input analog signal Vin is written to the even-numbered memory cells M2, M4,... Mn.
[0020]
Here, if the delay time is set to 7 sampling cycles, the control signal φ1 ′ becomes as shown in FIG. 2F, and the output switch SW1 ′ is turned on from time t7 to t8, and the control signal φ1 ′ is connected to the capacitor C1 of the memory cell M1. The stored voltage is read. In addition, the control signals φ2 ′ to φn ′ are obtained by shifting the control signal φ1 ′ every sampling period, as shown in FIGS. Therefore, reading is performed in the order of M1 → M2 →... Mn.
[0021]
When the signal is read from each of the memory cells M1 to Mn in this manner, the signal read from the odd-numbered memory cell is supplied to the terminal Sa of the switch SW0, and the signal read from the even-numbered memory cell is inverted by the inverting circuit 20. Is supplied to the terminal Sb. The switch SW0 selects the terminal Sa when the control signal φ0 is at a high level, and selects the terminal SWb when the control signal φ0 is at a low level. Therefore, the switch SW0 is controlled by the control signal φ0 shown in FIG. Then, the output analog signal Vout shown in FIG. 2 (k) is obtained. For example, in the period from time t7 to t8, the final value (the value at time t1) of the input analog signal Vin from time t0 to time t1 is output.
[0022]
Now, the operation of removing low-frequency noise in this example will be described with reference to timing charts shown in FIGS. Note that the waveform shown in the figure omits the hold effect of the capacitor for easy understanding. Now, assuming that the input analog signal Vin shown in FIG. 3A is supplied to the delay circuit, the signals stored in the memory cells M1 to M8 are inverted every sampling period as shown in FIG. It will be.
[0023]
As described above, since the values of the capacitors C1 to Cn built in the LSI are several pF, the impedance of each of the capacitors C1 to Cn is high even in a low frequency region, so that the capacitors C1 to Cn are held by low frequency noise such as hum. The voltage fluctuates. For example, if the noise voltage shown in FIG. 3C is superimposed on the capacitors C1 to C8, the signals stored in the memory cells M1 to M8 are as shown in FIG.
[0024]
Therefore, the output analog signal Vout becomes a solid line shown in FIG. In this case, since the noise component is the difference between the input analog signal Vin indicated by the dotted line and the output analog signal Vout indicated by the solid line, the noise signal superimposed on the output analog signal Vout is as shown in FIG. . Here, comparing the noise signal shown in FIG. 3C with the noise signal shown in FIG. 4C, it can be seen that the signal shown in FIG. 4C is modulated at the sampling frequency. That is, according to this delay circuit, the frequency component of the low-frequency noise component can be converted to the high-frequency near the sampling frequency. For example, if the sampling frequency is fs and the frequency of the noise signal is fn, the frequency of the frequency-converted noise signal is fs-fn, fs + fn.
[0025]
By the way, as described above, the low-pass filter for removing the sampling frequency component is provided at the subsequent stage of the delay circuit, so that the noise signal frequency-converted around the sampling frequency is removed by this low-pass filter. . Therefore, a noise signal superimposed on the output analog signal Vout can be removed.
[0026]
As described above, according to the present embodiment, the memory cell input analog signal Vin is alternately inverted and written when writing to the memory cells M1 to Mn, and is alternately inverted and read again when reading the same. Therefore, even if low-frequency noise is mixed during the period in which the input analog signal Vin is stored in the memory cells M1 to Mn, the low-frequency noise can be frequency-converted to near the sampling frequency. The low frequency noise that could not be separated can be removed from the output analog signal Vout to improve the SN ratio.
[0027]
B. Second embodiment
Hereinafter, a delay circuit according to another embodiment of the present invention will be described with reference to the drawings.
[0028]
1. Configuration of the second embodiment
FIG. 5 is a circuit diagram of a delay circuit according to the second embodiment of the present invention.
In the figure, the internal configuration of the memory cells M1 to Mn is the same as in the first embodiment. In this example, the memory cells M1 to Mn are connected in parallel, the input side of each of the memory cells M1 to Mn is connected to the input line Lin, and the output side is connected to the output line Lout. Have been. A parasitic capacitance Cp having voltage dependency exists between the output line Lout and the ground.
[0029]
A capacitor Cs and a switch SW0 are provided between the negative input terminal and the output terminal of the operational amplifier 40, and the positive input terminal is grounded. As the operational amplifier 40, one having a high input impedance and a sufficiently large gain is used. As a result, the negative input terminal and the positive input terminal of the operational amplifier 40 are imaginarily short-circuited. Therefore, the voltage of the positive input terminal is always a constant voltage, in this example, the ground level.
[0030]
When reading the voltage stored in the memory cell M1, the input switch SW1 and the switch SW0 are turned off, and in this state, the output switch SW1 'is turned on. Since the output line Lout is virtually grounded, when each switch is operated as described above, the electric charge accumulated in the capacitor C1 moves to the capacitor Cs. Here, the value of the capacitor Cs is set to be equal to the values of the capacitors C1 to Cn. Therefore, the voltage at the node A matches the voltage stored in the capacitor C1. Therefore, the voltage stored in each of the memory cells M1 to Mn can be read without being affected by the parasitic capacitance Cp.
[0031]
In this case, when reading the voltage stored in the next memory cell, if the charge read from the previous memory cell is accumulated in the capacitor Cs, the voltage stored in the next memory cell and the voltage stored in the previous memory cell are stored in the capacitor Cs. The stored voltage is added by the capacitor Cs. Therefore, it is necessary to clear the charge stored in the capacitor Cs every time reading from each of the memory cells M1 to Mn. The switch SW0 is provided for this purpose, and is turned on before reading a voltage from the next memory cell, and is configured to clear the charge accumulated in the capacitor Cs.
[0032]
By the way, since the voltage of the capacitor Cs is cleared every time the voltage is read from the memory cells M1 to Mn, the voltage of the node A changes like a chopper in synchronization with the operation of the switch SW0. For this reason, in this example, the output analog signal Vout is generated by converting the voltage of the node A into a continuous one by the sample and hold circuit. Specifically, a sample-and-hold circuit is configured by the operational amplifier 50 and the operational amplifier 60 constituting the voltage follower, the switch SW0 ′, and the capacitor Ch.
[0033]
Next, reference numeral 30 denotes a control circuit constituted by a shift register or the like, which controls control signals φ1 to φn, φ1 for controlling the switches SW1 to SWn, SW1 ′ to SWn ′, SW0, SW0 ′ based on the clock signal CLK. '~ Φn', φ0, φ0 '. Further, a low-pass filter (not shown) that can sufficiently remove the clock component is provided at the subsequent stage of the delay circuit as in the first embodiment. This low-pass filter has a flat frequency characteristic in the frequency band of the input analog signal Vin, and has a sufficient attenuation characteristic near the sampling frequency.
[0034]
2. Operation of the second embodiment
Next, the operation of the delay circuit according to the second embodiment of the present invention will be described. FIG. 6 is a timing chart showing the operation of the delay circuit according to the second embodiment. Assuming that the input analog signal Vin shown in FIG. 6A is supplied to the delay circuit and the input switches SW1 to SWn are controlled by the control signals φ1 to φn shown in FIGS. 6B to 6D, the input at time t1 The voltage at each timing is sequentially stored such that the analog signal Vin is stored in the memory cell M1 and the input analog signal Vin at time t2 is stored in the memory cell M2.
[0035]
Thereafter, when the control signals φ1 ′ to φn ′ shown in FIGS. 6E to 6F are supplied to the switches SW1 ′ to SWn ′, the voltages stored in the memory cells M1 to Mn are sequentially read. , The voltage of the node A has a chopper-like waveform as shown in FIG. When the voltage of the node A is sampled and held based on the control signal φ0 ′ shown in FIG. 6 (j), an output analog signal Vout shown in FIG. 6 (k) is obtained.
[0036]
Here, a detailed timing chart at the time of reading is shown in FIG. FIG. 7A shows a control signal φ0, in which the switch SW0 is on while the signal is at the low level, and the switch SW0 is off during the high level. In this example, first, during the period from time t0 to time t1, the switch SW0 is turned on, so that the charge of the capacitor Cs is cleared. The time during which the switch SW0 is turned on is set in consideration of a time constant determined by the value of the capacitor Cs and the on-resistance of the switch SW0 so that the electric charge accumulated therein is sufficiently cleared. Therefore, at time t1, the charge of the capacitor Cs is sufficiently cleared, and the preparation for reading from the memory cell is completed.
[0037]
Thereafter, in order to read a voltage from the k-th memory cell Mk, a control signal φk ′ shown in FIG. 7B is applied to the output switch SWk. The control signal φk ′ changes from the low level to the high level at time t2 after the control signal φ0 changes from the low level to the high level and the switch SW0 is turned off. Then, the capacitor Ck of the k-th memory cell Mk is connected to the output line Lout, so that the electric charge accumulated in the capacitor Ck moves to the capacitor Cs. Here, since the negative input terminal of the operational amplifier 40 is virtually grounded, no charge moves to the parasitic capacitance Cp, and all charges can move to the capacitor Cs. For this reason, the voltage stored in the memory cell can be accurately read without being affected by the parasitic capacitance Cp.
[0038]
When the charge moves to the capacitor Cs, the control signal φk ′ changes from the high level to the low level at time t4, and the output switch SWk ′ is turned off. At time t4, the control signal φ0 ′ changes from the low level to the high level, the switch SW0 ′ is turned on, and the voltage of the node A is held by the capacitor Ch. Thereafter, at time t5, when the control signal φ0 ′ changes from the high level to the low level, the switch SW0 ′ is turned off, and the voltage of the capacitor Ch is held until the switch SW0 ′ is turned on next time.
[0039]
Thereafter, at time t6, when the control signal φ0 changes from the high level to the low level, the switch SW0 is turned on again, and the electric charge stored in the capacitor Cs is cleared. Then, at time t7, when the switch SW0 is turned off and read preparation is completed, at time t8, the control signal φk + 1 ′ shown in FIG. 7D changes from the low level to the high level, and the control signal φk + 1 ′ changes from the (k + 1) th memory cell Mk + 1. , The stored voltage is read. Hereinafter, the same operation is repeated, and the voltages stored therein are sequentially read from each of the memory cells M1 to Mn.
[0040]
As described above, according to the present embodiment, the operational amplifier 40 that is virtually grounded is provided on the output side of the memory cells M1 to Mn, and the charge accumulated in the capacitor Cs is cleared at each sampling cycle. The voltage stored in each of the memory cells M1 to Mn can be accurately read out without being affected by the parasitic capacitance Cp. In particular, when several hundreds to thousands of memory cells are connected in parallel, the value of the parasitic capacitance Cp increases, so that the quality of the output analog signal Vout can be significantly improved.
[0041]
C. Third embodiment
In the delay circuits of the first and second embodiments described above, the input analog signal Vin is stored in each of the memory cells M1 to Mn in the voltage mode. On the other hand, the delay circuit of the third embodiment operates in the current mode in the input analog signal Vin. The signal Vin is stored. Hereinafter, the delay circuit according to the third embodiment will be described with reference to the drawings.
[0042]
1. Configuration of Third Embodiment
FIG. 8 is a circuit diagram of a delay circuit according to the third embodiment of the present invention.
In the figure, a voltage-to-current converter 70 performs a well-known voltage-to-current conversion including a current mirror circuit and the like, and outputs an input current Ii corresponding to the voltage of an input analog signal Vin.
[0043]
Next, the memory cells M1 ′ to Mn ′ have a configuration corresponding to the memory cells M1 to Mn described in the first and second embodiments. However, the memory cells M1 ′ to Mn ′ are different from the memory cells M1 to Mn that store voltage values in that they store current values. The memory cells M1 ′ to Mn ′ include input switches SW1 to SWn each having one end connected to the input line Lin, switches SW1 ″ to SWn ″ each having one end connected to the other end of the input switches SW1 to SWn, and a switch SW1 ′. Capacitors C1 to Cn provided between the other ends of '' to SWn 'and the ground, the sources are connected to the other ends of the input switches SW1 to SWn, the gates are connected to the capacitors C1 to Cn, and the drains are grounded. N-channel FETs N1 to Nn. The input switches SW1 to SWn, the output switches SW1 ′ to SWn ′ and the switches SW1 ″ to SWn ″ are turned on when the control signals φ1 to φn, φ1 ′ to φn ′, and φ1 ″ to φn ″ are at a high level. State. It is configured to be turned off when it is at a low level.
[0044]
For example, when writing the input current Ii to the memory cell M1 ′, the input switch SW1 and the switch SW1 ″ are turned on, and the switch SW1 ′ is turned off. Then, the input current Ii flows to the ground via the N-channel FET N1. In this case, the voltage value (gate voltage value) of the capacitor C1 is a value that allows the N-channel FET N1 to flow the input current Ii. Then, when the writing period ends, the input switch SW1 and the switch SW1 ″ are turned off. Since the input impedance of the gate of the N-channel FET N1 is extremely high, the voltage at the end of the writing period is held in the capacitor C1. That is, a voltage corresponding to the input current Ii is stored in the capacitor C1.
[0045]
On the other hand, when reading a current from the memory cell M1 ', the input switch SW1 and the switch SW1''are turned off and the output switch SW1' is turned on. Then, the N-channel FET N1 sinks the output current Io according to the voltage (gate voltage) of the capacitor C1 from the output line Lout. In this case, since the output current Io does not fluctuate under the influence of the parasitic capacitance Cp, the current value stored in the memory cell can be accurately read.
[0046]
Next, reference numeral 80 denotes a current-voltage converter, which is composed of an operational amplifier and a resistor. The output current Io is converted into a voltage by the current / voltage converter 80, and the voltage is output as an output analog signal Vout.
[0047]
Next, reference numeral 30 denotes a control circuit constituted by a shift register or the like, and control signals φ1 to SWn ″ for controlling the switches SW1 to SWn, SW1 ′ to SWn ′, and SW1 ″ to SWn ″ based on the clock signal CLK. φn, φ1 ′ to φn ′, and φ1 ″ to φn ″ are generated. Further, a low-pass filter (not shown) that can sufficiently remove the clock component is provided at the subsequent stage of the delay circuit as in the first embodiment. This low-pass filter has a flat frequency characteristic in the frequency band of the input analog signal Vin, and has a sufficient attenuation characteristic near the sampling frequency.
[0048]
2. Operation of the third embodiment
Next, the operation of the delay circuit according to the third embodiment will be described with reference to the drawings. FIG. 9 is a timing chart of the delay circuit according to the third embodiment. In the delay circuit in this example, when the input analog signal Vin shown in FIG. 9A is supplied to the delay circuit, it is converted into an input current Ii shown in FIG. 9H. Here, input switches SW1 to SWn are controlled by control signals φ1 to φn shown in FIGS. 9B to 9D, and switches SW1 ″ to SWn ″ are controlled by control signals φ1 ″ to φn ″. Then, the current value at each timing is sequentially stored, such as the value of the input current Ii at the time t1 in the memory cell M1, the value of the input current Ii at the time t2 as the memory cell M2, and so on. In this example, the pulse widths of the control signals φ1 to φn and the pulse widths of the control signals φ1 ″ to φn ″ are described as being equal to each other. The pulse width may be set slightly wider than the pulse width of φ1 ″ to φn ″.
[0049]
Thereafter, when the control signals φ1 ′ to φn ′ shown in FIGS. 9E to 9F are supplied to the switches SW1 ′ to SWn ′, the switches SW1 ′ to SWn ′ are sequentially turned on, and each N An output current Io according to the gate voltages of the channel FETs N1 to Nn is drawn from the output line Lout. Here, the gate voltages of the N-channel FETs N1 to Nn are given as voltages of the capacitors C1 to Cn, and each of the capacitors C1 to Cn stores a voltage enough to absorb the input current Ii at the end of each writing period. ing. Therefore, each of the N-channel FETs N1 to Nn sinks the output current Io having the same value as the stored input current Ii from the output line Lout. As a result, the output current Io is as shown in FIG. Thereafter, the output current Io is converted into a voltage by the current-voltage converter 80, and an output analog signal Vout shown in FIG. 9 (j) is obtained.
[0050]
As described above, in the present embodiment, the input analog signal Vin is voltage-current converted, the converted current value is stored in each of the memory cells M1 ′ to Mn ′, read out, and the output analog signal Vout is converted. Since the reproduction is performed, when the current is read from the memory cells M1 ′ to Mn ′, the stored current value can be accurately read without being affected by the parasitic capacitance Cp. As a result, a high-quality output analog signal Vout can be obtained.
[0051]
Further, in the second embodiment, when the voltage is read from each of the memory cells M1 to Mn, the electric charge accumulated in the capacitors C1 to Cn is moved to the capacitor Cs. Is limited to one time, but in the delay circuit according to the third embodiment, reading from the memory cells M1 ′ to Mn ′ is performed in the form of current, so that reading can be performed a plurality of times. .
[0052]
Further, since a voltage enough to allow the input current Ii to flow through each of the N-channel FETs N1 to Nn is held in each of the capacitors C1 to Cn, there is no problem even if the values of the capacitors C1 to Cn vary. Further, since the value of each of the capacitors C1 to Cn may be very small, it can be substituted by the parasitic capacitance of the gate. In this case, there is no need to specially form the capacitors C1 to Cn.
[0053]
D. Fourth embodiment
The delay circuit according to the fourth embodiment is a combination of the first embodiment and the second embodiment. Hereinafter, a delay circuit according to the fourth embodiment will be described with reference to the drawings.
[0054]
FIG. 10 is a circuit diagram of a delay circuit according to the fourth embodiment of the present invention. The same components as those shown in FIGS. 1 and 5 are denoted by the same reference numerals.
In this example, similarly to the first embodiment, the input analog signal Vin is supplied to each of the odd-numbered memory cells M1, M3,... Mn-1, and the input analog signal inverted by the inversion circuit 10. Vin is supplied to each of the even-numbered memory cells M2, M4,... Mn-1. Therefore, the input analog signal Vin is written into the memory cells M1 to Mn while alternately repeating normal rotation and inversion every sampling cycle.
[0055]
A virtual grounded operational amplifier 40 is provided on the output side of the odd-numbered memory cells M1, M3,... Mn-1, while the output side of the even-numbered memory cells M2, M4,. Is provided with an operational amplifier 40 'that is virtually grounded, and in this regard, is similar to the second embodiment. Therefore, the negative input terminal voltages of the operational amplifiers 40 and 40 'are always at the ground level, so that the input analog signal Vin stored in each of the memory cells M1 to Mn is read without being affected by the parasitic capacitances Cp and Cp'. be able to. The switches SW0 and SW0 'connected in parallel to the capacitors Cs and Cs' are turned on before reading the voltage from the next memory cell, and function as reset means for clearing the charge.
[0056]
Next, an addition circuit 41 having a positive input terminal 41a and a negative input terminal 41b is provided on the output side of the operational amplifiers 40 and 40 '. The adder circuit 41 includes an operational amplifier and a resistor. The output signal of the operational amplifier 40 is supplied to the positive input terminal 41a, and the output signal of the operational amplifier 40 'is supplied to the negative input terminal 41b. Therefore, the signals output from the even-numbered memory cells M2, M4,... Mn are again inverted and added to the signals output from the odd-numbered memory cells M1, M3,. Is output. Further, the control circuit 30 generates control signals φ1 to φn, φ1 ′ to φn ′, φ0, and φ0 ′ based on the clock signal CLK. Further, a low-pass filter (not shown) that can sufficiently remove the clock component is provided at the subsequent stage of the delay circuit as in the first embodiment. This low-pass filter has a flat frequency characteristic in the frequency band of the input analog signal Vin, and has a sufficient attenuation characteristic near the sampling frequency.
[0057]
Therefore, in this example, as in the first embodiment, even if low-frequency noise is mixed in the memory cells M1 to Mn, the low-frequency noise can be frequency-converted to near the sampling frequency. The low frequency noise that could not be removed can be removed from the output analog signal Vout to improve the SN ratio. Further, similarly to the second embodiment, the voltage stored in each memory cell can be read without being affected by the parasitic capacitance.
[0058]
As described above, according to the fourth embodiment, the advantages of removing the low-frequency noise of the first embodiment and avoiding the adverse effect of the parasitic capacitance of the second embodiment can be realized at the same time. A signal can be obtained.
[0059]
E. FIG. Fifth embodiment
The delay circuit according to the fifth embodiment is a combination of the first embodiment and the third embodiment. Hereinafter, the delay circuit according to the fifth embodiment will be described with reference to the drawings.
[0060]
FIG. 11 is a circuit diagram of a delay circuit according to the fifth embodiment of the present invention. The same components as those shown in FIGS. 1 and 8 are denoted by the same reference numerals.
In this example, the voltage value of the input analog signal Vin is converted into a current value by the non-inversion voltage / current conversion unit 70, and the odd-numbered memory cells M1 ′, M3 ′,. -1 '. Further, the inverted voltage value of the input analog signal Vin is converted into a current value by the inverted voltage / current converter 70 ′, and the inverted input analog signal Vin is converted into the even-numbered memory cells M2 ′, M4 ′,. Each is supplied. Therefore, a current corresponding to the input analog signal Vin is written to the memory cells M1 'to Mn' while alternately repeating normal rotation and inversion every sampling cycle.
[0061]
Also, current-voltage converters 80, 80 'are provided on the output sides of the odd-numbered memory cells M1', M3 ',... Mn-1' and the even-numbered memory cells M2 ', M4',. Thus, the normal output current Io and the inverted output current Io ′ are current-voltage converted. Note that the write / read operation of each of the memory cells M1 ′ to Mn ′ is performed by the control circuit 30 using control signals φ1 to φn, φ1 ′ to φn ′, and φ1 ″ to φn ′ generated based on the clock signal CLK. Is controlled by The output signal of the current-voltage converter 80 is supplied to the negative input terminal 41b of the adder circuit 41, while the output signal of the current-voltage converter 80 'is supplied to the positive input terminal 41a. Here, since the output signal of the current-voltage conversion unit 80 'and the output signal of the current-voltage conversion unit 80 have inverted amplitude polarities, the addition circuit 41 combines the two signals while making the amplitude polarities uniform. , The delayed input analog signal Vin can be reproduced. Further, a low-pass filter (not shown) that can sufficiently remove the clock component is provided at the subsequent stage of the delay circuit as in the first embodiment. This low-pass filter has a flat frequency characteristic in the frequency band of the input analog signal Vin, and has a sufficient attenuation characteristic near the sampling frequency.
[0062]
Therefore, in this example, as in the first embodiment, even if low-frequency noise is mixed in the memory cells M1 to Mn, the low-frequency noise can be frequency-converted to near the sampling frequency. The low frequency noise that could not be removed can be removed from the output analog signal Vout to improve the SN ratio. Further, similarly to the third embodiment, the current can be accurately read from each of the memory cells M1 ′ to Mn ′ without being affected by the parasitic capacitance, and the current can be read from the same memory cell a plurality of times.
[0063]
As described above, according to the fifth embodiment, the advantages of removing the low-frequency noise of the first embodiment and avoiding the adverse effect of the parasitic capacitance of the third embodiment can be realized at the same time. A signal can be obtained.
[0064]
F. Modified example
The embodiment according to the present invention has been described above, but the present invention is not limited to the above-described embodiment, and various modifications described below are possible.
{Circle around (1)} The delay circuits of the above embodiments can be used, for example, as echoes in a karaoke apparatus. In this case, the output analog signal Vin of the delay circuit is multiplied by a coefficient, the result is added to the input analog signal, and this is input to the delay circuit. The delay circuit may be used not only for audio signals but also for video signals.
[0065]
{Circle around (2)} In each of the above-described embodiments, since the write operation to each of the memory cells M1 to Mn corresponds to sampling, if the signal band of the input analog signal Vin is wide, aliasing occurs. For this reason, a low-pass filter having a cut-off frequency corresponding to the sampling period may be provided in the preceding stage of the above-described delay circuit so that aliasing distortion does not occur. Further, this low-pass filter may be realized by appropriately setting the frequency characteristics of the voltage-current converters 70 and 70 'of the third and fifth embodiments.
[0066]
{Circle around (3)} In the first, third, and fifth embodiments described above, the read operation from each memory cell is performed in a time-division manner within one sampling period, so that a plurality of delayed signals are provided for each sampling period. May be reproduced. In this case, since the reproduced signals correspond to the tap outputs of the transversal filter because the delay times are different, the transversal filter can be realized by adding the reproduced signals at an appropriate ratio. .
[0067]
{Circle around (4)} In the fourth and fifth embodiments described above, the output analog signal Vout is synthesized by the adder circuit 41. However, the output analog signal Vout may be synthesized by the sample-and-hold circuit.
[0068]
(5) In the first, second, and fourth embodiments described above, one end of each of the capacitors C1 to Cn is grounded, but it may be connected to a power supply. In short, what is necessary is just to connect to the line of a fixed voltage.
[0069]
{Circle around (6)} In the third and fifth embodiments described above, the memory cells M1 ′ to Mn ′ are composed of the capacitors C1 to Cn, the N-channel FETs N1 to Nn, etc., whose one ends are grounded. However, the present invention is not limited to this. One end of each of the capacitors C1 to Cn may be connected to a power supply, and a P-channel FET may be used instead of the N-channel FET. In the above-described fifth embodiment, the non-inversion voltage / current conversion unit 70 and the inversion voltage / current conversion unit 70 ′ may be configured as an integrated circuit as shown in FIG.
[0070]
【The invention's effect】
As described above, according to the present invention, data can be read from a memory cell without being affected by a parasitic capacitance, so that the quality of an output signal can be improved.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a delay circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing the operation of the delay circuit according to the embodiment.
FIG. 3 is a timing chart showing an operation of removing low-frequency noise according to the embodiment.
FIG. 4 is a timing chart showing an operation of removing low-frequency noise according to the embodiment.
FIG. 5 is a circuit diagram of a delay circuit according to a second embodiment of the present invention.
FIG. 6 is a timing chart showing the operation of the delay circuit according to the first embodiment.
FIG. 7 is a timing chart showing a read operation from a memory cell according to the first embodiment;
FIG. 8 is a circuit diagram of a delay circuit according to a third embodiment of the present invention.
FIG. 9 is a timing chart showing the operation of the delay circuit according to the same embodiment.
FIG. 10 is a circuit diagram of a delay circuit according to a fourth embodiment of the present invention.
FIG. 11 is a circuit diagram of a delay circuit according to a fifth embodiment of the present invention.
FIG. 12 is a circuit diagram of a forward current-to-voltage converter and a reverse current-to-voltage converter according to a modification.
FIG. 13 is a circuit diagram of a conventional delay circuit.
[Explanation of symbols]
10: inverting circuit (first inverting means, inverting means), 20: inverting circuit (second inverting means), 30: control circuit (writing means, reading means), 40: operational amplifier (negative feedback amplifying means, No. 1 negative feedback amplification means), 40 '... operational amplifier (second negative feedback amplification means), 41 ... addition circuit (synthesis means), 70 ... voltage / current conversion unit (voltage / current conversion means, forward voltage / current conversion means) , 80 ... current-voltage converter (current-voltage converter, inverted current-voltage converter), Vin ... input analog signal (input signal, input voltage signal), Vout ... output analog signal (output signal, output voltage signal), Ii ... Input current (input current signal), M1 to Mn, M1 'to Mn' ... memory cells, SW1 to SWn ... input switches (first switch means), SW1 'to SWn' ... output switches (second switch means) , SW1 ''-SW n '' ... switch (third switch means), SW0 ... switch (synthesis means, reset means, first reset means), SW0 '... switch (second reset means), C1 to Cn ... capacitors, Cs ... Capacitor (feedback capacitor).

Claims (2)

A delay circuit including a plurality of memory cells that store an analog signal by storing charge in a capacitor,
Voltage-current conversion means for converting an input voltage signal into a current to generate an input current signal;
Writing means for sequentially writing the input current signal to the plurality of memory cells;
Reading means for sequentially reading the input current signals stored from the plurality of memory cells according to a writing order;
A current-voltage converter for converting the input current signal read by the reading unit into a voltage to generate an output voltage signal; The memory cell includes first switch means connected at one end to an input terminal, second switch means provided between an output terminal and the other end of the first switch, and the first switch means Third switch means provided between the other end of the means and one end of the capacitor, a gate connected to one end of the capacitor, and the other end of the capacitor and the other end of the first switch means. 2. The analog signal delay circuit according to claim 1 , further comprising a field effect transistor having a source and a drain connected between the two.

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