JP3019089B1 - Correlated double sampling circuit - Google Patents

Abstract

An object of the present invention is to simplify a circuit configuration and achieve appropriate noise reduction only by specifying a pulse width on a side using a circuit. SOLUTION: Based on a selection signal input from the outside, one of pulses having a plurality of pulse widths generated by a clamp pulse generation circuit 12 and a sample hold pulse generation circuit 11 is selected, and a capacitance value is selected. A plurality of capacitors 41 to 43, 54 in the selection circuits 13, 14
Among the capacitors 56 to 56, capacitors that appropriately reduce noise for the pulse width selected by the selection signal are selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a correlated double sampling circuit used at various frequencies, and more particularly, to a correlated double sampling circuit capable of performing appropriate noise reduction by controlling a capacitor value. About.

[0002]

2. Description of the Related Art Conventionally, a correlated double sampling circuit (hereinafter referred to as a CDS circuit) has been used to reduce reset noise and amplifier noise contained in a CCD output signal, and is basically a clamp circuit. And a sample-and-hold circuit.

In general, a CDS circuit as described above is
The drive pulse width of the clamp circuit and the sample-and-hold circuit and the capacitance values of the clamp and hold capacitors constituting those circuits are designed to be correlated so that the effect of noise reduction is optimized.

In recent years, the number of pixels of a CCD has been diversified, and accordingly, the driving frequency and various pulse widths have been diversified. Therefore, it is inefficient to manufacture a CDS circuit for each of the diversified CCDs, and it is desired that one CDS circuit can handle various pulse widths.

In Japanese Patent Application Laid-Open No. 3-97382,
The hold capacitor of the sample-and-hold circuit is composed of a variable-voltage capacitor, and a signal that determines the bias voltage output from the bias control circuit is applied so that the capacitance value is suitable for the sample-and-hold pulse width. A noise reduction device that controls a capacitance value of a capacitance element is disclosed.

FIG. 2 is a diagram for explaining the operation of a general sampling circuit.

In the circuit shown in FIG. 2, a signal to be sampled is input to a terminal 101, and a sample and hold pulse is input to a terminal 103.

When a signal to be sampled is input to the terminal 101, the signal input to the terminal 101 is applied to the voltage variable capacitance element 106 during a period when the sample and hold pulse is input to the terminal 103 in the sample and hold circuit 105. The charge is accumulated and output to the terminal 102.

The voltage variable capacitance element 106 has a bias control circuit 107 in addition to the sample and hold circuit 105.
Are connected, and the capacitance value of the voltage variable capacitance element 106 is determined based on the difference between the signal potential to be sampled and the bias potential output from the bias control circuit 107.

A terminal 104 to which a signal for controlling a bias potential output from the bias control circuit 107 is input is connected to the bias control circuit 107. The signal input to the terminal 104 is a voltage An appropriate bias potential is applied to the bias control circuit 10 so that the variable capacitance element 106 has a capacitance value suitable for the sample hold pulse width.
7 is set to be output.

[0011]

However, in the conventional device described above, in order to control the capacitance of the voltage variable capacitance element, it is necessary to accurately grasp the pulse width of the applied pulse. There is a problem that a burden is imposed on the side using the circuit.

In addition, since the voltage variable capacitance element has a large temperature dependency, a control circuit for suppressing the temperature dependency is required, and there is a problem that the circuit becomes complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and simplifies a circuit configuration, so that an appropriate noise can be obtained simply by specifying a pulse width on a side where a circuit is used. It is an object of the present invention to provide a correlated double sampling circuit capable of achieving reduction.

[0014]

In order to achieve the above object, the present invention provides a clamp pulse generating means for generating a clamp pulse having a plurality of pulse widths based on an externally input clamp timing signal; Sample and hold pulse generation means for generating a sample and hold pulse having a plurality of pulse widths based on an input sample and hold timing signal, and using a clamp pulse generated by the clamp pulse generation means, A correlated double sampling circuit for clamping a feedthrough level of an input CCD output signal and sampling a signal level of the CCD output signal using a sample hold pulse generated by the sample hold pulse generation means; Clamp pulse generation means Selecting one of the clamp pulses having the plurality of pulse widths based on a first selection signal input from the outside, and outputting the selected one of the clamp pulses. Based on the selection signal, selects and outputs one of the sample and hold pulses having the plurality of pulse widths, and includes a plurality of capacitors connected in parallel with each other, based on the first selection signal. A first capacitance value selecting unit for selecting any one of the plurality of capacitors as a clamp capacitor for clamping the CCD output signal; and a plurality of capacitors connected in parallel to each other; Selecting one of the plurality of capacitors as a hold capacitor for holding the CCD output signal based on the selection signal of Characterized by comprising a capacitance value selecting means.

[0015] The clamp pulse generating means and the first capacitance value selecting means may determine a difference between a pulse width of the clamp pulse and a capacitance value of the clamp capacitor so as not to clamp a high frequency component of the CDD output signal. The sample and hold pulse generation means and the second capacitance value selection means simultaneously select a combination, and the pulse width of the sample and hold pulse and the capacitance of the hold capacitor are controlled so as to limit high frequency noise of the CDD output signal. It is characterized in that combinations with values are simultaneously selected.

The clamp pulse generating means may include a plurality of delay circuits, and generate the clamp pulse having the plurality of pulse widths by inputting the clamp timing signal to the plurality of delay circuits. Features.

The sample-and-hold pulse generating means includes a plurality of delay circuits, and generates the sample-and-hold pulse having the plurality of pulse widths by inputting the sample-and-hold timing signal to the plurality of delay circuits. It is characterized by doing.

Further, the first capacitance value selection means includes a plurality of switches respectively connected in series to the plurality of capacitors, and a connection state of the switches is controlled based on the first selection signal. Accordingly, one of the plurality of capacitors is selected as the clamp capacitor.

Further, the second capacitance value selecting means includes a plurality of switches connected in series to the plurality of capacitors, respectively, and a connection state of the switches is controlled based on the second selection signal. In this case, any one of the plurality of capacitors is selected as the hold capacitor.

(Operation) In the present invention configured as described above, based on the selection signal input from the outside, the present invention has a plurality of pulse widths generated by the clamp pulse generation means and the sample hold pulse generation means. One of the pulses is selected, and among the plurality of capacitors in the capacitance value selecting means, the capacitor that performs appropriate noise reduction for the pulse width selected by the selection signal is selected. , There is no need to set the capacitor value for the pulse width.

Further, since the capacitor for changing the capacitance value with respect to the pulse width can be switched by a switch, the circuit design becomes easy and the CDS which is stable against temperature fluctuations
Operation is realized.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a correlated double sampling circuit according to the present invention.

In this embodiment, as shown in FIG. 1, a terminal 1 to which a CCD output signal is input, a terminal 3 to which a sample hold timing signal is input, a terminal 4 to which a clamp timing signal is input, and a terminal 3 An input sample hold timing signal is input, a sample hold pulse generation circuit 11 that generates a sample hold pulse having a plurality of pulse widths based on the sample hold timing signal, and a clamp timing signal input to a terminal 4 are input. A clamp pulse generating circuit 12 for generating a clamp pulse having a plurality of pulse widths based on the clamp timing signal; and a plurality of capacitors 41 to 43 connected in parallel with each other. Select any one of the capacitors 41 to 43 based on the selection signal of A capacitance value selection circuit 13 serving as first capacitance value selection means for outputting a CCD output signal input to the terminal 1 via the capacitor; and an input terminal connected to the capacitance value selection circuit 13, And a plurality of capacitors 51 to 53 connected in parallel with each other, and a capacitor 51 based on a second selection signal input from outside.
To 53, and a capacitance value selection circuit 14 serving as second capacitance value selection means for grounding a signal output from the buffer 17 through the capacitor, and a sample hold pulse generation circuit 11. One of the generated sample-and-hold pulses having a plurality of pulse widths is selected, and the capacitors 51 to 51 in the capacitance value selection circuit 14 are selected.
53, terminals 5 to 7 to which a selection signal for selecting one is input, and one of the clamp pulses having a plurality of pulse widths generated by the clamp pulse generation circuit 12 are selected, and the capacitance is selected. Terminals 8 to 10 to which a selection signal for selecting one of capacitors 41 to 43 in value selection circuit 13 are input, and a potential for clamping a signal output from capacitance value selection circuit 13 are generated. A voltage source 18, a switch 15 for controlling supply of a potential generated by the voltage source 18 to the capacitance value selection circuit 13 based on a clamp pulse output from the clamp pulse generation circuit 12, A switch for controlling the input of the signal output from the buffer 17 to the capacitance value selection circuit 14 based on the output sample hold pulse. And 16, is connected to the capacitance value selection circuit 14 is input to the terminal 1 is the sample hold CC
And a terminal 2 to which a D output signal is output.

The sample and hold pulse generation circuit 1
Reference numeral 1 denotes a NOT gate 21 to which a sample hold timing signal input to a terminal 3 is input, inverts the sample hold timing signal and outputs the inverted signal, and outputs a signal output from the NOT gate 21 by delaying the signal by a predetermined time. And a delay circuit 23 that delays a signal output from the delay circuit 22 by a predetermined time and outputs the delayed signal.
A delay circuit 24 for delaying the signal output from the delay circuit 23 by a predetermined time and outputting the delayed signal; a sample and hold timing signal input to the terminal 3 to a first input terminal; Any one of the signals output from the delay circuits 22 to 24 is input, an OR operation is performed on the input signals, and an AND result is output as a sample and hold pulse for controlling the operation of the switch 16 A switch 25 for controlling the input of the signal output from the delay circuit 22 to the AND gate 28 based on the selection signal input to the terminal 7;
And a switch 26 for controlling the input of the signal output from the delay circuit 23 to the AND gate 28 based on the selection signal input to the AND gate 28, and the output from the delay circuit 24 based on the selection signal input to the terminal 5. And a switch 25 for controlling the input of the signal to the AND gate 28.

The capacitance selection circuit 14 is output from the buffer 17 based on a plurality of capacitors 51 to 53, one ends of which are grounded, and the selection signal input to the terminal 7, and is input via the switch 16. A switch 54 for controlling the application of the output signal to the capacitor 51, and a control for applying the signal output from the buffer 17 and input through the switch 16 to the capacitor 52 based on the selection signal input to the terminal 6. And a switch 56 that controls the application of the signal output from the buffer 17 and input through the switch 16 to the capacitor 53 based on the selection signal input to the terminal 5.

The clamp pulse generation circuit 12 receives the clamp timing signal input to the terminal 4 and
NOT for inverting and outputting the clamp timing signal
A gate 31, a delay circuit 32 that delays and outputs a signal output from the NOT gate 31 by a predetermined time, a delay circuit 33 that delays and outputs a signal output from the delay circuit 32 by a predetermined time, A delay circuit 34 for delaying the signal output from the delay circuit 33 by a predetermined time and outputting the same, a clamp timing signal input to the terminal 4 to a first input terminal, and a delay circuit to a second input terminal An AND gate 38 to which any one of the signals output from 32 to 34 is input, calculates the logical sum of the input signals, and outputs the operation result as a clamp pulse for controlling the operation of the switch 15; 8 of the signal output from the delay circuit 32 based on the selection signal input to
Switch 35 for controlling input to ND gate 38
And a switch 36 for controlling the input of the signal output from the delay circuit 33 to the AND gate 38 based on the selection signal input to the terminal 9, and the delay circuit 34 based on the selection signal input to the terminal 10. Switch 35 for controlling the input of the signal output from the AND gate 38 to the AND gate 38
It is composed of

Further, the capacitance selection circuit 13 inputs the CCD output signal input to the terminal 1 to a plurality of capacitors 41 to 43, respectively, and the selection signal input to the terminal 8 based on the selection signal input to the terminal 8. A switch 44 for controlling the input of the signal output from the capacitor 41 to the buffer 17, and a signal input to the terminal 1 based on the selection signal input to the terminal 9 and output via the capacitor 42. A switch 45 for controlling the input to the buffer 17 of the
A switch 45 controls the input of the signal input to the terminal 1 and output via the capacitor 43 to the buffer 17 based on the selection signal input to the terminal 10.

The operation of the correlated double sampling circuit configured as described above will be described below.

First, the operation of the clamp pulse generation circuit 12 will be described.

A terminal 4 receives a clamp timing signal having a rising edge during a feedthrough period of the CCD output signal, and terminals 8 to 10 receive a selection signal for determining a clamp pulse width.

The clamp timing signal input to the terminal 4 is input to the first input terminal of the AND gate 38 and the NOT gate 31, and is inverted and output from the NOT gate 31.

The signal output from the NOT gate 31 is
The signals are sequentially input to the delay circuits 32 to 34, and are delayed by a predetermined amount and output.

The signal output from the delay circuit 32 is input to the delay circuit 33 and applied to one end of the switch 35.

The signal output from the delay circuit 33 is input to the delay circuit 34 and the switch 36
Is added to one end.

The signal output from the delay circuit 34 is applied to one end of a switch 37.

Here, in the switches 35 to 37,
The operation is controlled based on a selection signal input to terminals 8 to 10.

When a selection signal is input to the terminal 8, the switch 35 is turned on and the switches 36 and 37 are turned off, whereby the signal output from the delay circuit 32, that is, the delay time in the delay circuit 32, The signal delayed by only this time is input to the second input terminal of the AND gate 38.

When a selection signal is input to the terminal 9,
The switch 36 is in the connected state, and the switches 35 and 37 are each in the open state. As a result, the signal output from the delay circuit 33, that is, the delay time in the delay circuit 32 and the delay time in the delay circuit 33 are delayed by a time. The signal is input to a second input terminal of the AND gate 38.

When a selection signal is input to the terminal 10, the switch 37 is connected and the switches 35 and 36 are open, whereby the signal output from the delay circuit 34, that is, The signal delayed by the sum of the delay time, the delay time in the delay circuit 33, and the delay time in the delay circuit 34 is AN
The signal is input to the second input terminal of the D gate 38.

As a result, the H level of the clamp timing signal input to the terminal 4 is maintained longer by the delay time selected by the switches 35 to 37, and the AND gate 38 controls the delay selected by the switches 35 to 37. A signal having a pulse width of time is generated and output as a clamp pulse.

The clamp pulse output from the clamp pulse generation circuit 12 is applied to the switch 15.

The switch 15 is connected when the clamp pulse output from the clamp pulse generation circuit 12 is applied, and is open when the clamp pulse is not applied.

When the switch 15 is connected, a potential for clamping the signal output from the capacitance value selection circuit 13 is supplied from the voltage source 18 to the output side of the capacitance value selection circuit 13.

Next, the operation of the capacitance value selection circuit 13 will be described.

The CCD output signal input to the terminal 1 is applied to each of the capacitors 41 to 43.

Here, in the switches 44 to 46,
The operation is controlled based on a selection signal input to terminals 8 to 10.

When a selection signal is input to the terminal 8, the switch 44 is connected and the switches 45 and 46 are open, whereby the capacitor 41 is selected as a clamp capacitor, and the switch 4 of the capacitor 41 is selected.
The signal appearing on the fourth side is output from the capacitance value selection circuit 13.

When a selection signal is input to the terminal 9,
The switch 45 is in the connected state, and the switches 44 and 46 are each in the open state, whereby the capacitor 42 is selected as a clamp capacitor, and a signal appearing on the switch 45 side of the capacitor 42 is output from the capacitance value selection circuit 13.

When a selection signal is input to the terminal 10, the switch 46 is connected and the switches 44 and 45 are opened, whereby the capacitor 43 is selected as a clamp capacitor, and the capacitor 43 is connected to the switch 46 side. Are output from the capacitance value selection circuit 13.

By the above-described operation, the switch 15 is connected for a period corresponding to the pulse width selected by the selection signal from the rising edge of the clamp timing signal having the rising edge in the feedthrough period of the CCD output signal, and the capacitance is set. The signal output from the value selection circuit 13 is clamped to the potential supplied by the voltage source 18 with respect to the ground level during the feedthrough period of the CCD output signal.

The clamp characteristics of the signal output from the capacitance value selection circuit 13 are determined by the clamp pulse width and the clamp capacitor value.

For a selected clamp pulse width, CD
A clamp capacitor having a capacitance value showing a clamp characteristic such that noise reduction of the S circuit is optimized is prepared in advance,
The capacitance value selection circuit 13 is designed so that a clamp capacitor corresponding to the selected clamp pulse width is selected.

Thus, the clamp operation for performing the optimal CDS operation can be performed only by selecting the clamp pulse width according to the driving of the CCD.

After that, the signal output from the capacitance value selection circuit 13 and clamped is input to the buffer 17.

Next, the sample and hold pulse generation circuit 1
1 will be described.

A terminal 3 receives a sample hold timing signal having a rising edge during the signal period of the CCD output signal, and terminals 5 to 7 receive a selection signal for determining a sample hold pulse width.

The sample hold timing signal input to the terminal 3 is connected to the first input terminal of the AND gate 28 and N
The signal is input to the OT gate 21 and inverted by the NOT gate 21 to be output.

The signal output from the NOT gate 21 is
The signals are sequentially input to the delay circuits 22 to 24, and each of them is output after being delayed by a predetermined amount.

The signal output from the delay circuit 22 is input to the delay circuit 23 and applied to one end of the switch 25.

The signal output from the delay circuit 23 is input to the delay circuit 24 and the switch 26
Is added to one end.

The signal output from the delay circuit 24 is applied to one end of a switch 27.

Here, in the switches 25 to 27,
The operation is controlled based on the selection signals input to the terminals 5 to 7.

When a selection signal is input to the terminal 7, the switch 25 is turned on and the switches 26 and 27 are turned off, whereby the signal output from the delay circuit 22, that is, the delay time in the delay circuit 22, The signal delayed by only this time is input to the second input terminal of the AND gate 28.

When a selection signal is input to the terminal 6,
The switch 26 is in the connected state, and the switches 25 and 27 are in the open state, respectively, whereby the signal output from the delay circuit 23, that is, the delay time of the delay circuit 22 and the delay time of the delay circuit 23 are delayed. The signal is input to a second input terminal of the AND gate 28.

When a selection signal is input to the terminal 5,
The switch 27 is in the connection state, and the switches 25 and 26 are in the open state, respectively, whereby the signals output from the delay circuit 24, that is, the delay time in the delay circuit 22, the delay time in the delay circuit 23, and the delay time in the delay circuit 24 Is input to the second input terminal of the AND gate 28.

Thus, the H level of the sample hold timing signal input to the terminal 3 is
27, held longer by the delay time selected by 27;
In the AND gate 28, a signal having a pulse width of the delay time selected by the switches 25 to 27 is generated,
It is output as a sample and hold pulse.

The sample and hold pulse output from the sample and hold pulse generation circuit 11 is applied to the switch 16.

The switch 16 is connected when the sample and hold pulse output from the sample and hold pulse generation circuit 11 is applied, and is opened when no sample and hold pulse is applied.

When the switch 16 is connected, the signal output from the capacitance value selection circuit 13 and the signal amplified by the buffer 17 are input to the capacitance value selection circuit 14.

Next, the operation of the capacitance value selection circuit 14 will be described.

The output from the buffer 17 and the switch 16
Is input to one end of each of the switches 54 to 56.

Here, in the switches 54 to 56,
The operation is controlled based on the selection signals input to the terminals 5 to 7.

When a selection signal is input to the terminal 7, the switch 54 is connected and the switches 55 and 56 are open respectively, whereby the capacitor 51 connected to the other end of the switch 54 is selected as a hold capacitor. , A signal appearing on the switch 54 side of the capacitor 51 is output to the terminal 2.

When a selection signal is input to the terminal 6,
The switch 55 is in the connected state, and the switches 54 and 56 are in the open state, whereby the capacitor 52 connected to the other end of the switch 55 is selected as the hold capacitor, and the signal appearing on the switch 55 side of the capacitor 52 is connected to the terminal 2. Is output.

When a selection signal is input to the terminal 5,
The switch 56 is in the connected state, and the switches 54 and 55 are in the open state, whereby the capacitor 53 connected to the other end of the switch 56 is selected as the hold capacitor, and a signal appearing on the switch 56 side of the capacitor 53 is supplied to the terminal 2. Is output.

By the above-described operation, the switch 16 is in the connected state for a period corresponding to the pulse width selected by the selection signal from the rising edge of the sample hold timing signal having the rising edge in the signal period of the CCD output signal, and the capacitance is set. The output terminal of the value selection circuit 14 has a CCD
During the signal period of the output signal, the feedthrough period and the signal period C
The CDS operation is realized by sampling the potential difference of the CD output.

The sampling characteristics of the output of the capacitance value selection circuit 14 are determined by the sample / hold pulse width and the hold capacitor value.

A hold capacitor having a capacitance value exhibiting a sampling characteristic such that the noise reduction of the CDS circuit is optimized with respect to the selected sample hold pulse width is prepared in advance. The capacitance value selection circuit 14 is designed so that the hold capacitor corresponding to the pulse width is selected.

As a result, the optimum CDS can be obtained simply by selecting the sample hold pulse width according to the driving of the CCD.
Sample-hold operation for performing the above operation can be performed.

Therefore, on the side using the circuit, C
By inputting a clamp timing signal and a sample hold timing signal having a rising edge at an appropriate timing with respect to the CD output signal and digitally setting a clamp pulse width and a sample hold pulse width suitable for the CCD drive frequency, The best CD for noise reduction
The operation of S can be easily obtained.

The present invention is not limited to the above embodiment, and various modifications can be made by those skilled in the art without departing from the scope of the present invention.

[0083]

Since the present invention is constructed as described above, it has the following effects.

(1) Proper noise reduction can be performed only by inputting a selection signal for selecting a pulse width in accordance with the CCD drive frequency.

(2) Since the configuration is such that a capacitor having a capacitance value suitable for the pulse width is switched by a switch, circuit design is facilitated.

(3) Since a voltage variable capacitance element is not used, stable CDS operation can be realized with respect to temperature fluctuation.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a correlated double sampling circuit of the present invention.

FIG. 2 is a diagram for explaining an operation of a general sampling circuit.

[Explanation of symbols]

1 to 10 terminal 11 sample and hold pulse generation circuit 12 clamp pulse generation circuit 13, 14 capacitance value selection circuit 15, 16, 25 to 27, 35 to 37, 44 to 46, 5
4 to 56 switch 17 buffer 18 voltage source 21, 31 NOT gate 22 to 24, 32 to 34 delay circuit 28, 38 AND gate 41 to 43, 51 to 53 capacitor

Claims (6)

(57) [Claims] 1. A clamp pulse generating means for generating a clamp pulse having a plurality of pulse widths based on an externally input clamp timing signal, and a plurality of pulse widths based on an externally input sample hold timing signal. Sample and hold pulse generating means for generating a sample and hold pulse having the clamp pulse generated by the clamp pulse generating means, and clamping a feedthrough level of a CCD output signal input from the outside, In a correlated double sampling circuit for sampling a signal level of the CCD output signal using a sample and hold pulse generated by the sample and hold pulse generation unit, the clamp pulse generation unit includes a first selection input from outside. Based on the signal Selecting and outputting one of the clamp pulses having the plurality of pulse widths, wherein the sample-and-hold pulse generating means outputs a sample having the plurality of pulse widths based on a second selection signal input from outside One of the hold pulses is selected and output, and a plurality of capacitors connected in parallel to each other are provided. Based on the first selection signal, one of the plurality of capacitors is output to the CCD output signal. Capacitance value selecting means for selecting a capacitor as a clamp capacitor for clamping voltage, and a plurality of capacitors connected in parallel with each other, and any one of the plurality of capacitors is selected based on the second selection signal. And a second capacitance value selecting means for selecting as a hold capacitor for holding the CCD output signal. Double sampling circuit. 2. The correlated double sampling circuit according to claim 1, wherein the clamp pulse generation unit and the first capacitance value selection unit are configured to clamp the high-frequency component of the CDD output signal without clamping the high-frequency component. A combination of a pulse width of a pulse and a capacitance value of the clamp capacitor is simultaneously selected, and the sample-and-hold pulse generation unit and the second capacitance value selection unit limit high-frequency noise of the CDD output signal. A correlated double sampling circuit, wherein a combination of a pulse width of the sample hold pulse and a capacitance value of the hold capacitor is simultaneously selected. 3. The correlation 2 according to claim 1 or claim 2.
In the multiple sampling circuit, the clamp pulse generation unit may include a plurality of delay circuits, and generate the clamp pulse having the plurality of pulse widths by inputting the clamp timing signal to the plurality of delay circuits. Features a correlated double sampling circuit. 4. The correlated double sampling circuit according to claim 1, wherein said sample-and-hold pulse generation means includes a plurality of delay circuits, and outputs said sample-and-hold timing signal to said plurality of sample-and-hold timing signals. A correlated double sampling circuit, wherein a sample hold pulse having the plurality of pulse widths is generated by inputting the sample hold pulse to a delay circuit. 5. The correlated double sampling circuit according to claim 1, wherein said first capacitance value selecting means includes a plurality of switches respectively connected in series to said plurality of capacitors. A correlation double sampling circuit comprising: selecting one of the plurality of capacitors as the clamp capacitor by controlling a connection state of the switch based on the first selection signal. . 6. The correlated double sampling circuit according to claim 1, wherein said second capacitance value selecting means includes a plurality of switches respectively connected in series to said plurality of capacitors. A correlation double sampling circuit comprising: selecting one of the plurality of capacitors as the hold capacitor by controlling a connection state of the switch based on the second selection signal. .