JPH0832877A - Solid-state image pickup device and driving method for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the image quality due to the insufficient transfer of a signal charge from the charge transfer section of a solid-state image pickup element. CONSTITUTION:The device is provided with a clock generator 20 generating pulses H1, H2 for a horizontal scanning period in which horizontal drive pulses phiH1, phiH2 are in existence, correction waveform generating circuits 70, 71 generating correction pulses H1DC, H2DC to cancel low frequency components H1L, H2L of the outputs H1, H2 from the clock generator 20 and horizontal drive circuits 30,40 to generate the horizontal drive pulses phiH1, phiH2 given to a horizontal transfer register 10 of the solid-state image pickup element based on the output from the clock generator 20 and the output from the correction waveform generating circuits 70, 71. Thus, the horizontal drive circuits 30, 40 generate the horizontal drive pulses phiH1, phiH2 in which the decrease in a 1st pulse amplitude for the horizontal scanning period is suppressed as required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a method for driving a solid-state image pickup element used in, for example, a video camera.

[0002]

2. Description of the Related Art Generally, in a solid-state image pickup device used in a video camera or the like, the signal charge of each imaged pixel is sequentially transferred in the vertical direction at the timing of horizontal scanning, and is provided at the end thereof. After being transferred to the horizontal transfer register, it is transferred at a high speed in the horizontal direction at the timing of the pixel clock and taken out as a video signal to the outside. A drive pulse of a two-phase clock is generally used to drive the horizontal transfer register in this type of solid-state image sensor. Note that the driving method of the solid-state imaging device using such a driving pulse is described in, for example, CCD camera technology (first edition issue date: November 3, 1986, issue office: Radio Technology Co., Ltd., author: Hiroo Takemura). It is well known as described on pages 23 to 27, 46 to 61.

Here, a conventional example will be described with reference to FIGS. 13 is a circuit block diagram of the solid-state imaging device, FIG. 14 is a configuration diagram of the horizontal drive circuit of FIG. 13, and FIG.
[Fig. 3] is a signal waveform diagram. In the figure, 10 is a horizontal transfer register of a solid-state image sensor, 20 is a clock generator that generates clock pulses H1 and H2 of a required cycle and a required amplitude in a logic circuit, and 30 and 40 are based on outputs H1 and H2 from the clock generator 20. Drive pulses φH1, φ for driving the horizontal transfer register 10 of the solid-state image sensor
It is a horizontal drive circuit that generates H2.

The horizontal drive circuits 30 and 40 include input coupling capacitors C1 and C2, resistors C1 and R2 for potential clamping, and current amplifying transistors Q1 and Q2.
It has power supply voltages Vcc and Vss. The operation of the horizontal drive circuits 30 and 40 is such that the DC component of the signals H1 and H2 having the waveforms as shown in FIG.
1 and C2, and after clamping to the voltage Vcc or Vss with the resistors R1 and R2, they are input to the base terminals of the transistors Q1 and Q2 and converted into an output determined by the voltages Vcc and Vss by the switching operation of the transistors Q1 and Q2. As a result, horizontal drive pulses φH1 and φH2 having waveforms as shown in FIG. 15B are generated.

The horizontal drive pulses φH1 and φH2 are used for a horizontal scanning period 81 for outputting a signal from the horizontal transfer register 10 of the solid-state image sensor and a horizontal blanking period for stopping the signal output from the horizontal transfer register 10 of the solid-state image sensor. 82 is continuous in a required cycle, and inversion is simultaneously started (started) at the beginning of the horizontal scanning period 81, and fixed (stopped) to a high potential and a low potential in the horizontal blanking period 82, respectively. Has been done. Further, the horizontal drive pulses φH1 and φH2 have low frequency components φH1L and φH2L having waveforms as shown in FIG. 15C, which have a horizontal scanning period 81 and a horizontal blanking period 82 as a cycle. The low-frequency components φH1L and φH2L are conceptually shown, and the potential relations thereof are changed to opposite phases.

[0006]

By the way, the above-mentioned conventional example has the following problems.

That is, the outputs H1 and H2 from the clock generator 20 are horizontal drive circuits 30 and 40, respectively.
Is input to the coupling capacitors C1 and C
2 and the resistors R1 and R2 for clamping, the high-frequency passage circuit distorts the waveform and causes distortion. Therefore, the low frequency components H1L and H2L of the outputs H1 and H2 from the clock generator 20 are also distorted as shown in FIG. Then, the low frequency components H1L and H2L
Is superimposed on the beginning of the horizontal scanning period 81, the signals H1b and H2b having waveforms as shown in FIG. 16B are given to the bases of the transistors Q1 and Q2. Thus, the base input signal H1 of the transistors Q1 and Q2 is
When the pulse amplitude h at the start of the horizontal scanning period 81 in b and H2b decreases, the transistors Q1 and Q2 cannot be turned on sufficiently, and particularly the frequency characteristics of the current supply capability of the transistors Q1 and Q2 of the horizontal drive circuits 30 and 40. 16C is insufficient, the pulse amplitude h of the horizontal drive pulses φH1 and φH2 decreases more than necessary at the beginning of the horizontal scanning period 81 as shown in FIG. 16C. Such horizontal drive pulses φH1 and φH2 induce charge transfer failure in the horizontal transfer register 10 of the solid-state image sensor, and thus vertical line noise is generated, resulting in a significant deterioration in image quality.

In addition, when the driving frequency of the horizontal transfer register 10 is set to be high with the increase in the number of pixels of the solid-state image pickup device, the width of the horizontal driving pulses φH1 and φH2 becomes narrow and the transient response of the pulse becomes a problem. That is, since the horizontal transfer register 10 of the solid-state image pickup device is a capacitive load, the horizontal drive pulse φH1, which is applied from the horizontal drive circuits 30 and 40, is generated.
The waveform of φH2 is distorted and distortion occurs. for that reason,
Low frequency components φH1L of horizontal drive pulses φH1 and φH2,
.phi.H2L is similarly distorted as shown in FIG. Especially, when the driving frequency becomes high, this low frequency component φH1
The distortion of L and φH2L cannot be ignored. That is, distortion of the low frequency components φH1L and φH2L is
Since it is superposed on the start pulse of
If the frequency characteristics of the current supply capability of the 0 transistors Q1 and Q2 are not sufficient, horizontal drive pulses φH1 and φH
As shown in FIG. 17B, 2 has a waveform in which the pulse amplitude h decreases more than necessary at the beginning of the horizontal scanning period 81. Such horizontal drive pulses φH1 and φH2 induce charge transfer failure in the horizontal transfer register 10 of the solid-state image sensor, and thus vertical line noise is generated, resulting in a significant deterioration in image quality.

Therefore, it is an object of the present invention to prevent image quality deterioration due to defective transfer of signal charges from the charge transfer section of a solid-state image pickup device.

[0010]

A first solid-state image pickup device according to the present invention comprises a clock pulse generation circuit for generating a clock pulse which defines a drive timing of a charge transfer section of a solid-state image pickup device, and a clock pulse generation circuit. A correction waveform generation circuit that generates a correction pulse that cancels the low-frequency component of the output, and the output from the correction waveform generation circuit and the output from the clock pulse generation circuit are mixed and stored in the image pickup unit of the solid-state image pickup device. And a drive circuit for generating a drive pulse in which a transfer period for transferring the signal charge and a stop period for fixing the potential are continuous in a required cycle, and driving the charge transfer unit of the solid-state image sensor by the drive pulse. .

The drive circuit includes a transistor, a coupling capacitor connected to the base of the transistor, and a clamp resistor, and the correction pulse is mixed with the low frequency component at the base of the transistor.

A second solid-state image pickup device according to the present invention uses a clock pulse generation circuit for generating a clock pulse for defining a drive timing of a charge transfer section of a solid-state image pickup element and a low-frequency component of an output from the clock pulse generation circuit. A high-frequency cutoff circuit that cuts off the included high-frequency components, and a transfer period for transferring the signal charge accumulated in the image pickup unit of the solid-state image pickup device based on the output from the high-frequency cutoff circuit and a stop period for stopping the transfer. And a drive circuit for generating a drive pulse in which a continuous cycle is generated at a required period, and driving the charge transfer unit of the solid-state image sensor by the drive pulse.

The drive circuit includes a coupling capacitor and a clamp resistor connected to the base of a transistor that outputs a drive pulse. In the third solid-state imaging device of the present invention, wherein the high-frequency cutoff circuit is composed of a low-pass filter including a resistor and a capacitor, a clock pulse that generates a clock pulse that defines the drive timing of the charge transfer unit of the solid-state imaging device. Based on the output from the generation circuit and the clock pulse generation circuit, a drive pulse in which a transfer period for transferring the signal charge accumulated in the image pickup unit of the solid-state image pickup device and a stop period in which the potential is fixed are connected in a required cycle. A drive circuit for generating and driving the charge transfer section of the solid-state image pickup device by the drive pulse, wherein the drive circuit sets the amplitude of a pulse of at least one cycle at the beginning of the transfer period of the drive pulse to be larger than a predetermined amplitude. The setting means for setting is provided.

A fourth solid-state image pickup device according to the present invention is based on a clock pulse generation circuit for generating a clock pulse which defines a drive timing of a charge transfer section of a solid-state image pickup element, and an output from the clock pulse generation circuit. A drive pulse in which a transfer period for transferring the signal charge accumulated in the image pickup unit of the image pickup device and a stop period in which the potential is fixed are continuous in a required cycle is generated, and the drive pulse drives the charge transfer unit of the solid-state image pickup device. And a drive circuit for
There is provided setting means for setting the pulse width of the pulse of at least one cycle of the start end of the transfer period to be wider than a predetermined pulse width.

According to a first method of driving a solid-state image pickup device of the present invention, a solid-state image pickup device for transferring signal charges accumulated by irradiation of light to the image pickup unit from the charge transfer unit to the outside is provided in the image pickup unit of the solid-state image pickup device. Driving in which a transfer period for transferring the accumulated signal charges and a stop period for stopping the transfer are continuous in a required cycle, and the pulse amplitude of at least one cycle at the beginning of the transfer period is set to be larger than a predetermined amplitude Drive with pulse.

According to a second method for driving a solid-state image pickup device of the present invention, a solid-state image pickup device for transferring signal charges accumulated by irradiation of light to the image pickup unit from the charge transfer unit to the outside is provided in the image pickup unit of the solid-state image pickup device. A transfer period for transferring the accumulated signal charges and a stop period for stopping the transfer are connected in a required cycle, and a pulse width of a pulse at least at one end of the transfer period is set to be wider than a predetermined pulse width. It drives with the drive pulse.

[0017]

The first and second solid-state image pickup devices are devised so that the pulse amplitude at the beginning of the transfer period in the generated drive pulse can be suppressed from being reduced more than necessary.

In the third solid-state image pickup device and the first solid-state image pickup element driving method, the waveform of the drive pulse applied to the solid-state image pickup element is prevented from being distorted due to the charge transfer portion which is the capacitive load of the solid-state image pickup element. However, it is devised so that the distortion of the waveform of the low frequency component of the drive pulse can be canceled.

In the fourth solid-state image pickup device and the second solid-state image pickup device driving method, the waveform of the drive pulse applied to the solid-state image pickup device is prevented from being distorted due to the charge transfer portion which is the capacitive load of the solid-state image pickup device. However, it is devised so that the distortion of the waveform of the low frequency component of the drive pulse does not affect the pulse at the beginning of the transfer period in the drive pulse.

That is, according to the third and fourth solid-state image pickup devices and the first and second solid-state image pickup device driving methods, the pulse amplitude at the start of the transfer period in the driving pulse is maintained at a magnitude higher than required. Become so. This is particularly effective when the drive frequency of the charge transfer section is set high as the number of pixels of the solid-state image sensor increases.

According to the present invention as described above, the signal charges can be stably and reliably transferred from the charge transfer section of the solid-state image pickup device to the outside.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the first to fourth embodiments shown in FIGS.

1 to 3 show claims 1 and 2 of the present invention.
1 is a circuit block diagram of a solid-state image pickup device, FIG. 2 is a configuration diagram of the horizontal drive circuit of FIG. 1, and FIG. 3 is a signal waveform diagram. In these figures, parts corresponding to those in the conventional example are designated by the same reference numerals. In the figure, 10 is a horizontal transfer register of the solid-state image sensor, 20 is a clock generator (clock pulse generation circuit) for generating clock pulses H1 and H2 of a required cycle and a required amplitude in a logic circuit, and 30 and 40 are clock generator 20 clock signals. It is a horizontal drive circuit (drive circuit) that generates horizontal drive pulses φH1 and φH2 for driving the horizontal transfer register 10 (charge transfer unit) of the solid-state imaging device based on the outputs H1 and H2.

The configuration of the first embodiment different from that of the conventional example is that correction waveform generating circuits 70 and 71 are newly provided and that the clock generator 20 has a new function.

The clock generator 20 supplies signals H1 and H2 having the waveforms shown in FIG. 3A to the horizontal drive circuits 30 and 40, and as shown in FIG. 3B supplied to the correction waveform generation circuits 70 and 71. Waveform signals H1La and H2La
(The same as H1L and H2L) are generated. The signals H1La and H2La supplied to the correction waveform generation circuits 70 and 71 are waveforms in which the potentials are inverted at the same timing as the low frequency components H1L and H2L of the signals H1 and H2 supplied to the horizontal drive circuits 30 and 40.

The correction waveform generating circuits 70 and 71 are respectively provided with input coupling capacitors C4 and C5, potential clamping resistors R4 and R5, and inverting amplifiers A1 and A2. Capacitors C4 and C5 and resistance R
4, 4 and R5 form a high frequency passage circuit, and the output terminals of the inverting amplifiers A1 and A2 are connected to the bases of the transistors Q1 and Q2 of the horizontal drive circuits 30 and 40. The correction waveform generation circuits 70 and 71 respectively output the signals H1La and H2La having the waveforms as shown in FIG.
4, C5, R4, R5), waveforms H1Lb, H2Lb as shown in FIG.
After inversion by and the amplitude is adjusted, correction pulses H1DC and H2DC having waveforms as shown in FIG.

The operation will be described. Clock generator 2
A signal H having a waveform as shown in FIG.
Although the low frequency components H1L and H2L of H1 and H2 have waveforms as shown in FIG. 3C due to the high frequency pass circuits of the horizontal drive circuits 30 and 40, correction waveform generation circuits 70 and 71 are provided.
The correction pulses H1DC and H2DC having a waveform as shown in FIG. 3 (d) output from each of the horizontal drive circuits 30 and 40 are mixed with the bases of the transistors Q1 and Q2, respectively, so that the low frequency component H1L is mixed. , H2L will be canceled. Therefore, the horizontal drive circuits 30, 40
At the bases of the transistors Q1 and Q2, signals H1b and H2b having waveforms as shown in FIG. 3 (e) having an amplitude h larger than required to ensure the switching operation of the transistors Q1 and Q2 are provided. Will be given.
Therefore, the horizontal drive pulses φH1 and φH2 output from the horizontal drive circuits 30 and 40 have a waveform in which the pulse amplitude h at the start end of the horizontal scanning period 81 hardly decreases as shown in FIG.

As described above, in the first embodiment, the horizontal drive pulse φH1, which has almost no decrease in the pulse amplitude h from the horizontal drive circuits 30 and 40 at the beginning of the horizontal scanning period 81.
Since φH2 can be generated and output, the signal charge can be stably and reliably transferred to the outside from the horizontal transfer register 10 of the solid-state image sensor, and as a result, deterioration of image quality such as vertical streak noise can be prevented.

4 to 6 show the third and third aspects of the present invention.
4 is a circuit block diagram of a solid-state image pickup device, FIG. 5 is a configuration diagram of the horizontal drive circuit of FIG. 4, and FIG. 6 is a signal waveform diagram. In these figures, parts corresponding to those in the conventional example are designated by the same reference numerals. In the figure, 10 is a horizontal transfer register of the solid-state image sensor, 2
Reference numeral 0 is a clock generator, and 30 and 40 are horizontal drive circuits.

The second embodiment differs from the prior art in that the clock generator 20 and the horizontal drive circuits 30 and 4 are used.
That is, the high frequency cutoff circuits 50 and 60 are provided between the high frequency cutoff circuit and the high frequency cutoff circuit. The high frequency cutoff circuits 50 and 60 are configured by a low pass filter including a resistor R3 and a capacitor C3, and cut off high frequency components included in the low frequency components of the output from the clock generator 20.

The operation will be described. Clock generator 2
Signal H having a waveform as shown in FIG.
1 and H2 are input to the horizontal drive circuits 30 and 40 via the high frequency cutoff circuits 50 and 60, the signals H1 and H2
Low frequency components H1L and H2L of high frequency cutoff circuits 50 and 6
From the waveform as shown in FIG.
The waveform becomes as shown in (c), and the amount of change is suppressed. Therefore, the bases of the transistors Q1 and Q2 are
Signals H1b and H2b having waveforms as shown in FIG. 6 (d) having an amplitude larger than required to ensure the switching operation of the transistors Q1 and Q2 are provided. Therefore, the horizontal drive pulses φH1 and φH2, which are the outputs of the horizontal drive circuits 30 and 40, are waveforms in which the unnecessary reduction of the pulse amplitude h at the beginning of the horizontal transfer period 81 is suppressed as shown in FIG. Becomes

As described above, in the second embodiment, the horizontal drive circuits φH1 and φH2 can be generated and output from the horizontal drive circuits 30 and 40 in which the decrease of the pulse amplitude h at the start of the horizontal scanning period 81 is suppressed. The signal charges can be stably and reliably transferred to the outside from the horizontal transfer register 10 of the element, and as a result, the deterioration of the image quality such as vertical stripe noise can be prevented.

In the second embodiment, the high-frequency cutoff circuits 50 and 60 are constructed so that a resistor R3 and a capacitor C are provided.
Although the first-order low-pass filter constituted by 3 and 3 is used, the circuit configuration is arbitrary as long as it cuts off high frequency.

7 to 9 show claims 6 and 7 of the present invention.
7 is a circuit block diagram of a solid-state imaging device, FIG. 8 is a configuration diagram of the horizontal drive circuit of FIG. 7, and FIG. 9 is a signal waveform diagram. In these figures, parts corresponding to those in the conventional example are designated by the same reference numerals.

In the third embodiment, the configuration different from the conventional example is that the horizontal drive circuits 30 and 40 are driven by the horizontal drive pulse φH according to the signals inputted to the control terminals 31 and 41.
That is, the amplitude h of 1 and φH2 is made variable. In particular, only the first pulse amplitude h of the horizontal drive pulses φH1 and φH2 in the horizontal scanning period 81 is set to be larger than a predetermined amplitude value. For example, the first pulse amplitude of the horizontal scanning period 81 is the low frequency component φH1 caused by the horizontal transfer register 10 which is the capacitive load of the solid-state image sensor.
The level is set to a level higher than that for canceling the distortion of the L and φH2L waveforms.

More specifically, the horizontal drive circuits 30 and 40 include the input coupling capacitors C1 and C2, the potential clamp resistors R1 and R2, and the current amplification transistor Q.
1, Q2, power supply voltages Vcc and Vss, a power supply Vaa having a higher potential than the power supply Vcc, and control terminals 31 and 4.
Switch SW that performs switching by input signal to 1
1 and. As the operation of the horizontal drive circuits 30 and 40, the switch SW1 is switched according to the input signal to the control terminals 31 and 41, and the horizontal scanning period 81
In, in the first, by using Vaa having a high potential as the power supply voltage and in the second and subsequent potentials as the power supply voltage, horizontal drive pulses φH1 and φH2 in which the amplitude h of the first pulse in the horizontal scanning period 81 is set to be large are obtained. This switch S
W1 corresponds to the setting means of claim 7.

Therefore, the horizontal drive pulses φH1 and φH2 of FIG. 9A output from the horizontal drive circuits 30 and 40.
The horizontal transfer register 1 which is the capacitive load of the solid-state image sensor
When 0 is driven, the horizontal transfer register 1 which is a capacitive load
Since it is inevitable that the waveforms of the low frequency components φH1L and φH2L are distorted as shown in FIG. 9B due to 0,
The distortion of the low frequency components φH1L and φH2L is superposed on the first pulse in the horizontal scanning period 81, and the first pulse amplitude h is reduced. Is set to a large value, the horizontal drive pulse φH1, as shown in FIG.
It is possible to maintain the first pulse amplitude h in the horizontal scanning period 81 in φH2 at a magnitude larger than required.

In the third embodiment as described above, the signal charges can be stably and reliably transferred from the horizontal transfer register 10 of the solid-state image pickup device, and as a result, the deterioration of the image quality such as vertical stripe noise can be prevented. become. In particular, it is effective when the drive frequency of the horizontal transfer register 10 is set high as the number of pixels of the solid-state image sensor increases.

In the third embodiment, the horizontal scanning period 8
The first pulse amplitude h of 1 can be easily adjusted by adjusting the voltage. Moreover, the number of pulses having a large amplitude h can be easily increased by adjusting the switching timing. That is, if the correction is insufficient only by increasing the first pulse amplitude h because the time constant of the low frequency component is large, the second and third pulse amplitudes h may be set to be large as necessary.

10 to 12 relate to a fourth embodiment corresponding to claims 8 and 9 of the present invention. FIG. 10 is a circuit block diagram of a solid-state image pickup device, and FIG. 11 is a horizontal drive circuit of FIG. 12 is a signal waveform diagram. In these figures, parts corresponding to those in the conventional example are designated by the same reference numerals.

In the fourth embodiment, the configuration different from the conventional example can generate, as the clock generator 20, clock pulses H1 and H2 having the first wide pulse width w in the horizontal scanning period 81 as shown in FIG. 12 (a). That is what I am doing. For example, the first pulse width w of the horizontal scanning period 81 is the low frequency component φH1L caused by the horizontal transfer register 10 which is the capacitive load of the solid-state image sensor,
In order not to be affected by the distortion of the waveform of φH2L, it is widely set, for example, set sufficiently larger than the time constant of the low frequency components φH1L and φH2L. The amplitudes h of the outputs H1 and H2 of the clock generator 20 are set to the horizontal drive circuits 30 and 4, respectively.
By converting with 0, horizontal drive pulses φH1 and φH2 as shown in FIG. 12B can be obtained.

Therefore, when the horizontal transfer register 10 which is the capacitive load of the solid-state image pickup device is driven by the horizontal drive pulses φH1 and φH2 output from the horizontal drive circuits 30 and 40, the horizontal transfer register 10 which is the capacitive load causes And the waveforms of the low frequency components φH1L and φH2L are shown in FIG.
Although distortion is inevitable as shown in (c), the distortion of the low frequency components φH1L and φH2L is caused by the horizontal drive pulse φH.
1 and φH2 can be suppressed within the first pulse width w of the horizontal scanning period 81.
As shown in (d), it is possible to maintain the first pulse amplitude h of the horizontal drive pulses φH1 and φH2 in the horizontal scanning period 81 at a magnitude larger than required.

In the fourth embodiment as described above, the signal charges can be stably and reliably transferred from the horizontal transfer register 10 of the solid-state image pickup device, and as a result, the deterioration of the image quality such as vertical stripe noise can be prevented. become. In particular, it is effective when the drive frequency of the horizontal transfer register 10 is set high as the number of pixels of the solid-state image sensor increases.

The fourth embodiment is advantageous because it is sufficient to change the logic circuit of the clock generator 20 of the conventional example. The clock generator 20 and the horizontal drive circuits 30 and 40 correspond to the setting means described in claim 9.

The present invention is not limited to the above embodiment. For example, although the horizontal drive circuits 30 and 40 perform the clamp operation by the resistance, they may perform the clamp operation by the diode. Further, although the example in which the present invention is applied to the horizontal drive pulse given to the horizontal transfer register of the solid-state image pickup element is given, it can be applied to the vertical drive pulse and the like. Furthermore, although the two-phase drive system is taken as an example, three-phase
The present invention can also be applied to a four-phase drive system.

Besides, the solid-state image pickup device of the first embodiment or the solid-state image pickup device of the second embodiment and the solid-state image pickup device of the third embodiment or the solid-state image pickup device of the fourth embodiment can be appropriately combined. . In this case, the horizontal drive circuits 30, 40
The inconvenience associated with the high frequency pass circuit and the inconvenience associated with the horizontal transfer register 10 which is the capacitive load of the solid-state image sensor can be eliminated at the same time.

[0047]

According to the first and second solid-state image pickup devices of the present invention, it is possible to generate and output a drive pulse in which a decrease in pulse amplitude at the beginning of a transfer period is suppressed.

In the third and fourth solid-state image pickup devices and the first and second solid-state image pickup element driving methods of the present invention, the charge transfer section, which is a capacitive load of the solid-state image pickup element, causes the driving pulse. It is possible to prevent the pulse amplitude at the beginning of the transfer period from decreasing more than necessary. This is particularly effective when the drive frequency of the charge transfer section is set high as the number of pixels of the solid-state image sensor increases.

Therefore, according to the present invention, the signal charge can be stably and reliably transferred from the charge transfer section of the solid-state image pickup device, and the deterioration of the image quality such as vertical streak noise can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of a first embodiment of a solid-state imaging device of the present invention.

FIG. 2 is a configuration diagram of the horizontal drive circuit of FIG.

FIG. 3 is a signal waveform diagram in the first embodiment.

FIG. 4 is a circuit block diagram of a second embodiment of the solid-state imaging device of the present invention.

5 is a configuration diagram of the horizontal drive circuit of FIG.

FIG. 6 is a signal waveform diagram in the second embodiment.

FIG. 7 is a circuit block diagram of a third embodiment of the solid-state imaging device of the present invention.

8 is a configuration diagram of the horizontal drive circuit of FIG.

FIG. 9 is a signal waveform diagram in the third embodiment.

FIG. 10 is a circuit block diagram of a fourth embodiment of the solid-state imaging device of the present invention.

11 is a configuration diagram of the horizontal drive circuit of FIG.

FIG. 12 is a signal waveform diagram in the fourth embodiment.

FIG. 13 is a circuit block diagram of a conventional solid-state imaging device.

14 is a configuration diagram of the horizontal drive circuit of FIG.

FIG. 15 is a signal waveform diagram of a conventional example.

FIG. 16 is a signal waveform diagram for pointing out the problem of the conventional example.

FIG. 17 is a signal waveform diagram for pointing out another problem of the conventional example.

[Explanation of symbols]

10 Horizontal transfer register of solid-state image sensor 20 Clock generator 30, 40 Horizontal drive circuit C1, C2 Input coupling capacitor of horizontal drive circuit R1, R2 Resistance for potential clamp of horizontal drive circuit Q1, Q2 Current amplification of horizontal drive circuit Transistor Vcc, Vss Power supply voltage for horizontal drive circuit SW1 Horizontal switch circuit changeover switch 70, 71 Correction waveform generation circuit H1, H2 Clock generator output H1L, H2L Low frequency component of clock generator output φH1, φH2 Horizontal drive pulse 81 Horizontal drive pulse horizontal scanning period 82 Horizontal drive pulse horizontal blanking period

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryuichiro Kuga 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (9)

[Claims] 1. A clock pulse generation circuit that generates a clock pulse that defines a drive timing of a charge transfer unit of a solid-state imaging device, and a correction that generates a correction pulse that cancels a low-frequency component of an output from the clock pulse generation circuit. The waveform generation circuit and the output from the correction waveform generation circuit and the output from the clock pulse generation circuit are mixed to transfer the signal charge accumulated in the image pickup section of the solid-state image pickup device, and the potential and the potential are fixed. Generates a drive pulse in which the stop period continues at the required period,
A drive circuit for driving the charge transfer section of the solid-state image pickup device by the drive pulse, and a solid-state image pickup device comprising: 2. The drive circuit includes a transistor, a coupling capacitor connected to the base of the transistor, and a clamp resistor, and the correction pulse is mixed with the low frequency component at the base of the transistor. The solid-state imaging device according to claim 1. 3. A clock pulse generation circuit that generates a clock pulse that defines a drive timing of a charge transfer unit of a solid-state image pickup device, and a high frequency cutoff that cuts off a high frequency component included in a low frequency component of an output from the clock pulse generation circuit. Based on the output of the circuit and the high-frequency cutoff circuit, a drive pulse in which a transfer period for transferring the signal charge accumulated in the image pickup section of the solid-state image pickup device and a stop period for stopping the transfer are connected in a required cycle. A solid-state imaging device comprising: a drive circuit that generates and drives the charge transfer unit of the solid-state imaging device by the drive pulse. 4. The solid-state imaging device according to claim 3, wherein the drive circuit includes a coupling capacitor and a clamp resistor connected to the base of a transistor that outputs a drive pulse. 5. The solid-state imaging device according to claim 3, wherein the high-frequency cutoff circuit includes a low-pass filter including a resistor and a capacitor. 6. A transfer for transferring a signal charge accumulated in an image pickup section of a solid-state image pickup device to a solid-state image pickup element for transferring the signal charge accumulated in the image pickup section by irradiation of light from a charge transfer section to the outside. A solid-state imaging device, characterized in that a period and a stop period for stopping the transfer are continuous in a required cycle, and the pulse of at least one cycle of the start end of the transfer period is driven by a drive pulse set to be larger than a predetermined amplitude. Device driving method. 7. A clock pulse generation circuit that generates a clock pulse that defines a drive timing of a charge transfer unit of the solid-state image pickup device, and an image pickup unit of the solid-state image pickup device based on an output from the clock pulse generation circuit. A drive circuit that generates a drive pulse in which a transfer period for transferring the signal charge and a stop period in which the potential is fixed are continuous in a required cycle, and drives the charge transfer unit of the solid-state image sensor by the drive pulse; The circuit includes a setting unit that sets the amplitude of a pulse of at least one cycle of the start end of the transfer period of the drive pulse to be larger than a predetermined amplitude. 8. A transfer for transferring a signal charge accumulated in an image pickup section of a solid-state image pickup device to a solid-state image pickup element which transfers the signal charge accumulated in the image pickup section by light irradiation from the charge transfer section to the outside. The period and the stop period for stopping the transfer are continuous in a required period, and the pulse width of the pulse of at least one cycle of the start end of the transfer period is driven by a drive pulse set to be wider than a predetermined pulse width. Method for driving solid-state image sensor. 9. A clock pulse generation circuit that generates a clock pulse that defines a drive timing of a charge transfer unit of the solid-state image pickup device, and an image pickup unit of the solid-state image pickup device based on an output from the clock pulse generation circuit. A drive circuit that generates a drive pulse in which a transfer period for transferring the signal charge and a stop period in which the potential is fixed are continuous in a required cycle, and drives the charge transfer unit of the solid-state image sensor by the drive pulse; The circuit is provided with a setting means for setting a pulse width of a pulse of one cycle of at least the start end of the transfer period to be wider than a predetermined pulse width.