JP3587031B2 - Method for manufacturing semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device such as a gate of a MOS (Metal-Oxide-Semiconductor) transistor, a TFT (Thin Film Transistor) formed on an insulating film, and ion implantation. The present invention relates to a method for manufacturing a semiconductor device using a silicidation technique, a method for manufacturing a semiconductor device for reducing resistance by ion implantation, and the like.
[0002]
[Prior art]
In a low-voltage LSI, a transistor formed in an SOI (Silicon on Insulator) has a smaller parasitic capacitance than a bulk MOS transistor, which is advantageous for applications requiring high speed, such as a logic circuit, and is partially put into practical use. Have been. On the other hand, on a circuit, a SIMOX (Separation by Implanted Oxgen) substrate as an ideal fully depleted substrate, an SOI substrate formed using a so-called Smart Cut technology, an SOI substrate formed using a bonding etch-back method, and the like are manufactured. Investigations are underway to reduce costs, improve film thickness uniformity, and improve crystallinity. [IEICE Current Status and Issues of SOI, 80 [7] (1997) Yonehara, p. 758-762].
[0003]
In a MOS LSI, as a device operated at a low voltage, reduction of a gate voltage swing value and control of a low threshold value are important in order to achieve both low leakage current and high transconductance gm. In particular, in CMOS devices, miniaturization has progressed, and the pMOS transistor has shifted to a surface channel type using a p-type polysilicon gate. In a surface channel type device, p is used in a region where the channel concentration is low. ⁺ Polysilicon gates have too low a threshold, making it difficult to keep the transistor enhanced. That is, at a low voltage (for example, less than 1 V), a material capable of changing the Fermi level within a band gap of silicon of 1.1 V is required. In particular, in a fully depleted SOI, it is difficult to control a threshold value by controlling a channel concentration, and therefore, it is required to control the threshold value by using a work function of a gate film. P with smaller band gap than silicon ⁺ By changing the composition ratio of silicon germanium (SiGe), the work function can be effectively changed mainly in the valence band only, and therefore, the controllability of the threshold value is excellent. Therefore, proposals for use in the gates of fine pMOS transistors and nMOS transistors have been proposed by Institute of Electrical and Electronics Engineers (IEEE) Electronic Devices Letters (USA), 12 (1991) T.A. -J. King et al. , P. 533-535, IEDM (International Electron Devices Meeting) (USA), 10.4.1-4 (1990) -J. King et al. , P. 253-256 and the like.
[0004]
In addition, silicon germanium (Si _1-x Ge _x Is difficult to control above the mid-gap in Si, but can be changed from about 0 to 0.56 V below the mid-gap in Si by changing the composition ratio (x) of germanium in the p-type. At present, a MOS transistor of 0.1 μm to 0.25 μm rule using SiGe as a gate material, including a bulk MOS transistor, and an SOI MOSFET (Field Effect Transistor: FET) are IEDM (USA), 30.2.1 to 4.2.1. (1993) N.P. Kistler and J.M. Woo (UCLA) p. 727-730.
[0005]
On the other hand, in a SRAM, a liquid crystal device (LCD), or a field emission display (FED), a polysilicon FET (Field Effect Transistor) capable of increasing the mobility is used, but the performance is further improved. Due to the demand for a low-temperature process, poly-SiGe.TFT has been developed by J. Electrochem.Soc. (USA), 142 (9) (1995) A. Tsai, A .; J. Tang, T .; Noguchi and R. Reif, p. 3220-3225.
[0006]
As described above, the proposal of a transistor using a poly-SiGe gate is active.
[0007]
Next, a silicidation technique using ion implantation will be described. One of the methods of forming a high melting point metal silicide film such as cobalt silicide or tungsten silicide is to form a high melting point metal (molybdenum, tungsten, tantalum, titanium, or cobalt) film by a sputtering apparatus, and then form the high melting point metal film. There is a method in which silicon (Si) is ion-implanted in a state where the metal film is the outermost surface, and the refractory metal film is silicided to form a silicide film.
[0008]
Next, a technology for lowering the resistance of the SiGe film will be described. Although a low-concentration channel is required for a low-voltage MOS transistor, it is necessary to control the work function of a gate to control a threshold value. Therefore, SiGe whose work function is easily controlled is used as a gate material. However, it is difficult to use the SiGe film as it is because the resistance is too high, so that a method of lowering the resistance value by ion-implanting dopants such as boron ions, boron difluoride ions, arsenic ions, and phosphorus ions into the SiGe film has been performed. I have. Also in this case, ion implantation is performed with the SiGe film being the outermost surface.
[0009]
[Problems to be solved by the invention]
In the method of manufacturing a semiconductor device using SiGe, since the melting point of Ge is 937 ° C. and lower than 1415 ° C., which is the melting point of Si, it is difficult to perform a heat treatment on the SiGe thin film at a temperature equal to or higher than the melting point of Ge. there were. Therefore, the improvement in the crystallinity of SiGe has been limited. Further, Ge diffuses outward during the heat treatment, so that it is necessary to separately prepare a heat treatment apparatus from the viewpoint of cleanliness. In the method of manufacturing a semiconductor device using SiGe, a cleaning step is performed in the same manner as a general Si / LSI manufacturing step. However, the etching rate of a SiGe thin film is significantly different from that of Si, particularly in a solution, and is easily soluble [J. Electrochem. Soc. (USA), 139 (10) (1992) J. Godby, A .; H. Krist, K .; D. Hobart and M.S. E. FIG. Twigg, p. 2943-2947], the RCA (NH) generally used in the Si LSI process is used. ₃ + H ₂ O ₂ + H ₂ O ... HCl + H ₂ O ₂ ) Difficult to employ cleaning. For this reason, it has been difficult to adapt to the Si process. That is, it was necessary to separately prepare a dedicated washing tank.
[0010]
Next, in the method of forming a silicide film by injecting Si ions into the refractory metal film after forming the refractory metal film, since the ion implantation is performed directly on the refractory metal surface, It scatters to the end station part inside the ion implanter, and that part is contaminated. When the next wafer processing is performed in this state, there is a problem that the high-melting metal adhered to the inside of the apparatus is sputtered and adheres to the surface of the wafer or is injected, thereby deteriorating the quality. I was
[0011]
Next, in the method of lowering the resistance value by implanting ions into SiGe, the ions are implanted directly into the SiGe surface, so that the sputtered Ge atoms scatter to the end station portion inside the ion implanter, and that portion is contaminated. You. When the next wafer processing is performed in this state, there has been a problem that Ge adhering to the inside of the apparatus is sputtered and adheres to the wafer surface or is injected.
[0012]
One of the methods for solving the problem of contamination of the end station portion is to completely remove contaminants by performing ion implantation on dummy wafers. This is unrealistic because it requires a long process. On the other hand, the method of performing maintenance on the end station portion of the apparatus has a problem that it takes time and effort and is not acceptable in an actual production line.
[0013]
[Means for Solving the Problems]
The present invention is a method for manufacturing a semiconductor device which has been made to solve the above-mentioned problems. The first manufacturing method is a method for solving the problems at the time of the above heat treatment and at the time of cleaning, and when forming a silicon germanium (SiGe) film as a gate material of an insulated gate transistor, the SiGe film was formed. Thereafter, the method includes a step of coating and forming a silicon (Si) film on the SiGe film, and a step of heat-treating the SiGe film at a temperature equal to or higher than the melting point of germanium (Ge) and lower than the melting point of Si.
[0014]
In the first manufacturing method, after the SiGe film is coated on the SiGe film and then heat-treated at a temperature not lower than the melting point of Ge and lower than the melting point of Si, the SiGe film is capped by the Si film. Thus, the SiGe film does not flow, and a good crystallized SiGe film is formed while maintaining the flatness. Further, since the SiGe film is covered with the Si film, the wafer surface can be easily cleaned without dissolving the SiGe film. Therefore, it is possible to use a conventional Si / LSI cleaning process. In addition, there is no need to prepare a special washing tank.
[0015]
The second manufacturing method is a method for solving the problems at the time of the heat treatment and the problems at the time of cleaning. In forming a SiGe film serving as a channel material of a thin film transistor, after forming the SiGe film, the second method is performed on the SiGe film. And a heat treatment of the SiGe film at a temperature equal to or higher than the melting point of Ge and lower than the melting point of Si.
[0016]
In the second manufacturing method, similarly to the first manufacturing method, the SiGe film is capped by the Si film during the heat treatment at a temperature equal to or higher than the melting point of Ge and lower than the melting point of Si, and the SiGe film flows. A good crystallized SiGe film is formed while maintaining flatness. Further, since the SiGe film is covered with the Si film, the wafer surface can be easily cleaned without dissolving the SiGe film. Therefore, it is possible to use a conventional Si / LSI cleaning process. In addition, there is no need to prepare a special washing tank.
[0017]
The third manufacturing method is a method for solving the problem at the time of the above-described ion implantation, in which a step of forming a high-melting-point metal film and then coating and forming a Si film on the high-melting-point metal film is performed. The method is characterized by including a step of implanting ions into the refractory metal film and a step of removing the Si film.
[0018]
In the third manufacturing method, since a Si film is formed on the high-melting-point metal film by coating and then Si is ion-implanted into the high-melting-point metal film through the Si film, the high-melting-point metal is sputtered by the ion-implanted Si. Since the silicidation is performed without scattering, the end station in the apparatus is not contaminated. Therefore, it is not necessary to decontaminate the end station in the apparatus.
[0019]
The fourth manufacturing method is a method for solving the problem at the time of the ion implantation, in which a SiGe film is formed and then a Si film is formed on the SiGe film, and the ion implantation is performed on the SiGe film through the Si film. And a step of removing the Si film.
[0020]
In the fourth manufacturing method, since the Si film is coated on the SiGe film and then Si is ion-implanted into the SiGe film through the Si film, SiGe is not sputtered and scattered by the ion-implanted Si. Since the resistance of the SiGe film is reduced, contamination of the end station in the apparatus is eliminated. Therefore, it is not necessary to decontaminate the end station in the apparatus.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
An example of an embodiment according to the first manufacturing method of the present invention will be described with reference to a manufacturing process diagram of FIG.
[0022]
As shown in FIG. 1A, after an element isolation region 14 is formed in a silicon (Si) substrate 11 in which a silicon oxide layer 12 and a silicon layer 13 are laminated on a silicon (Si) substrate 11, A gate insulating film 15 is formed on the surface of the Si layer 13. In order to form the gate insulating film 15 thin, for example, RTO (Rapid Thermal Oxidation) is performed at a high temperature for a short time in an oxygen atmosphere, for example. For example, the surface of the Si layer 13 is oxidized for 30 seconds in a dry oxygen atmosphere at 950 ° C. to form a Si oxide film of about 4 nm. In this case, in order to suppress threshold fluctuation due to penetration of boron (B) into the oxide film, for example, nitrous oxide (N ₂ O) RTN (Rapid Thermal Nitrogation) in an atmosphere may be performed continuously [IEEE Electron Device Letters (USA), Fifteen (12) (1994) -Q. Yao et al. , P. 516-519].
[0023]
Next, as shown in FIG. 1B, a SiGe film 16 used as a gate film is formed on the gate insulating film 15. The SiGe film 16 is formed by using germane (GeH) as a source gas. ₄ ) And monosilane (SiH) ₄ ) May be used to form the film. The method is described in J. Electrochem. Soc. (USA), 142 (9) (1995) A. Tsai, A .; J. Tang, T .; Noguchi and R. Reif, p. 3220-3225, IEEE Electron Device Letters (USA), 12 (1991) T.A. -J. King et al. , P. 533-535, IEDM (USA), 10.4.1-4 (1990). -J. King et al. , P. 253-256. Alternatively, the film may be formed by a sputtering method.
[0024]
When forming the SiGe film 16 by the latter sputtering method, the SiGe film 16 is deposited at a low temperature of about 200 ° C. in an argon (sputtering atom) atmosphere to control the SiGe film 16 to a predetermined ratio, for example. The SiGe target is formed by depositing SiGe to a thickness of, for example, about 80.0 nm.
[0025]
Subsequently, Si is deposited on the SiGe film 16 to form the Si film 17. For example, after breaking the vacuum of the atmosphere for forming the SiGe film 16 and replacing the SiGe target with a Si target or moving to another processing chamber having a SiGe target, the thickness is 1.0 nm or more and 200 nm or less, for example, approximately An Si film 17 having a thickness of 6.0 nm is formed, and the SiGe film 16 is covered with the Si film 17. The Si film 17 can be formed by a low pressure CVD (LP-CVD) method, in which case it can be formed at a temperature of about 500 ° C. On the other hand, when the Si film 17 is formed by the plasma CVD method, the temperature can be lowered to about 200 ° C., but a large amount of hydrogen is taken into the film, so that when crystallization is performed by ELA (Excimer Laser Annealing). Requires pre-annealing without hydrogen.
[0026]
Next, as shown in FIG. 1C, a constant dose [for example, BF for P-type is applied to the SiGe film 16. ₂ 3 × 10 ions or B ions ^Fifteen Pieces / cm ² ), And then heat treatment for activation and crystallization is performed. This heat treatment temperature is a temperature not lower than the melting point of Ge (937 ° C.) and not higher than the melting point of Si (1415 ° C.). Alternatively, heat treatment such as ELA and RTA (Rapid Thermal Annealing) is also effective. Also in this case, heat treatment is performed so that SiGe has a temperature equal to or higher than the melting point of Ge. Since the SiGe film 16 is covered with the Si film 17, it is possible to perform a heat treatment at a temperature equal to or higher than the melting point of Ge, which was impossible because the SiGe film 16 alone melts the SiGe film 16. An excellent crystallized film of the SiGe film 16 can be obtained in a state where the flatness of the SiGe film 16 is maintained. As a result, a low-resistance SiGe film 16 having a high activation rate is obtained.
[0027]
On the other hand, if the heat treatment is performed at a temperature equal to or higher than the melting point of Si, the Si film 17 also flows and cannot maintain the shape before the heat treatment, which causes a problem. Further, if the heat treatment is performed at a temperature lower than the melting point of Ge, a sufficient SiGe crystallized film cannot be obtained. Therefore, as described above, this heat treatment needs to be performed at a temperature higher than the melting point of Ge and lower than the melting point of Si.
[0028]
Thereafter, as shown in FIG. 1D, the Si film 17 / SiGe film 16 is patterned using lithography and etching to form a gate pattern 21. After that, a fixed dose [for example, BF for P-type ₂ 3 × 10 ions or B ions ^Fifteen Pieces / cm ² The source / drain regions 22 and 23 are formed in the Si layer 13 by performing self-aligned ion implantation using the gate pattern 21 as a mask.
[0029]
Next, a conventional LSI manufacturing process of depositing an interlayer insulating film 31, forming contact holes 32 and 33 by lithography for contact formation and etching, removing a mask used for the etching, and forming metal wirings 34 and 35 is performed. .
[0030]
In the first manufacturing method, the SiGe film 16 may be formed of a SiGe film containing impurities by introducing an impurity gas into the film formation atmosphere. As the impurity gas introduced at that time, for example, diborane (B ₂ H ₆ ) Can be used. As the n-type impurity gas, for example, phosphine (PH ₃ ), Arsine (AsH ₃ ) Can be used. As described above, by forming the SiGe film 16 with the SiGe film containing impurities, the gate pattern 21 has a low resistance even without performing ion implantation into the SiGe film 16, and high performance can be achieved.
[0031]
In the first manufacturing method, the SiGe film 16 is coated on the SiGe film 16 and then heat-treated at a temperature equal to or higher than the melting point of Ge and lower than the melting point of Si. The capped state is obtained, the SiGe film 16 does not flow, and a good crystallized SiGe film 16 is formed while maintaining the flatness. Further, since the SiGe film 16 is covered with the Si film 17, the wafer surface can be easily cleaned without dissolving the SiGe film 16, so that a conventional Si / LSI cleaning process can be used. Therefore, there is no need to prepare a special washing tank. After the gate pattern 21 is formed, it is also possible to perform a normal salicide (Self-Aligned Silicidation) technique.
[0032]
Next, an example of an embodiment according to the second manufacturing method of the present invention will be described with reference to a manufacturing process diagram of FIG. FIG. 2 illustrates an example in which the present invention is applied to a TFT channel in an SOI such as on a glass substrate.
[0033]
As shown in FIG. 2A, an insulating film such as SiO 2 is formed on the glass substrate 51. ₂ A film 52 is formed, and a SiGe film 53 is formed thereon with a thickness of, for example, 50 nm. The formation of the SiGe film 53 is performed by the CVD method or the sputtering method in the same manner as described in the first manufacturing method. Subsequently, Si is deposited on the SiGe film 53 to form a Si film 54 having a thickness of, for example, 5 nm. For example, when the SiGe film 53 is formed by the CVD method, the Si film 54 is also formed continuously by changing the source gas in the same chamber. Alternatively, when the SiGe film 53 is formed by the sputtering method, the SiGe target is replaced with the Si target without breaking the vacuum of the film formation atmosphere of the SiGe film 53 to form the film. As a result, the SiGe film 53 is covered with the Si film 54, and the Si film 54 and the SiGe film 53 become channels. In this case, the thickness of the SiGe film 53 is 10 nm to 100 nm, preferably 30 nm to 80 nm, while the thickness of the Si film 54 is 1.0 nm to 100 nm, preferably 30 nm to 50 nm.
[0034]
Thereafter, as shown in FIG. 2B, a heat treatment for crystallization is performed. The heat treatment temperature is a temperature higher than the melting point of Ge (937 ° C.) and lower than the melting point of Si (1415 ° C.), for example, a maximum processing temperature suitable for crystallization within this temperature range. This heat treatment is also effectively performed by RTA or the like by ELA, lamp annealing (for example, annealing using halogen lamp light or ultraviolet arc lamp light). Also in this case, excimer laser light or lamp light is applied so that SiGe has a temperature equal to or higher than the melting point of Ge and lower than the melting point of Si. As a result, since the SiGe film 53 is covered with the Si film 54, it is possible to perform a heat treatment at a temperature equal to or higher than the melting point of Ge, which was impossible because the SiGe film 53 alone melts. Thereby, an excellent crystallized film of the SiGe film 53 can be obtained in a state where the flatness of the SiGe film 53 is maintained. Therefore, the SiGe film 53 becomes a film having high mobility. During the heat treatment, the SiGe film 53 is in a semi-molten state, ₂ Even at the interface between the layer 52 and the SiGe film 53, SiO ₂ As in the case of the / Si interface, there is also a possibility of controlling the plane orientation to minimize the (100) plane surface energy. On the other hand, although not shown, the (100) plane is also stable at the Si / SiGe interface, so that in the case of SiGe heteroepitaxial growth on a Si wafer, a (100) plane wafer is usually used.
[0035]
On the other hand, when the heat treatment is performed at a temperature equal to or higher than the melting point of Si, the Si film 54 also flows and cannot maintain the shape before the heat treatment, which causes inconvenience. Further, if the heat treatment is performed at a temperature lower than the melting point of Ge, a sufficient SiGe crystallized film cannot be obtained. Therefore, as described above, this heat treatment needs to be performed at a temperature equal to or higher than the melting point of Ge and lower than the melting point of Si.
[0036]
Next, as shown in FIG. 2C, a gate oxide film (SiO 2) is formed on the surface of the Si film 54. ₂ After the formation of the (film) 55, the Si film 54 and the SiGe film 53 are patterned by a normal process to separate an activation region, and further, an Si gate 56 is formed, and the Si film 54 and the SiGe on both sides of the Si gate are formed. Source / drain 57 and 58 are formed on film 53. Then, an interlayer insulating film 61 is deposited, connection holes 62 and 63 are formed by a lithography process for contact formation and etching, and after removing a mask used for the etching, metal electrodes 64 and 65 are formed. The TFT 50 is completed by performing an LSI manufacturing process. In the TFT 50 thus formed, SiO 2 ₂ / Si interface is SiO ₂ Since the interface state density is lower than the / SiGe interface, the S (swing) value is excellent and the leakage can be reduced.
[0037]
In the second manufacturing method, the SiGe film 53 may be formed of a SiGe film containing impurities by introducing an impurity gas into the film formation atmosphere. As the impurity gas introduced at that time, for example, diborane (B ₂ H ₆ ) Can be used. As the n-type impurity gas, for example, phosphine (PH ₃ ), Arsine (AsH ₃ ) Can be used.
[0038]
In the case where a commercially available glass having a low melting point is used for the substrate, a process at a temperature of 600 ° C. or lower, preferably 450 ° C. or lower is required. After the film 54 and the SiGe film 53 are deposited, a low-temperature process can be performed by using the ELA method. As an example of the ELA conditions, as an example, a xenon chlorine (XeCl) excimer laser having a wavelength of 308 nm is used, and 350 mJ / cm per shot is used. ² 1 shot irradiation with the energy of
[0039]
In the second manufacturing method, similarly to the first manufacturing method, the SiGe film 53 is capped by the Si film 54 during the heat treatment at a temperature equal to or higher than the melting point of Ge and lower than the melting point of Si. The 53 does not flow, and a good crystallized SiGe film 53 is formed while maintaining the flatness. Further, since the SiGe film 53 is covered with the Si film 54, the surface of the wafer can be easily cleaned without dissolving the SiGe film 53. Therefore, a cleaning process of a conventional Si / LSI process can be used. Therefore, there is no need to prepare a special washing tank. After the gate pattern 21 is formed, a normal salicide technique can be performed.
[0040]
When a channel made of the SiGe film 53 is formed on the glass substrate 51 by a low-temperature process of 600 ° C. or less, for example, when irradiation with excimer laser (UV pulse) light is performed, the SiGe film is hardly heated. Since the heat treatment can be performed on the film 53, the performance of the TFT 50 can be improved.
[0041]
Next, an example of an embodiment according to the third manufacturing method of the present invention will be described with reference to a manufacturing process diagram of FIG. FIG. 3 shows an example of silicidation of a high melting point metal film by ion implantation.
[0042]
As shown in FIG. 3A, an element isolation region 53 for isolating an element formation region 52 is formed on a semiconductor substrate 51 by a normal MIS (Metal Insulator semiconductor) transistor process. A gate electrode 55 is formed via the gate insulating film 54. Next, after forming LDDs (Lightly Doped Drains) 56 and 57, sidewalls 58 are formed on both sides of the gate electrode 55, and the source / drain regions 59 are formed by ion implantation using the gate electrode 55 and the sidewalls 58 as a mask. , 60 are formed.
[0043]
A refractory metal film 61 covering the gate electrode 55 is formed on the semiconductor substrate 51 as described above. The refractory metal film 61 may be any material that can be silicided, such as cobalt, and may be, for example, tungsten, molybdenum, tantalum, or titanium, in addition to the above-described cobalt. Subsequently, a Si film 62 is formed so as to cover the surface of the refractory metal film 61 by a sputtering method. The refractory metal film 61 and the Si film 62 can be continuously formed by a CVD method.
[0044]
Thereafter, as shown in FIG. 3B, Si is ion-implanted into the refractory metal film 61 through the Si film 62. At this time, before ion implantation, an ion implantation mask (not shown) having an opening provided on the gate electrode 55 and an opening from the source / drain regions 59 and 60 to the element isolation region 53 is formed. In this ion implantation, the Si film 62 does not serve as a mask, and the dopant is injected into the high melting point metal film 61 through the Si film 62. The thickness of the Si film 62 can be made any thickness by changing the acceleration voltage at the time of ion implantation, but is preferably 100 nm or less. Thus, a silicide layer 63 is formed on the gate electrode 55, and silicide layers 64, 65 are formed on a region from the source / drain regions 59, 60 to the element isolation region 53. At this time, the high melting point metal film 61 is not sputtered and adheres to the end station of the ion implantation apparatus (not shown).
[0045]
After removing the ion implantation mask, the Si film 62 is further removed using a dry etching apparatus or a wet cleaning apparatus. As a result, silicide layers 63, 64, and 65 are formed on the gate electrode 55 and the source / drain regions 59 and 60 without causing cross-contamination through the ion implantation device, as shown in FIG. Is done. Thereafter, although not shown, the refractory metal film 61 in the non-silicided portion is removed by, for example, etching.
[0046]
In the third manufacturing method, after the Si film 62 is formed on the high melting point metal film 61 by coating, the Si is ion-implanted into the high melting point metal film 61 through the Si film 62. The metal film 61 is silicided without being sputtered and scattered. Therefore, the contamination of the end station in the ion implantation apparatus (not shown) is eliminated, so that it is not necessary to remove the contamination of the end station in the ion implantation apparatus. Further, since the refractory metal film 61 is covered with the Si film 62, a cleaning step such as RCA cleaning can be added immediately before ion implantation.
[0047]
Next, an example of an embodiment according to a fourth manufacturing method of the present invention will be described with reference to a manufacturing process diagram of FIG. FIG. 4 shows, as an example, reduction of the resistance of the SiGe film by ion implantation.
[0048]
As shown in FIG. 4A, a SiGe film 72 is formed on the substrate 71 by, for example, a sputtering method. Subsequently, a Si film 73 is formed by a sputtering method so as to cover the surface of the SiGe film 72. The SiGe film 72 and the Si film 73 can be continuously formed by a CVD method.
[0049]
Thereafter, as shown in FIG. 4B, a dopant for lowering the resistance is ion-implanted into the SiGe film 72 through the Si film 73. As the dopant, boron ions or boron difluoride ions, which are P-type impurity ions, are used when the SiGe film 72 is made P-type to lower the resistance. Phosphorus ions, arsenic ions, and the like, which are ions, are used. In this ion implantation, the Si film 73 does not serve as a mask, and the dopant is injected into the SiGe film 72 through the Si film 73. The thickness of the Si film 73 can be made any thickness by changing the acceleration voltage at the time of ion implantation, but is usually 100 nm or less. As a result, the SiGe film 72 is not sputtered and Ge does not adhere to the end station.
[0050]
Thereafter, the Si film 73 is removed using a dry etching device or a wet cleaning device. This makes it possible to obtain a low-resistance SiGe film 72 as shown in FIG. 4C without causing cross-contamination via the ion implantation apparatus. Although not shown, a substrate having a gate insulating film formed on a semiconductor substrate is used as the substrate 71, and the SiGe film 72 is formed on the gate insulating film and patterned to form a low-resistance gate electrode. It becomes possible to do.
[0051]
In the fourth manufacturing method, the SiGe film 72 is formed by coating the SiGe film 72 and then Si is ion-implanted into the SiGe film 72 through the Si film 73. Therefore, the SiGe film 72 is sputtered by the ion-implanted Si. Since the resistance of the SiGe film 72 is reduced without scattering, the end station in the ion implantation device (not shown) is not contaminated. Therefore, it is not necessary to decontaminate the end station in the apparatus. Further, since the SiGe film 72 is covered with the Si film 73, a cleaning step such as RCA cleaning can be added immediately before ion implantation.
[0052]
Next, after the Si film was formed on the SiGe film, the state of contamination of the end station of the ion implantation apparatus by performing the ion implantation was evaluated by examining the surface of the wafer on which the work was performed immediately after the ion implantation was performed using concentrated fluorescent X-rays. Determined by analysis. The result is shown in FIG. FIG. 5A shows the case where a Si film is formed, and no Ge peak (peak at 9.88 keV) is not shown. On the other hand, FIG. 5B shows a case where no Si film is formed, and a Ge peak (peak at 9.88 keV) appears. That is, it can be seen that the formation of the Si film prevents Ge from being scattered by ion implantation. In FIG. 5, the vertical axis indicates the integrated intensity of the fluorescent X-ray, and the horizontal axis indicates the energy of the fluorescent X-ray.
[0053]
【The invention's effect】
As described above, according to the first aspect of the invention, since the heat treatment is performed after the Si film is coated on the SiGe film, the heat treatment can be performed at a temperature equal to or higher than the melting point of Ge. Therefore, the crystallinity and the activation rate can be improved. In addition, since it is covered with the Si film, normal RCA cleaning can be performed.
[0054]
According to the second aspect, since the heat treatment is performed after the Si film is coated on the SiGe film, the heat treatment can be performed at a temperature equal to or higher than the melting point of Ge. Therefore, the crystallinity of the SiGe film serving as a channel can be improved, so that the mobility can be improved.
[0055]
According to the third aspect, since the high melting point metal is prevented from scattering at the time of ion implantation by the Si film, it becomes possible to prevent the end station of the ion implantation apparatus from being contaminated by the high melting point metal. Therefore, contamination of other wafers through the ion implantation apparatus is eliminated, so that a silicide film having excellent quality can be formed, and apparatus maintenance for removing contamination is not required.
[0056]
According to the fourth aspect, since the Si film prevents Ge in SiGe from being scattered during ion implantation, it is possible to prevent Ge from contaminating the end station of the ion implantation apparatus. Therefore, contamination of other wafers through the ion implantation apparatus is eliminated, so that a silicide film having excellent quality can be formed, and apparatus maintenance for removing contamination is not required.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram illustrating an example of an embodiment according to a first manufacturing method of the present invention.
FIG. 2 is a manufacturing process diagram illustrating an example of an embodiment according to a second manufacturing method of the present invention.
FIG. 3 is a manufacturing process diagram illustrating an example of an embodiment according to a third manufacturing method of the present invention.
FIG. 4 is a manufacturing process diagram illustrating an example of an embodiment according to a fourth manufacturing method of the present invention.
FIG. 5 is an explanatory diagram of the results of a concentrated X-ray fluorescence analysis in which the state of contamination on the surface of a work wafer due to the presence or absence of a Si film was examined.
[Explanation of symbols]
16 ... SiGe film, 17 ... Si film

Claims (12)

When forming a silicon germanium film as a gate material of an insulated gate transistor,
After forming the silicon germanium film, a step of forming a silicon film on the silicon germanium film,
Heat treating the silicon germanium film at a temperature equal to or higher than the melting point of germanium and lower than the melting point of silicon. The method for manufacturing a semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, characterized in that the silicon germanium film is formed from a silicon germanium film containing impurities by introducing an impurity gas into a film formation atmosphere. When forming a silicon germanium film to be a channel material of a thin film transistor,
After forming the silicon germanium film, a step of forming a silicon film on the silicon germanium film,
Heat treating the silicon germanium film at a temperature equal to or higher than the melting point of germanium and lower than the melting point of silicon. The method for manufacturing a semiconductor device according to claim 3,
A method for manufacturing a semiconductor device, characterized in that the silicon germanium film is formed from a silicon germanium film containing impurities by introducing an impurity gas into a film formation atmosphere. The method for manufacturing a semiconductor device according to claim 3,
Forming the silicon germanium film on the insulating film formed on the substrate,
The silicon film is formed continuously to the silicon germanium film,
A method for manufacturing a semiconductor device, wherein the heat treatment is performed by irradiation with energy rays. The method for manufacturing a semiconductor device according to claim 4,
Forming the silicon germanium film on the insulating film formed on the substrate,
The silicon film is formed continuously to the silicon germanium film,
A method for manufacturing a semiconductor device, wherein the heat treatment is performed by irradiation with energy rays. The method for manufacturing a semiconductor device according to claim 5,
The method of manufacturing a semiconductor device, wherein the irradiation of the energy ray is performed by irradiation of a lamp light or an excimer laser light. The method for manufacturing a semiconductor device according to claim 6,
The method of manufacturing a semiconductor device, wherein the irradiation of the energy ray is performed by irradiation of a lamp light or an excimer laser light. Forming a silicon film on the refractory metal film after forming the refractory metal film,
Implanting ions into the refractory metal film through the silicon film;
Removing the silicon film. The method of manufacturing a semiconductor device according to claim 9,
In the ion implantation, using silicon ions as a dopant,
A method for manufacturing a semiconductor device, wherein the refractory metal film is silicided by the ion implantation. Forming a silicon germanium film on the silicon germanium film after forming a silicon film,
Implanting ions into the silicon germanium film through the silicon film;
Removing the silicon film. The method for manufacturing a semiconductor device according to claim 11,
In the ion implantation, p-type impurity ions or n-type impurity ions are used as dopants,
A method for manufacturing a semiconductor device, wherein the ion implantation lowers the resistance of the silicon germanium film.

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