JP3583999B2 - Level conversion circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a level conversion circuit that converts a voltage amplitude of an input signal into a larger voltage amplitude, a semiconductor device and a display device using the same.
[0002]
[Prior art]
In recent years, as an integrated circuit using bulk silicon, a chip called a system-on-silicon having a microprocessor or a memory mounted on the same chip as a logic circuit has been developed. Along with this, the development of technology for integrating many types of circuits into one chip with as small a design rule as possible has been promoted.
[0003]
However, since the circuit is designed according to different design rules for each type of circuit, it is inevitable to integrate circuits having different design rules. As a result, a plurality of circuits operating at different power supply voltages are mixedly mounted on one chip. In this case, it is necessary to perform voltage level conversion at an interface between different circuits.
[0004]
By mounting a plurality of different types of circuits on the same chip, the speed can be improved. Therefore, high-speed operation characteristics are also required for a level conversion circuit that performs voltage level conversion between different circuits.
[0005]
Further, a thin film transistor made of polycrystalline silicon is used for a display device such as a liquid crystal display device and an organic EL (electroluminescence) device. When a level conversion circuit is provided on the same substrate as such a display device, the level conversion circuit is also formed of a thin film transistor made of polycrystalline silicon.
[0006]
In a transistor manufacturing process, device characteristics such as a threshold voltage vary. In particular, in a thin film transistor made of polycrystalline silicon, variation in element characteristics such as a threshold voltage is large. Therefore, a level conversion circuit that can operate reliably even when the element characteristics such as the threshold voltage of the thin film transistor varies is desired.
[0007]
In addition, such a display device requires a level conversion circuit that can operate even when an input signal with a small amplitude is given and that can operate at high speed from the viewpoint of low power consumption and high definition.
[0008]
FIG. 45 is a circuit diagram showing a first example of a conventional level conversion circuit.
The level conversion circuit 800 of FIG. 45 includes two p-channel MOSFETs (metal oxide semiconductor field effect transistors) 801 and 802 and two n-channel MOSFETs 803 and 804.
[0009]
P-channel MOSFETs 801 and 802 are connected between power supply terminals receiving power supply potential VDD and output nodes N11 and N12, respectively, and n-channel MOSFETs 803 and 804 are connected between output nodes N11 and N12 and a ground terminal, respectively. The gates of the p-channel MOSFETs 801 and 802 are cross-connected to output nodes N12 and N11, respectively. The gates of the n-channel MOSFETs 803 and 804 are supplied with input signals CLK1 and CLK2 which change complementarily to each other.
[0010]
When the input signal CLK1 goes high and the input signal CLK2 goes low, the n-channel MOSFET 803 turns on and the n-channel MOSFET 804 turns off. Thereby, the p-channel MOSFET 802 turns on and the p-channel MOSFET 801 turns off. As a result, the output potential Vout of the output node N12 increases. Conversely, when the input signal CLK1 goes low and the input signal CLK2 goes high, the output potential Vout of the output node N12 decreases.
[0011]
In this case, in order for the n-channel MOSFETs 803 and 804 to turn on, the voltage amplitude of the input signals CLK1 and CLK2 needs to be larger than the threshold voltage Vtn of the n-channel MOSFETs 803 and 804.
[0012]
Therefore, the level conversion circuit 800 of FIG. 45 is used when the voltage ratio between the input signal and the output signal is small.
[0013]
For example, the level conversion circuit 800 converts a 3V signal into a 5V signal, converts a 2.5V signal into a 3V signal, or converts a 1.8V signal into a 2.5V signal. This is effective when converting to a system signal or a 3.3V system signal.
[0014]
FIG. 46 is a circuit diagram showing a second example of a conventional level conversion circuit.
The level conversion circuit 810 of FIG. 46 includes a bias circuit 811, a p-channel MOSFET 812, and an n-channel MOSFET 813.
[0015]
P-channel MOSFET 812 is connected between a power supply terminal receiving power supply potential VDD and output node N13, and n-channel MOSFET 813 is connected between output node N13 and a power supply terminal receiving predetermined potential VEE. Input signal CLK is applied to the gate of p-channel MOSFET 812 and bias circuit 811. The bias circuit 811 shifts the center level of the input signal CLK and applies the shifted signal to the gate of the n-channel MOSFET 813.
[0016]
When the input signal CLK goes high, the p-channel MOSFET 812 turns off and the n-channel MOSFET 813 turns on. Thereby, output potential Vout of output node N13 decreases. When the input signal CLK goes low, the p-channel MOSFET 812 turns on and the n-channel MOSFET 813 turns off. Thereby, the output potential Vout of the output node N13 rises.
[0017]
In this case, since the center level of input signal CLK is shifted by bias circuit 811, level conversion circuit 810 operates even when the voltage amplitude of input signal CLK is smaller than threshold voltage Vtn of n-channel MOSFET 813.
[0018]
FIG. 47 is a circuit diagram showing a third example of the conventional level conversion circuit.
The level conversion circuit 820 of FIG. 47 includes a clamp circuit 821 and a current mirror type amplifier 822.
[0019]
The current mirror amplifier 822 includes two p-channel MOSFETs 831 and 832 and two n-channel MOSFETs 833 and 834. P-channel MOSFETs 831 and 832 are connected between a power supply terminal receiving power supply potential VDD and output nodes N14 and N15, respectively. N-channel MOSFETs 833 and 834 are connected between output nodes N14 and N15 and a ground terminal, respectively. Gates of p-channel MOSFETs 831 and 832 are connected to output node N14. The clamp circuit 821 shifts the central level of the input signals CLK1 and CLK2 that change complementarily to each other and applies the shifted signal to the gates of the n-channel MOSFETs 833 and 834.
[0020]
When the input signal CLK1 goes high and the input signal CLK2 goes low, the n-channel MOSFET 833 turns on and the n-channel MOSFET 834 turns off. Thereby, p-channel MOSFETs 831 and 832 are turned on. As a result, the output potential Vout of the output node N15 increases. Conversely, when the input signal CLK1 goes low and the input signal CLK2 goes high, the output potential Vout of the output node N15 decreases.
[0021]
In this case, since the center levels of input signals CLK1 and CLK2 are shifted by clamp circuit 821, level conversion circuit 820 determines that the voltage amplitude of input signals CLK1 and CLK2 is smaller than threshold voltage Vtn of n-channel MOSFETs 833 and 834. Can work even if.
[0022]
FIG. 48 is a circuit diagram showing a fourth example of a conventional level conversion circuit.
The level conversion circuit 840 of FIG. 48 includes a clamp circuit 841 and a PMOS cross-coupled amplifier 842.
[0023]
The PMOS cross-coupled amplifier 842 includes two p-channel MOSFETs 851 and 852 and two n-channel MOSFETs 853 and 854. P-channel MOSFETs 851 and 852 are connected between power supply terminals receiving power supply potential VDD and output nodes N16 and N17, respectively, and n-channel MOSFETs 853 and 854 are connected between output nodes N16 and N17 and a ground terminal, respectively. The gates of p-channel MOSFETs 851 and 852 are cross-connected to output nodes N17 and N16, respectively. The clamp circuit 841 shifts the center level of the input signals CLK1 and CLK2 that change complementarily with each other and applies the shifted signals to the gates of the n-channel MOSFETs 853 and 854, respectively.
[0024]
When the input signal CLK1 goes high and the input signal CLK2 goes low, the n-channel MOSFET 853 turns on and the n-channel MOSFET 854 turns off. Thereby, the p-channel MOSFET 851 turns off and the p-channel MOSFET 852 turns on. As a result, the output potential Vout of the output node N17 increases. Conversely, when the input signal CLK1 goes low and the input signal CLK2 goes high, the output potential Vout of the output node N17 decreases.
[0025]
In this case, since the center levels of input signals CLK1 and CLK2 are shifted by clamp circuit 841, level conversion circuit 840 has a voltage amplitude of input signals CLK1 and CLK2 smaller than threshold voltage Vtn of n-channel MOSFETs 853 and 854. Can work even if.
[0026]
[Problems to be solved by the invention]
As described above, level conversion circuit 800 in FIG. 45 cannot operate when the voltage amplitudes of input signals CLK1 and CLK2 are smaller than threshold voltages Vtn of n-channel MOSFETs 803 and 804.
[0027]
On the other hand, in level conversion circuit 810 of FIG. 46, since the center level of input signal CLK is shifted by bias circuit 811, it operates even when the voltage amplitude of input signal CLK is smaller than threshold voltage Vtn of n-channel MOSFET 813. It is possible to do.
[0028]
Similarly, in clamp circuits 820 and 840 shown in FIGS. 47 and 48, since the center levels of input signals CLK1 and CLK2 are shifted by clamp circuits 821 and 841, the voltage amplitude of input signals CLK1 and CLK2 is reduced by n-channel MOSFETs 833 and 834. , 853, 854 can be operated even when it is smaller than the threshold voltage Vtn.
[0029]
However, the level conversion circuits 810, 820, and 840 shown in FIGS. 46 to 48 may not operate if the threshold voltage Vtn of the n-channel MOSFET greatly deviates from a design value due to a variation in a manufacturing process.
[0030]
In any of the level conversion circuits 800, 810, 820, and 840 in FIGS. 45 to 48, if the threshold voltages of the p-channel MOSFET and the n-channel MOSFET are irregularly varied in the manufacturing process, for example, the n-channel MOSFET The threshold voltage Vtp of the p-channel MOSFET becomes small and the threshold voltage Vtp of the n-channel MOSFET becomes small and the threshold voltage Vtp of the p-channel MOSFET becomes large. , The duty ratio of the output voltage waveform deviates from a predetermined design value.
[0031]
In particular, when the level conversion circuit is used to generate a clock signal for a display device such as a liquid crystal display device or an organic EL device, the duty ratio of the clock signal needs to be set to 50%. When the threshold voltage Vtn of the n-channel MOSFET and the threshold voltage Vtp of the p-channel MOSFET of the level conversion circuit change irregularly, and the duty ratio of the clock signal deviates from 50%, the pixels of the display device are switched between the display devices. Lighting and turning-off times vary.
[0032]
In the level conversion circuit 800 of FIG. 45, the gate charges of the p-channel MOSFETs 801 and 802 are extracted when the n-channel MOSFETs 803 and 804 are turned on and off. Therefore, it takes time to invert the level of the output potential Vout, and high-speed operation cannot be achieved.
[0033]
In particular, when a transistor having a small driving capability such as a thin film transistor made of polycrystalline silicon is used as the p-channel MOSFETs 801 and 802, the time required for inverting the level of the output potential Vout further increases.
[0034]
When the level of the output potential Vout is inverted, a through current flows from the power supply terminal to the ground terminal through the path of the p-channel MOSFET 801 and the n-channel MOSFET 803 or the path of the p-channel MOSFET 802 and the n-channel MOSFET 804. In particular, in the case where it takes time to invert the level of the output potential Vout, the time required for the through current to flow increases, and power consumption increases.
[0035]
In the bias circuit 811 of the level conversion circuit 810 in FIG. 46, a potential difference between the input signal CLK and the output signal is formed by flowing a current through the resistance element. In this case, it takes time until the potential difference between the input signal CLK and the output signal is set, so that high-speed operation is prevented. In addition, a large layout area is required to form a resistance element. In addition, since current always flows through the resistance element, power consumption increases. Furthermore, since high-speed operation cannot be achieved, the through current in the p-channel MOSFET 812 and the n-channel MOSFET 813 in the output stage increases.
[0036]
Similarly, in the clamp circuits 821 and 841 of the level conversion circuits 820 and 840 of FIGS. 47 and 48, similarly to the bias circuit 811 of the level conversion circuit 810 of FIG. 46, high-speed operation is hindered and a large layout area is required. And the power consumption increases.
[0037]
An object of the present invention is to achieve a reliable operation even when a threshold voltage of a transistor deviates from a design value due to a variation in a manufacturing process, and to achieve a high-speed operation, low power consumption, and a small area. An object of the present invention is to provide a conversion circuit, a semiconductor device and a display device using the conversion circuit.
[0038]
Means for Solving the Problems and Effects of the Invention
(1) First invention
A level conversion circuit according to a first aspect of the present invention includes a first transistor connected between a first node receiving a first potential and an output node, and a second transistor receiving a second potential different from the first potential. A second transistor connected between the second node and the output node; receiving the first input signal; turning on both the first and second transistors; Control means for respectively controlling the degree of the ON state of the first and second transistors.
[0039]
In the level conversion circuit according to the present invention, both the first and second transistors are turned on by the control unit, and the first and second transistors are turned on in accordance with the level of the first input signal. Are controlled individually. Thereby, the potential of the output node rises or falls according to the level of the first input signal.
[0040]
In this case, since the potential of the output node changes by controlling the degree of the on state of the first and second transistors that are always on, the voltage amplitude of the first input signal is changed to the first and second levels. Operation can be performed even when the threshold voltage is lower than the threshold voltage of the second transistor. Further, even when the threshold voltages of the first and second transistors deviate significantly from the design values, the duty ratio of the potential change at the output node accurately corresponds to the duty ratio of the first input signal. As described above, even when the threshold voltage of the transistor deviates from the design value due to a variation in the manufacturing process, the semiconductor device can operate reliably.
[0041]
Further, the degree of the ON state of the first and second transistors that are always in the ON state is controlled, so that the potential of the output node changes, so that high-speed operation can be performed. Further, since the transition period of the potential level of the output node is shortened by enabling the high-speed operation, the period in which the through current flows is shortened. Thus, low power consumption can be achieved.
[0042]
Further, even if the voltage amplitude of the first input signal is small, a circuit for shifting the level is not required, so that the area can be reduced.
[0043]
(2) Second invention
The level conversion circuit according to a second aspect of the present invention is the level conversion circuit according to the first aspect, wherein the first input signal has a voltage amplitude smaller than a potential difference between the first potential and the second potential. It changes with.
[0044]
In this case, the potential of the output node changes with a voltage amplitude larger than the voltage amplitude of the first input signal.
[0045]
(3) Third invention
A level conversion circuit according to a third invention is the level conversion circuit according to the first or second invention, wherein the first input signal changes between the first level and the second level, Is a first conductive channel type field effect transistor, the second transistor is a second conductive channel type field effect transistor, and the control means controls a first potential and a gate potential of the first conductive channel type transistor. The absolute value of the difference between the second conductive channel transistor and the gate potential of the second conductive channel transistor is equal to or greater than the absolute value of the threshold voltage of the first conductive channel transistor. Potential of the first conductive channel type transistor in response to the first and second levels of the first input signal so as to be equal to or greater than the absolute value of the threshold voltage of the type transistor. It is for setting the gate potential of the second conductivity channel type transistor.
[0046]
In this case, the absolute value of the difference between the first potential and the gate potential of the first conductive channel type transistor is equal to or greater than the absolute value of the threshold voltage of the first conductive channel type transistor. The type transistor is always on. Further, when the absolute value of the difference between the second potential and the gate potential of the second conductive channel type transistor is equal to or greater than the absolute value of the threshold voltage of the second conductive channel type transistor, It is always on.
[0047]
Thus, even if the threshold voltage of the transistor deviates from the design value, the transistor can operate reliably, and high-speed operation, low power consumption, and small area can be achieved.
[0048]
(4) Fourth invention
A level conversion circuit according to a fourth invention is the level conversion circuit according to the third invention, wherein the first potential is a positive potential, the second potential is a positive potential lower than the first potential, and ground. Potential or negative potential.
[0049]
In this case, since the first and second transistors are always on, current flows from the first node to the second node via the first and second transistors.
[0050]
(5) Fifth invention
In the level conversion circuit according to a fifth aspect, in the configuration of the level conversion circuit according to the fourth aspect, the second potential is set to a first level and a second level complementarily to the first input signal. It is the changing second input signal.
[0051]
In this case, the first and second levels of the first and second input signals are lower than the first potential, and when the first input signal is at the first level, the second input signal is at the first level. 2 level, and when the first input signal is at the second level, the second input signal is at the first level.
[0052]
(6) Sixth invention
The level conversion circuit according to a sixth aspect of the present invention is the level conversion circuit according to the fourth or fifth aspect, wherein the first conductive channel type field-effect transistor has a first threshold voltage having a first threshold voltage. A channel-type field effect transistor, the second conductive channel-type field effect transistor is a first n-channel field-effect transistor having a second threshold voltage, and the control means includes a first p-channel field-effect transistor. The gate potential of the effect transistor is set within a range lower than the first potential by the absolute value of the first threshold voltage, and the gate potential of the first n-channel field effect transistor is changed from the second potential to the second potential. The threshold voltage is set within a range increased by the threshold voltage of 2 or more.
[0053]
In this case, the gate potential of the first p-channel field-effect transistor is set in a range lower than the first potential by an absolute value of the first threshold voltage or more. The field effect transistor is always on. When the gate potential of the first p-channel field-effect transistor is at a high level within the above range, the first p-channel field-effect transistor is weakly turned on, and the gate potential of the first p-channel field-effect transistor is increased. When it is at a low level within the above range, the first p-channel field effect transistor is strongly turned on.
[0054]
The gate potential of the first n-channel field effect transistor is set within a range that is higher than the second potential by an absolute value of the second threshold voltage or more, so that the first n-channel field effect transistor Is always on. When the gate potential of the first n-channel field-effect transistor is at a low level within the above range, the first n-channel field-effect transistor turns on weakly, and the gate potential of the first n-channel field-effect transistor becomes low. When the level is at a high level within the above range, the first n-channel field effect transistor is strongly turned on.
[0055]
(7) Seventh invention
A level conversion circuit according to a seventh invention is the level conversion circuit according to the sixth invention, wherein the control means includes a second p-channel field-effect transistor, a second n-channel field-effect transistor, and a control circuit. Wherein the source of the second p-channel field effect transistor receives the first potential, and the gate and drain of the second p-channel field effect transistor are connected to the gate of the first p-channel field effect transistor , The source of the second n-channel field-effect transistor receives the first input signal or the second potential, and the gate and drain of the second n-channel field-effect transistor are connected to the first n-channel field-effect transistor. The control circuit is connected to the gate of the second p-channel field-effect transistor according to the level of the first input signal. And controls the rhein potential and the potential of the drain of the second n-channel type field effect transistor.
[0056]
In this case, the gate potential of the first p-channel field-effect transistor is set by the second p-channel field-effect transistor within a range in which the gate potential is lower than the first potential by an absolute value of the first threshold voltage or more. You. Further, the gate potential of the first n-channel field effect transistor is set within a range in which the gate potential of the first n-channel field effect transistor has risen from the second potential by the absolute value of the second threshold voltage or more by the second n-channel field effect transistor. . Further, the gate potential of the first p-channel field effect transistor is controlled within the above range by the control circuit, and the gate potential of the first n-channel field effect transistor is controlled within the above range.
[0057]
(8) Eighth invention
In a level conversion circuit according to an eighth aspect, in the configuration of the level conversion circuit according to the seventh aspect, the control circuit includes first and second load elements, and one end of the first load element is connected to the first load element. Upon receiving the input signal, the other end of the first load element is connected to the gate of the first p-channel field effect transistor, one end of the second load element receives the first potential, and the other end of the second load element The other end is connected to the gate of the first n-channel type field effect transistor.
[0058]
In this case, the gate potential of the first p-channel field effect transistor is controlled by the first load element according to the level of the first input signal, and the first n-channel field effect transistor is controlled by the second load element. Is controlled.
[0059]
In this configuration, since the level conversion circuit is composed of six elements, the area can be reduced.
[0060]
(9) Ninth invention
A level conversion circuit according to a ninth aspect is the level conversion circuit according to the eighth aspect, wherein each of the first and second load elements is a field effect transistor or a resistance element.
[0061]
In this case, the gate potential of the first p-channel type field effect transistor and the gate potential of the first n-channel type field effect transistor are controlled by the field effect transistor or the resistance element.
[0062]
(10) Tenth invention
In a level conversion circuit according to a tenth aspect, in the configuration of the level conversion circuit according to the seventh aspect, the control means further includes a third p-channel field-effect transistor and a third n-channel field-effect transistor. , A source, a gate and a drain of the third p-channel field-effect transistor are connected to a source and an output node of the second p-channel field-effect transistor and a drain of the second p-channel field-effect transistor, respectively. The source, gate and drain of the n-channel field-effect transistor No. 3 are connected to the source and output node of the second n-channel field-effect transistor and the drain of the second n-channel field-effect transistor, respectively. .
[0063]
In this case, even when the difference between the first potential and the second potential is small, the first p-channel field effect transistor and the first n-channel field effect transistor can be reliably turned on. Therefore, low voltage driving becomes possible.
[0064]
(11) Eleventh invention
In a level conversion circuit according to an eleventh aspect, in the configuration of the level conversion circuit according to the sixth aspect, the control means includes a second n-channel type field-effect transistor and a control circuit, The source of the effect transistor receives the first input signal or the second potential, the gate and drain of the second n-channel field effect transistor are connected to the gate of the first n-channel field effect transistor, and the control circuit is , The gate potential of the first n-channel field effect transistor and the drain potential of the second n-channel field effect transistor are controlled in accordance with the level of the first input signal.
[0065]
In this case, the control circuit sets the gate potential of the first p-channel field-effect transistor within a range lower than the first potential by the absolute value of the first threshold voltage. Further, the gate potential of the first n-channel field effect transistor is set within a range in which the gate potential of the first n-channel field effect transistor has risen from the second potential by the absolute value of the second threshold voltage or more by the second n-channel field effect transistor. . Further, the gate potential of the first p-channel field effect transistor is controlled within the above range by the control circuit, and the gate potential of the first n-channel field effect transistor is controlled within the above range.
[0066]
(12) Twelfth invention
In a level conversion circuit according to a twelfth aspect, in the configuration of the level conversion circuit according to the eleventh aspect, the control circuit includes first, second, and third load elements, and one end of the first load element is Upon receiving the first potential, the other end of the first load element is connected to the gate of the first p-channel field effect transistor, and one end of the second load element receives the first input signal or the second potential. The other end of the second load element is connected to the gate of the first p-channel field effect transistor, one end of the third load element receives the first potential, and the other end of the third load element is It is connected to the gate of the first n-channel field effect transistor.
[0067]
In this case, the gate potential of the first p-channel type field effect transistor is controlled by the first and second load elements according to the level of the first input signal, and the first n-channel type is set by the third load element. The gate potential of the field effect transistor is controlled.
[0068]
In this configuration, since the level conversion circuit is composed of six elements, the area can be reduced.
[0069]
(13) 13th invention
A level conversion circuit according to a thirteenth aspect is the level conversion circuit according to the twelfth aspect, wherein each of the first, second, and third load elements is a field-effect transistor or a resistance element. .
[0070]
In this case, the gate potential of the first p-channel type field effect transistor and the gate potential of the first n-channel type field effect transistor are controlled by the field effect transistor or the resistance element.
[0071]
(14) Fourteenth invention
A level conversion circuit according to a fourteenth invention is the level conversion circuit according to any one of the first to thirteenth inventions, wherein the transition between the first level and the second level of the first input signal is provided. The apparatus further includes a blocking unit that blocks a current path from the first node to the second node via the first and second transistors during the period.
[0072]
In this case, current does not flow through the first and second transistors during a transition period between the first level and the second level of the first input signal, so that an increase in power consumption due to a through current is prevented. . Therefore, power consumption is further reduced.
[0073]
(15) Fifteenth invention
A level conversion circuit according to a fifteenth invention is the level conversion circuit according to any one of the first to fourteenth inventions, wherein the first transistor, the second transistor, and the control means are formed of a single crystal on an insulating substrate. , Formed of a polycrystalline or amorphous semiconductor.
[0074]
In this case, an SOI (Silicon on Insulator) device constitutes a level conversion circuit.
[0075]
(16) Sixteenth invention
A semiconductor device according to a sixteenth aspect includes a plurality of logic circuits operating at different power supply voltages, and a level conversion circuit according to any one of the first to fifteenth aspects connected between the plurality of logic circuits. Things.
[0076]
In this case, in a semiconductor device provided with a plurality of logic circuits operating with different power supply voltages, reliable operation can be performed even when the variation in the threshold voltage of the transistor is large in the manufacturing process, and high-speed operation and low power consumption are achieved. And the area can be reduced.
[0077]
(17) Seventeenth invention
A semiconductor device according to a seventeenth aspect of the present invention provides an internal circuit provided on a chip, an external circuit provided outside the chip, and any one of the first to fifteenth connected between the internal circuit and the external circuit. And a level conversion circuit according to the invention.
[0078]
In this case, in a semiconductor device including an internal circuit provided on a chip and an external circuit provided outside the chip, reliable operation can be performed even when a variation in threshold voltage of a transistor is large in a manufacturing process. , High speed operation, low power consumption and small area can be realized.
[0079]
(18) Eighteenth invention
A display device according to an eighteenth aspect of the present invention is a display device comprising: a semiconductor memory provided on a chip; a logic circuit provided on the chip; and first to fifteenth connected between the semiconductor memory and the logic circuit on the chip. And a level conversion circuit according to any one of the inventions.
[0080]
In this case, in a semiconductor device in which a semiconductor memory and a logic circuit are mixedly mounted on a chip, reliable operation can be performed even when a variation in threshold voltage of a transistor is large in a manufacturing process, and high-speed operation and low power consumption are achieved. And the area can be reduced.
[0081]
(19) Nineteenth invention
A semiconductor device according to a nineteenth aspect includes a plurality of sensors, a plurality of selection transistors for selecting one of the plurality of sensors, and a peripheral circuit for driving the plurality of sensors via the plurality of selection transistors. And a level conversion circuit according to any one of the first to fifteenth inventions, which level-converts a predetermined signal and supplies the level-converted signal to a peripheral circuit.
[0082]
In this case, in a semiconductor device having a plurality of selection transistors and a level conversion circuit, reliable operation can be performed even when the threshold voltage of the transistor greatly varies in a manufacturing process, and high-speed operation and low power consumption can be achieved. In addition, the area can be reduced and the definition can be increased.
[0083]
(20) Twentieth invention
A display device according to a twentieth aspect drives a plurality of display elements, a plurality of selection transistors for selecting one of the plurality of display elements, and the plurality of display elements via the plurality of selection transistors. The circuit includes a peripheral circuit and a level conversion circuit according to any one of the first to fifteenth inventions, which level-converts a predetermined signal and supplies the level-converted signal to the peripheral circuit.
[0084]
In this case, in a display device including a plurality of selection transistors and a level conversion circuit, reliable operation can be performed even when variation in threshold voltage of the transistor is large in a manufacturing process, and high-speed operation and low power consumption can be achieved. Small area and high definition can be achieved.
[0085]
(21) Twenty-first invention
A display device according to a twenty-first aspect is the display device according to the twentieth aspect, wherein the plurality of display elements are liquid crystal elements, and the plurality of liquid crystal elements, the plurality of selection transistors, the peripheral circuit, and the level conversion circuit are It is formed on an insulating substrate.
[0086]
In this case, a reliable operation can be performed even when the threshold voltage of the transistor has a large variation in the manufacturing process, and a liquid crystal display device capable of high-speed operation, low power consumption, small area, and high definition is realized. Is done.
[0087]
(22) Twenty-second invention
A display device according to a twenty-second aspect is the display device according to the twentieth aspect, wherein the plurality of display elements are organic electroluminescence elements, the plurality of organic electroluminescence elements, the plurality of selection transistors, the peripheral circuit, and The level conversion circuit is formed on an insulating substrate.
[0088]
In this case, an organic electroluminescent device that can operate reliably even when the threshold voltage of the transistor has a large variation in the manufacturing process, and that can perform high-speed operation, low power consumption, small area, and high definition. Is achieved.
[0089]
(23) Twenty-third invention
A display device according to a twenty-third aspect is the display device according to any one of the twentieth to twenty-second aspects, wherein the plurality of selection transistors and the first and second transistors of the level conversion circuit are thin film transistors. Things.
[0090]
In this case, a reliable operation can be performed even when the variation in the threshold voltage of the thin film transistor is large in the manufacturing process, and a display device capable of high-speed operation, low power consumption, small area, and high definition is realized. You.
[0091]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a circuit diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention.
[0092]
1, the level conversion circuit 1 includes a control unit 10, a driver unit 20, and an inverter 3. The control unit 10 includes a control circuit 100, a p-channel MOSFET (metal oxide semiconductor field effect transistor) 101, and an n-channel MOSFET 102. The driver section 20 includes a p-channel MOSFET 201 and an n-channel MOSFET 202. Inverter 3 is configured by a CMOS circuit including a p-channel MOSFET and an n-channel MOSFET.
[0093]
The control circuit 100 of the control unit 10 is connected to the input nodes I1 and I2, the first node NP, and the second node NN. Input signals CLK1 and CLK2 which change to a high level and a low level complementarily to each other are applied to input nodes I1 and I2, respectively. The source of p-channel MOSFET 101 is connected to a power supply terminal receiving power supply potential VDD, and the gate and drain are connected to first node NP. The source of the n-channel MOSFET 102 is connected to the input node I1, and the gate and drain are connected to the second node NN.
[0094]
In driver section 20, the source of p-channel MOSFET 201 is connected to a power supply terminal receiving power supply potential VDD, the drain is connected to output node NO, and the gate is connected to first node NP. The source of the n-channel MOSFET 202 is connected to the input node I2, the drain is connected to the output node NO, and the gate is connected to the second node NN.
[0095]
The potential difference between the high level and the low level of the input signals CLK1 and CLK2 is smaller than the potential difference between the power supply potential VDD and the ground potential. In this embodiment, the low level of the input signals CLK1 and CLK2 is the ground potential, and the high level is a potential between the power supply potential VDD and the ground potential.
[0096]
Control circuit 100 controls potential VNP of first node NP and potential VNN of second node NN in response to input signals CLK1 and CLK2. The potential VNP of the first node NP is set to a level lower than the power supply potential VDD by the absolute value of the threshold voltage Vtp of the p-channel MOSFET 101 or more. Further, the potential VNN of the second node NN is set to a level higher than the low level of the input signal CLK1 by the absolute value of the threshold voltage Vtn of the n-channel MOSFET 102 or more. Further, the potential of the source of the n-channel MOSFET 102 becomes the level of the input signal CLK1.
[0097]
Thereby, one of the p-channel MOSFET 201 and the n-channel MOSFET 202 turns on strongly and the other turns on weakly. As described above, one of the p-channel MOSFET 201 and the n-channel MOSFET 202 of the driver section 20 is not completely turned off.
[0098]
For example, when the p-channel MOSFET 201 is strongly turned on, the n-channel MOSFET 202 is weakly turned on. Thereby, the value of the on-resistance of the p-channel MOSFET 201 becomes smaller than the value of the on-resistance of the n-channel MOSFET 202. As a result, the output potential Vout of the output node NO increases.
[0099]
When the n-channel MOSFET 202 is strongly turned on, the p-channel MOSFET 201 is weakly turned on. Thereby, the value of the on-resistance of the n-channel MOSFET 202 becomes smaller than the value of the on-resistance of the p-channel MOSFET 201. As a result, the output potential Vout of the output node NO decreases.
[0100]
The inverter 3 converts the output potential Vout into an output potential VOUT that changes between the power supply potential VDD and the ground potential.
[0101]
FIGS. 2, 3 and 4 are schematic diagrams showing examples of possible ranges of the potential VNP of the first node NP and the potential VNN of the second node NN in the level conversion circuit 1 of FIG.
[0102]
As shown in FIGS. 2 to 4, the potential range of the first node NP can be a first level V1 lower than the power supply potential VDD by the threshold voltage Vtp of the p-channel MOSFET 101 and the first level V1. It is between the second level V2 lower than V1. The possible range of the potential VNN of the second node NN is a third level V3 raised from the ground potential GND by the threshold voltage Vtn of the n-channel MOSFET 102, and a fourth level V4 higher than the third level V3. Between.
[0103]
FIG. 2 shows a case where the threshold voltage Vtp of the p-channel MOSFET 101 and the threshold voltage Vtn of the n-channel MOSFET 102 are relatively small. In this case, the potential VNP of the first node NP becomes higher than the potential VNN of the second node NN. Thus, the current flowing through p-channel MOSFET 201 and n-channel MOSFET 202 of driver section 20 is relatively small. Therefore, the through current in the driver section 20 is relatively small, but the operation speed is relatively low.
[0104]
FIG. 3 shows a case where the threshold voltage Vtp of the p-channel MOSFET 101 and the threshold voltage Vtn of the n-channel MOSFET 102 are slightly higher. In this case, the difference between the potential VNP of the first node NP and the potential VNN of the second node NN becomes small. As a result, the value of the current flowing through the p-channel MOSFET 201 and the n-channel MOSFET 202 of the driver unit 20 becomes slightly larger. Therefore, the through current in the driver unit 20 is slightly higher than in the case of FIG. 2, but the operation speed is slightly higher than in the case of FIG.
[0105]
FIG. 4 shows a case where the threshold voltage Vtp of the p-channel MOSFET 101 and the threshold voltage Vtn of the n-channel MOSFET 102 are relatively large. In this case, the potential VNP of the first node NP becomes lower than the potential VNN of the second node NN. As a result, the current flowing through the p-channel MOSFET 201 and the n-channel MOSFET 202 of the driver section 20 becomes relatively large. Therefore, although the through current in the driver unit 20 is relatively large, the operation speed is relatively high.
[0106]
FIG. 5 is a voltage waveform diagram showing an operation example of the level conversion circuit 1 of FIG. The operation example of FIG. 5 corresponds to the case of FIG. 4, in which the high level of the potential VNP of the first node NP is lower than the high level of the potential VNN of the second node NN, and the potential of the first node NP. The low level of VNP is higher than the low level of the potential VNN of the second node NN. In the operation example of FIG. 5, the through current in the driver unit 20 is relatively large, but the operation speed is high.
[0107]
As shown in FIG. 5, the potential VNP of the first node NP and the potential VNN of the second node NN change in phase. When the input signal CLK1 goes high and the input signal CLK2 goes low, the potential VNP of the first node NP and the potential VNN of the second node NN go high. As a result, the output potential VOUT becomes the ground potential GND.
[0108]
When the input signal CLK1 goes low and the input signal CLK2 goes high, the potential VNP of the first node NP and the potential VNN of the second node NN go low. As a result, the output potential VOUT becomes the power supply potential VDD.
[0109]
In the level conversion circuit 1 of the present embodiment, the degree of the ON state of the p-channel MOSFET 201 and the n-channel MOSFET 202, which are always on, is controlled, so that the voltage amplitude of the input signals CLK1, CLK2 is Operation is possible even when the threshold voltage is lower than the threshold voltage of the channel MOSFET 202. Further, even when the threshold voltages of the p-channel MOSFET 201 and the n-channel MOSFET 202 greatly deviate from the design values, a waveform of the output potential Vout corresponding to a change in the level of the input signals CLK1 and CLK2 can be obtained. As described above, even when the threshold voltages of the p-channel MOSFET 201 and the n-channel MOSFET 202 deviate from the design values due to variations in the manufacturing process, the operation can be reliably performed.
[0110]
Further, since the degree of the on-state of the p-channel MOSFET 201 and the n-channel MOSFET 202, which are always on, is controlled, high-speed operation is possible. Furthermore, since the transition period of the level of the output potential Vout is shortened by enabling high-speed operation, the period in which a through current flows is shortened. Thus, low power consumption can be achieved.
[0111]
Further, even if the voltage amplitude of the input signals CLK1 and CLK2 is small, a circuit for shifting the level is not required, so that the area can be reduced.
[0112]
FIG. 6 is a circuit diagram showing a first example of a circuit configuration of the level conversion circuit 1 of FIG.
As shown in FIG. 6, the control circuit 100 includes an n-channel MOSFET 103 and a p-channel MOSFET 104. The source of n-channel MOSFET 103 is connected to input node I1, and the drain and gate are connected to first node NP. The source of the p-channel MOSFET 104 is connected to the power supply terminal, the drain is connected to the second node NN, and the gate is connected to the input node I2.
[0113]
As described above, in the example of FIG. 6, the level conversion circuit 1 includes six MOSFETs. Therefore, the area can be reduced.
[0114]
Here, the threshold voltage of the p-channel MOSFET 101 is Vtp, and the threshold voltage of the n-channel MOSFET 102 is Vtn.
[0115]
In the manufacturing process, even if the threshold voltage of the p-channel MOSFET and the threshold voltage of the n-channel MOSFET vary from one level conversion circuit 1 to another, the p-channel MOSFETs 101, 104, The threshold voltages are the same, and the threshold voltages of the n-channel MOSFETs 102, 103, and 202 are the same.
[0116]
In the example of FIG. 6, the potential VNP of the first node NP is set by the p-channel MOSFET 101 to a level lower than the power supply potential VDD by the absolute value of the threshold voltage Vtp or more. Thereby, p-channel MOSFET 201 is always turned on. Further, the potential VNN of the second node NN is set to a level higher than the ground potential by the absolute value of the threshold voltage Vtn by the n-channel MOSFET 102. Thereby, n-channel MOSFET 202 is always turned on.
[0117]
The potential VNP of the first node NP is controlled to a high level or a low level by the n-channel MOSFET 103 according to the level of the input signal CLK1. Further, the potential VNN of the second node NN is controlled to a high level or a low level by the p-channel MOSFET 104 according to the level of the input signal CLK2. Thereby, one of the p-channel MOSFET 201 and the n-channel MOSFET 202 is turned on strongly, and the other is weakly turned on.
[0118]
FIG. 7 is a circuit diagram showing a second example of the circuit configuration of the level conversion circuit 1 of FIG.
7 differs from the level conversion circuit 1 of FIG. 6 in that the gate of the p-channel MOSFET 104 of the control circuit 100 is connected to the ground terminal. In this case, the p-channel MOSFET 104 is always on, and functions as a load resistance. Thereby, the n-channel MOSFET 202 of the driver section 20 is always on.
[0119]
The potential VNN of the second node NN is controlled to a high level or a low level according to the level of the input signal CLK1. Thereby, the n-channel MOSFET 202 is turned on strongly or weakly.
[0120]
The configuration and operation of the other parts of the level conversion circuit 1 of FIG. 7 are the same as those of the level conversion circuit 1 of FIG.
[0121]
FIG. 8 is a circuit diagram showing a third example of the circuit configuration of the level conversion circuit 1 of FIG.
The level conversion circuit 1 of FIG. 8 differs from the level conversion circuit 1 of FIG. 7 in that the control circuit 100 includes an n-channel MOSFET 105 instead of the p-channel MOSFET 104. The source of the n-channel MOSFET 105 is connected to the second node NN, and the drain and the gate are connected to a power supply terminal. In this case, the n-channel MOSFET 105 is always on, and functions as a load resistance. Thereby, the n-channel MOSFET 202 of the driver section 20 is always on.
[0122]
The potential VNN of the second node NN is controlled to a high level or a low level according to the level of the input signal CLK1. Thereby, the n-channel MOSFET 202 is turned on strongly or weakly.
[0123]
The configuration and operation of the other parts of the level conversion circuit 1 of FIG. 8 are the same as those of the level conversion circuit 1 of FIG.
[0124]
FIG. 9 is a circuit diagram showing a fourth example of the circuit configuration of the level conversion circuit 1 of FIG.
9 is different from the level conversion circuit 1 in FIG. 6 in that the source of the n-channel MOSFET 102 is connected to the ground terminal. In this case, the potential VNN of the second node NN is set to a level higher than the ground potential by the absolute value of the threshold voltage Vtn by the n-channel MOSFET 102. Thereby, the n-channel MOSFET 202 of the driver section 20 is always on.
[0125]
The potential VNN of the second node NN is controlled to a high level or a low level by the p-channel MOSFET 104 according to the level of the input signal CLK2. Thereby, the n-channel MOSFET 202 is turned on strongly or weakly.
[0126]
The configuration and operation of the other parts of the level conversion circuit 1 of FIG. 9 are the same as those of the level conversion circuit 1 of FIG.
[0127]
FIG. 10 is a circuit diagram showing a fifth example of the circuit configuration of the level conversion circuit 1 of FIG. The level conversion circuit 1 of FIG. 10 differs from the level conversion circuit 1 of FIG. 6 in that the gate of the n-channel MOSFET 103 of the control circuit 100 is connected to the power supply terminal. In this case, the n-channel MOSFET 103 is always on, and functions as a load resistance. Thereby, the potential VNP of the first node NP is controlled to a high level or a low level according to the level of the input signal CLK1. Therefore, the p-channel MOSFET 201 of the driver section 20 is turned on strongly or weakly.
[0128]
The configuration and operation of the other parts of the level conversion circuit 1 of FIG. 10 are the same as those of the level conversion circuit 1 of FIG.
[0129]
FIG. 11 is a circuit diagram showing a sixth example of the circuit configuration of the level conversion circuit 1 of FIG. The level conversion circuit 1 in FIG. 11 differs from the level conversion circuit 1 in FIG. 6 in that the control circuit 100 is configured by resistance elements R1 and R2. One end of resistance element R1 is connected to first node NP, and the other end is connected to input node I1. One end of the resistance element R2 is connected to the power supply terminal, and the other end is connected to the second node NN. In this case, the potential VNP of the first node NP is controlled to a high level or a low level according to the level of the input signal CLK1, and the potential VNN of the second node NN is controlled to a high level or a low level.
[0130]
The configuration and operation of the other parts of the level conversion circuit 1 of FIG. 11 are the same as those of the level conversion circuit 1 of FIG.
[0131]
FIG. 12 is a circuit diagram showing the configuration of the level conversion circuit according to the second embodiment of the present invention.
[0132]
The level conversion circuit 1 of FIG. 12 differs from the level conversion circuit 1 of FIG. 1 in that the source of the n-channel MOSFET 202 of the driver unit 20 is connected to the ground terminal.
[0133]
Also in the level conversion circuit 1 of the present embodiment, the potential VNN of the second node NN is set to a level higher than the low level of the input signal CLK1 by the absolute value of the threshold voltage Vtn of the n-channel MOSFET 102.
[0134]
When the input signal CLK1 is at the low level, the potential VNN of the second node NN becomes a level raised from the low level by the absolute value of the threshold voltage Vtn. At this time, the source of the n-channel MOSFET 202 is at the ground potential. Thereby, the n-channel MOSFET 202 turns on weakly. When the input signal CLK1 is at a high level, the potential VNN of the second node NN becomes a level raised from the high level by the absolute value of the threshold voltage Vtn. At this time, the source of the n-channel MOSFET 202 is at the ground potential. Thereby, the n-channel MOSFET 202 turns on strongly.
[0135]
The configuration and operation of the other parts of the level conversion circuit 1 of the second embodiment are the same as those of the level conversion circuit 1 of the first embodiment.
[0136]
FIG. 13 is a circuit diagram showing a configuration of a level conversion circuit according to the third embodiment of the present invention.
[0137]
The level conversion circuit 1 of FIG. 13 differs from the level conversion circuit 1 of FIG. 1 in that the source of the n-channel MOSFET 202 of the driver unit 20 is connected to a power supply terminal receiving the negative potential Vee.
[0138]
Also in the level conversion circuit 1 of the present embodiment, the potential VNN of the second node NN is set to a level higher than the low level of the input signal CLK1 by the absolute value of the threshold voltage Vtn of the n-channel MOSFET 102.
[0139]
When the input signal CLK1 is at the low level, the potential VNN of the second node NN becomes a level raised from the low level by the absolute value of the threshold voltage Vtn. At this time, the source of the n-channel MOSFET 202 is at the negative potential Vee. Thereby, the n-channel MOSFET 202 turns on weakly. When the input signal CLK1 is at a high level, the potential VNN of the second node NN becomes a level raised from the high level by the absolute value of the threshold voltage Vtn. At this time, the source of the n-channel MOSFET 202 is at the negative potential Vee. Thereby, the n-channel MOSFET 202 turns on strongly.
[0140]
The configuration and operation of the other parts of the level conversion circuit 1 of the third embodiment are the same as those of the level conversion circuit 1 of the first embodiment.
[0141]
FIG. 14 is a circuit diagram showing a configuration of a level conversion circuit according to the fourth embodiment of the present invention.
[0142]
In the level conversion circuit 1 of FIG. 14, the control unit 10 includes a control circuit 100a and an n-channel MOSFET 102. Control circuit 100a is connected to input nodes I1 and I2, first node NP, and second node NN. Input signals CLK1 and CLK2 are applied to input nodes I1 and I2, respectively, as in level conversion circuit 1 of the first embodiment.
[0143]
The source of the n-channel MOSFET 102 is connected to the input node I1, and the drain and the gate are connected to the second node NN. The configuration of the other parts of the level conversion circuit 1 of FIG. 14 is the same as the configuration of the level conversion circuit 1 of FIG.
[0144]
Control circuit 100a controls potential VNP of first node NP and potential VNN of second node NN in response to input signals CLK1 and CLK2. The potential VNP of the first node NP is set to a level between the power supply potential VDD and the level of the input signal CLK1 by the control circuit 100a. Further, the potential VNN of the second node NN is set to a level higher than the low level of the input signal CLK1 by the absolute value of the threshold voltage Vtn of the n-channel MOSFET 102 or more.
[0145]
Thereby, one of the p-channel MOSFET 201 and the n-channel MOSFET 202 of the driver section 20 is turned on strongly and the other is weakly turned on. As described above, one of the p-channel MOSFET 201 and the n-channel MOSFET 202 of the driver section 20 is not completely turned off.
[0146]
The configuration and operation of the other parts of the level conversion circuit 1 of the fourth embodiment are the same as those of the level conversion circuit 1 of the first embodiment.
[0147]
FIG. 15 is a circuit diagram showing a first example of a circuit configuration of the level conversion circuit 1 of FIG.
[0148]
As shown in FIG. 15, control circuit 100a includes resistance elements R3, R4 and p-channel MOSFET 104. One end of the resistance element R3 is connected to the power supply terminal, and the other end is connected to the first node NP. One end of resistance element R4 is connected to first node NP, and the other end is connected to input node I1. The source of the p-channel MOSFET 104 is connected to the power supply terminal, the drain is connected to the second node NN, and the gate is connected to the input node I2.
[0149]
In the example of FIG. 15, the potential VNP of the first node NP is set to a level between the power supply potential VDD and the level of the input signal CLK1 by the resistance elements R3 and R4. Thereby, p-channel MOSFET 201 is always turned on. Further, the potential VNN of the second node NN is set to a level higher than the ground potential by the absolute value of the threshold voltage Vtn by the n-channel MOSFET 102. Thereby, n-channel MOSFET 202 is always turned on.
[0150]
The potential VNP of the first node NP is controlled to a high level or a low level according to the level of the input signal CLK1. In addition, the potential VNN of the second node NN is controlled to a high level or a low level according to the levels of the input signals CLK1 and CLK2. Thereby, one of the p-channel MOSFET 201 and the n-channel MOSFET 202 is turned on strongly, and the other is weakly turned on.
[0151]
When the input signal CLK1 is at the high level, the potential VNP of the first node NP is set to a level between the power supply potential VDD and the high level of the input signal CLK1. Thereby, the p-channel MOSFET 201 is weakly turned on. At this time, the n-channel MOSFET 202 turns on strongly.
[0152]
When the input signal CLK1 is at the low level, the potential VNP of the first node NP is set to a level between the power supply potential VDD and the low level of the input signal CLK1. Thereby, p-channel MOSFET 201 is strongly turned on. At this time, the n-channel MOSFET 202 turns on strongly.
[0153]
FIG. 16 is a circuit diagram showing a second example of the circuit configuration of the level conversion circuit 1 of FIG.
[0154]
The level conversion circuit 1 of FIG. 16 differs from the level conversion circuit 1 of FIG. 15 in that the other end of the resistance element 4 of the control circuit 100a is connected to the ground terminal.
[0155]
In this case, the potential VNN of the first node NP is fixed to a predetermined potential between the power supply potential VDD and the ground potential by the resistance elements R3 and R4. Thereby, p-channel MOSFET 202 is always on.
[0156]
When the n-channel MOSFET 202 is strongly turned on, the p-channel MOSFET 201 is weakly turned on, and when the n-channel MOSFET 202 is weakly turned on, the p-channel MOSFET 201 is strongly turned on.
[0157]
FIG. 17 is a circuit diagram showing a third example of the circuit configuration of the level conversion circuit 1 of FIG.
[0158]
The level conversion circuit 1 of FIG. 17 differs from the level conversion circuit 1 of FIG. 15 in that a p-channel MOSFET 106 is provided instead of the resistance element R3 of the control circuit 100a. The source of the p-channel MOSFET 106 is connected to the power supply terminal, the drain is connected to the first node NP, and the gate is connected to the input node I1.
[0159]
When the input signal CLK1 is at a high level, the potential VNP of the first node NP is at a high level. Thereby, the p-channel MOSFET 201 is weakly turned on. When the input signal CLK1 is at a low level, the potential VNP of the first node NP is at a low level. Thereby, p-channel MOSFET 201 is strongly turned on.
[0160]
The level conversion circuits 1 of the first to fourth embodiments operate in response to input signals CLK1 and CLK2 that change complementarily to each other, but the level conversion circuit 1 of the fifth embodiment described below has a single input. Operate in response to a signal.
[0161]
FIG. 18 is a circuit diagram showing a configuration of a level conversion circuit according to the fifth embodiment of the present invention.
[0162]
18, the source of n-channel MOSFET 103 of control circuit 100 is connected to input node I1 receiving a single input signal CLK, and the drain and gate are connected to first node NP. The source of the p-channel MOSFET 104 is connected to the power supply terminal, the drain is connected to the second node NN, and the gate is connected to the ground terminal. The source of the n-channel MOSFET 202 of the driver section 20 is connected to a ground terminal.
[0163]
The configuration of the other parts of the level conversion circuit 1 of FIG. 18 is the same as the configuration of the level conversion circuit 1 of FIG.
[0164]
FIG. 19 is a circuit diagram showing the configuration of the level conversion circuit according to the sixth embodiment of the present invention.
[0165]
In the level conversion circuit 1 of FIG. 19, the configuration of the control unit 10 is the same as the configuration of the control unit 10 of the level conversion circuit 1 of FIG. In the driver section 20, a p-channel MOSFET 210 is connected between the source of the p-channel MOSFET 201 and a power supply terminal. Control signal CONT is applied to the gate of p-channel MOSFET 210. The configuration of the other parts of the level conversion circuit 1 of FIG. 19 is the same as the configuration of the level conversion circuit 1 of FIG.
[0166]
FIG. 20 is a voltage waveform diagram showing an operation example of the level conversion circuit 1 of FIG.
As shown in FIG. 20, input signals CLK1 and CLK2 change to a high level and a low level complementarily to each other. The output potential VOUT changes with a voltage amplitude larger than the voltage amplitude of the input signals CLK1 and CLK2.
[0167]
The control signal CONT is at a high level during a period during which the input signals CLK1 and CLK2 transition between a high level and a low level, and at a low level during other periods.
[0168]
A period in which the control signal CONT is at a high level is referred to as a through current blocking period TH. During the through current blocking period TH, the p-channel MOSFET 210 is turned off. Thereby, a through current flowing from the power supply terminal through the p-channel MOSFET 201 and the n-channel MOSFET 202 is prevented. Therefore, low power consumption can be achieved.
[0169]
Here, a simulation of the characteristics of the level conversion circuit according to the present invention was performed. FIG. 21 is a diagram showing a circuit configuration of the level conversion circuit used for the simulation. The configuration of the level conversion circuit 1 in FIG. 21 is the same as the configuration of the level conversion circuit 1 shown in FIG. First, the high speed operation of the level conversion circuit 1 of FIG. 21 was examined.
[0170]
Generally, in a transistor made of bulk silicon, the threshold voltage Vtp is, for example, (-0.9 ± 0.1) V, and the threshold voltage Vtn is, for example, (0.7 ± 0.1) V. On the other hand, in a thin film transistor using polycrystalline silicon, the threshold voltage Vtp is, for example, (−2.5 ± 1 to 1.5) V, and the threshold voltage Vtn is, for example, (1.8 ± 1 to 1.. 5) V. As described above, in a thin film transistor using polycrystalline silicon, variation in threshold voltage in a manufacturing process is larger than that in a transistor including bulk silicon.
[0171]
FIG. 22 is a diagram showing a simulation result when the level conversion circuit 1 is configured by a transistor made of bulk silicon.
[0172]
The frequency of the input signals CLK1 and CLK2 was 1 GHz, the input voltage amplitude (the amplitude of the input signals CLK1 and CLK2) was 0.5 V, and the output voltage amplitude (the amplitude of the output potential VOUT) was 3.0 V.
[0173]
FIG. 22A shows the waveforms of the input signals CLK1 and CLK2 and the output potential VOUT, and FIG. 22B shows the potential VNP of the first node NP, the potential VNN of the second node NN, and the output potential of the output node NO. 4 shows a waveform of Vout.
[0174]
From the simulation results of FIG. 22, it is understood that an output potential VOUT having a duty ratio of 50% can be obtained in response to the input signals CLK1 and CLK2 even at a frequency as high as 1 GHz. Thus, high-speed operation is possible in the level conversion circuit 1 configured by transistors made of bulk silicon.
[0175]
FIG. 23 is a diagram showing a simulation result when the level conversion circuit 1 is configured by a thin film transistor made of polycrystalline silicon.
[0176]
The frequencies of the input signals CLK1 and CLK2 were set to 20 MHz, the input voltage amplitude was set to 3.0 V, and the output voltage amplitude was set to 12 V.
[0177]
FIG. 23A shows the waveforms of the input signals CLK1 and CLK2 and the output potential VOUT, and FIG. 23B shows the potential VNP of the first node NP, the potential VNN of the second node NN, and the output potential of the output node NO. 4 shows a waveform of Vout.
[0178]
From the simulation results of FIG. 23, it is understood that an output potential VOUT having a duty ratio of 50% can be obtained in response to the input signals CLK1 and CLK2 even at a high frequency of 20 MHz. As described above, high-speed operation is possible even in the level conversion circuit 1 constituted by the thin film transistors made of polycrystalline silicon.
[0179]
Next, a voltage waveform simulation was performed when the threshold voltages of the p-channel MOSFET and the n-channel MOSFET of the level conversion circuit 1 varied. In this simulation, a thin film transistor made of polycrystalline silicon was used as the p-channel MOSFET and the n-channel MOSFET of the level conversion circuit 1. The frequency of the input signals CLK1 and CLK2 was 2 MHz.
[0180]
FIG. 24 is a diagram showing simulation results when the threshold voltages of the p-channel MOSFET and the n-channel MOSFET are smaller than the set values. In the simulation of FIG. 24, the threshold parameter (threshold voltage) of the p-channel MOSFET was -2.0 V, and the threshold parameter (threshold voltage) of the n-channel MOSFET was 1.3 V.
[0181]
FIG. 25 is a diagram showing simulation results when the threshold voltages of the p-channel MOSFET and the n-channel MOSFET are set values. In the simulation of FIG. 25, the threshold parameter of the p-channel MOSFET was -3.5 V, and the threshold parameter of the n-channel MOSFET was 2.8 V.
[0182]
FIG. 26 is a diagram showing simulation results when the threshold voltages of the p-channel MOSFET and the n-channel MOSFET are higher than the set values. In the simulation of FIG. 26, the threshold parameter of the p-channel MOSFET was -5.0 V, and the threshold parameter of the n-channel MOSFET was 4.3 V.
[0183]
24, 25 and 26 that the duty ratio is 50% in response to the input signals CLK1 and CLK2 even when the threshold parameters of the p-channel MOSFET and the n-channel MOSFET deviate relatively greatly from the set values. It can be seen that the output potential VOUT is obtained.
[0184]
FIG. 27 is a circuit diagram showing the configuration of the level conversion circuit according to the seventh embodiment of the present invention.
[0185]
The level conversion circuit 1a in FIG. 27 includes two control units 10A and 10B, two driver units 20A and 20B, and one PMOS cross-coupled differential amplifier 30.
[0186]
The configurations of the control units 10A and 10B and the driver units 20A and 20B are the same as the configurations of the control unit 10 and the driver unit 20 in the first to sixth embodiments. However, input signals CLK1 and CLK2 are applied to input nodes I1 and I2 of control unit 10A, respectively, and input signals CLK2 and CLK1 are applied to input nodes I1 and I2 of control unit 10B, respectively.
[0187]
A predetermined potential VEE is applied to the sources of the n-channel MOSFETs 303 of the driver units 20A and 20B. The predetermined potential VEE is a positive potential, a ground potential, a negative potential, a clock signal CLK1 or a clock signal CLK2 lower than the power supply potential VDD.
[0188]
Differential amplifier 30 includes p-channel MOSFETs 301 and 302 and n-channel MOSFETs 303 and 304. The sources of the p-channel MOSFETs 301 and 302 are connected to the power supply terminals, the drains are connected to the output nodes NO1 and NO2, respectively, and the gates are cross-connected to the output nodes NO2 and NO1. Predetermined potential VEE is applied to the sources of n-channel MOSFETs 303 and 304, the drains are connected to output nodes NO1 and NO2, respectively, and the gates are connected to output nodes NOA and NOB of driver sections 20A and 20B, respectively.
[0189]
In the level conversion circuit 1a of this embodiment, output potentials VOUT1 and VOUT2 that change complementarily with each other are output from output nodes NO1 and NO2 of the differential amplifier 30. The output potentials VOUT1 and VOUT2 change between the power supply potential VDD and the ground potential.
[0190]
FIG. 28 is a circuit diagram showing a specific configuration example of the level conversion circuit 1a of FIG. 28, the configurations of the control units 10A and 10B are the same as the configuration of the control unit 10 shown in FIG. The sources of the n-channel MOSFETs 202 of the driver sections 20A and 20B are connected to the input node I2. The sources of the n-channel MOSFETs 303 and 304 of the differential amplifier 30 are connected to a ground terminal.
[0191]
FIG. 29 is a circuit diagram showing the configuration of the level conversion circuit according to the eighth embodiment of the present invention.
[0192]
The level conversion circuit 1b in FIG. 29 differs from the level conversion circuit 1a in FIG. 27 in that a current mirror type amplifier 31 is connected instead of the PMOS cross-coupled differential amplifier 30.
[0193]
Current mirror type amplifier 31 includes p-channel MOSFETs 311, 312 and n-channel MOSFETs 313, 314. The sources of the p-channel MOSFETs 311 and 312 are connected to the power supply terminals, the drains are connected to the output nodes NO3 and NO4, respectively, and the gates are connected to the output node NO3. Predetermined potential VEE is applied to the sources of n-channel MOSFETs 313 and 314, the drains are connected to output nodes NO3 and NO4, respectively, and the gates are connected to output nodes NO1 and NO2 of driver sections 20A and 20B, respectively.
[0194]
In the level conversion circuit 1b of the present embodiment, the output potential VOUT is output from the output node NO4 of the current mirror type amplifier 31. The output potential VOUT changes between the power supply potential VDD and the ground potential.
FIG. 30 is a circuit diagram showing the configuration of the level conversion circuit according to the ninth embodiment of the present invention.
[0195]
In the level conversion circuit 1c of FIG. 30, a plurality of PMOS cross-coupled differential amplifiers 30 are connected between output nodes NOA and NOB of the driver sections 20A and 20B. The configuration of the other parts of the level conversion circuit 1c in FIG. 30 is the same as the configuration of the level conversion circuit 1a in FIG.
[0196]
In the level conversion circuit 1c of this embodiment, output potentials VOUT1 and VOUT2 that change complementarily with each other are output from output nodes NO1 and NO2 of the plurality of differential amplifiers 30. The output potentials VOUT1 and VOUT2 change between the power supply potential VDD and the ground potential.
[0197]
FIG. 31 is a circuit diagram showing the configuration of the level conversion circuit according to the tenth embodiment of the present invention. The level conversion circuit 1d in FIG. 31 is a pair type level conversion circuit.
[0198]
The level conversion circuit 1d in FIG. 31 includes two control units 10A and 10B, two driver units 20A and 20B, and two inverters 3A and 3B.
[0199]
The configuration of the control units 10A and 10B is the same as the configuration of the control unit 10 shown in FIG. 6, and the configuration of the driver units 20A and 20B is the same as the configuration of the driver unit 20 shown in FIG. The gate of the p-channel MOSFET 104 of the control unit 10A, the source of the n-channel MOSFET 202 of the driver unit 20A, the source of the n-channel MOSFET 102 of the control unit 10B, and the source of the n-channel MOSFET 103 of the control unit 10B are connected to the input node IA that receives the clock signal CLK1. Connected. The source of the n-channel FET 102 of the control unit 10A, the source of the n-channel MOSFET 103 of the control unit 10A, the gate of the p-channel MOSFET 104 of the control unit 10B, and the source of the n-channel MOSFET 202 of the driver unit 20B are connected to the input node IB that receives the clock signal CLK2. Connected.
[0200]
Inverters 3A and 3B are connected to output nodes NOA and NOB of driver sections 20A and 20B, respectively. Inverters 3A and 3B output output potentials VOUT1 and VOUT2 that change complementarily to each other. The output potentials VOUT1 and VOUT2 change between the power supply potential VDD and the ground potential. Thus, the level conversion circuit 1d of FIG. 31 performs a complementary operation.
[0201]
FIG. 32 is a circuit diagram showing the configuration of the level conversion circuit according to the eleventh embodiment of the present invention. The level conversion circuit 1e in FIG. 32 is a pair type and phase adjustment type level conversion circuit.
[0202]
The level conversion circuit 1e of FIG. 32 is different from the level conversion circuit 1d of FIG. 31 in that a pair of inverters 5A and 5B for phase adjustment are provided between the output node NOA of the driver 20A and the output node NOB of the driver 20B. That is, they are connected in opposite directions.
[0203]
In the level conversion circuit 1e of the present embodiment, the phases of the output potentials of the output nodes NOA and NOB can be matched by the inverters 5A and 5B. Thereby, even if the variation in the threshold voltage of the MOSFET in the manufacturing process is large, the phase shift of the output potentials VOUT1 and VOUT2 is reduced.
[0204]
FIG. 33 is a circuit diagram showing a configuration of a level conversion circuit according to a twelfth embodiment of the present invention. The level conversion circuit 1f in FIG. 33 is a low voltage drive type level conversion circuit.
[0205]
33 is different from level conversion circuit 1 in FIG. 6 in that control section 10 further includes p-channel MOSFET 105 and n-channel MOSFET 106.
[0206]
The source of the p-channel MOSFET 105 is connected to the power supply terminal, the gate is connected to the output node NO, and the drain is connected to the first node NP. The source of the n-channel MOSFET 106 is connected to the input node I1, the gate is connected to the output node NO, and the drain is connected to the second node NN.
[0207]
As described above, in the level conversion circuit 1 of FIG. 6, the gate potentials of the p-channel MOSFET 201 and the n-channel MOSFET 202 of the driver unit 20 are adjusted by the threshold voltage Vtp of the p-channel MOSFET 101 of the control unit 10 and the potential of the n-channel MOSFET 102. The operation is shifted to the operation region by the threshold voltage Vtn. Thus, even when the threshold voltage of the MOSFET deviates from the design value due to a variation in the manufacturing process, the p-channel MOSFET 201 and the n-channel MOSFET 202 can operate reliably. However, when the power supply potential VDD decreases and the threshold voltage shifts to become larger than the design value due to a variation in the manufacturing process, the p-channel MOSFET 201 and the n-channel MOSFET 202 of the driver unit 20 do not operate. Can occur.
[0208]
Therefore, in the level conversion circuit 1f of the present embodiment, in order to avoid this, the p-channel MOSFET 105 and the n-channel MOSFET 106 are provided. As described above, the range that the output potential Vout of the output node NO can take is larger than the range that the potential VNP of the first node NP can take and the range that the potential VNN of the second node NN can take. That is, the range in which the output potential Vout of the output node NO can take is larger than the range in which the gate potential of the p-channel MOSFET 101 and the gate potential of the n-channel MOSFET 102 can take. As a result, the gate potential of the p-channel MOSFET 105 and the gate potential of the n-channel MOSFET 106 fluctuate in a range larger than the potential VNP of the first node NP and the potential VNN of the second node NN. Therefore, the p-channel MOSFET 105 and the n-channel MOSFET 106 turn on more strongly. As a result, the potential VNP of the first node NP and the potential VNN of the second node NN are not affected by the threshold voltages of the p-channel MOSFET 101 and the n-channel MOSFET 102. Therefore, the level conversion circuit 1f in FIG. 33 can operate reliably even when the power supply potential VDD is low and the variation in the manufacturing process is large.
[0209]
FIG. 34 is a circuit diagram showing the configuration of the level conversion circuit according to the thirteenth embodiment of the present invention. The level conversion circuit 1g in FIG. 34 is a low voltage drive type and pair type level conversion circuit.
[0210]
34 is different from level conversion circuit 1d in FIG. 31 in that control unit 10A further includes p-channel MOSFET 105A and n-channel MOSFET 106A, and control unit 10B further includes p-channel MOSFET 105B and n-channel MOSFET 106B. It is. That is, the control units 10A and 10B have the same configuration as the control unit 10 shown in FIG.
[0211]
In the level conversion circuit 1g of this embodiment, output potentials VOUT1 and VOUT2 that change complementarily to each other are output from the inverters 3A and 3B, similarly to the level conversion circuit 1d of FIG. The output potentials VOUT1 and VOUT2 change between the power supply potential VDD and the ground potential. The level conversion circuit 1g can operate reliably even when the power supply potential VDD is low and the variation in the manufacturing process is large, similarly to the level conversion circuit 1f in FIG.
[0212]
FIG. 35 is a circuit diagram showing the configuration of the level conversion circuit according to the fourteenth embodiment of the present invention. The level conversion circuit 1h in FIG. 35 is a low voltage drive type, pair type and phase adjustment type level conversion circuit.
[0213]
The level conversion circuit 1h of FIG. 35 is different from the level conversion circuit 1g of FIG. 34 in that a pair of inverters 5A and 5B for phase adjustment are provided between the output node NOA of the driver unit 20A and the output node NOB of the driver unit 20B. That is, they are connected in opposite directions.
[0214]
In the level conversion circuit 1h of the present embodiment, the phase shift of the output potentials VOUT1 and VOUT2 is reduced even when the variation in the threshold voltage of the MOSFET in the manufacturing process is large. Further, even when the power supply potential VDD is low, the operation can be reliably performed.
[0215]
FIG. 36 is a block diagram showing a first example of a semiconductor device using the level conversion circuit of the present invention.
[0216]
In the semiconductor device of FIG. 36, a logic circuit 501 operating at a power supply voltage of 2.5 V, a logic circuit 502 operating at a power supply voltage of 3.3 V, and a level conversion circuit 10A are mounted on a chip 500 in a mixed manner. The level conversion circuit 10A converts the level of the 2.5 V system signal supplied from the logic circuit 501 into a 3.3 V system signal, and supplies the converted signal to the logic circuit 502.
[0217]
Any of the level conversion circuits 1 and 1a to 1h of the first to fourteenth embodiments is used as the level conversion circuit 1A. Thereby, the semiconductor device of FIG. 36 can operate reliably even when the threshold voltage of the p-channel MOSFET and the n-channel MOSFET greatly varies in the manufacturing process, and can operate at high speed, reduce power consumption, and reduce the size. The area can be increased.
[0218]
FIG. 37 is a block diagram showing a second example of a semiconductor device using the level conversion circuit of the present invention.
[0219]
In the semiconductor device of FIG. 37, a logic circuit 511 operating at a power supply voltage of 1.2 V, a logic circuit 512 operating at a power supply voltage of 1.8 V, and logic circuits 513 and 514 operating at a power supply voltage of 2.5 V are provided on a chip 510. And the level conversion circuits 1B, 1C, and 1D.
[0220]
The level conversion circuit 1 </ b> B converts the level of a 1.2 V-system signal supplied from the logic circuit 511 into a 1.8 V-system signal, and provides the same to the logic circuit 512. The level conversion circuit 1 </ b> C converts the level of a 1.8 V-system signal supplied from the logic circuit 512 into a 2.5 V-system signal, and supplies the converted signal to the logic circuit 514. The level conversion circuit 1 </ b> D converts the level of a 1.2 V-system signal supplied from the logic circuit 511 to a 2.5 V-system signal, and supplies the signal to the logic circuit 513.
[0221]
Any of the level conversion circuits 1 and 1a to 1h of the first to fourteenth embodiments is used as the level conversion circuits 1B, 1C and 1D. Accordingly, the semiconductor device of FIG. 37 can operate reliably even when the threshold voltage of the p-channel MOSFET and the n-channel MOSFET greatly varies in the manufacturing process, and can operate at high speed, reduce power consumption, and reduce power consumption. The area can be increased.
[0222]
FIG. 38 is a block diagram showing a third example of a semiconductor device using the level conversion circuit of the present invention.
[0223]
In the semiconductor device of FIG. 38, a semiconductor memory 521 operating at a power supply voltage of 1.8 V, a logic circuit 522 operating at a power supply voltage of 3.3 V, and a level conversion circuit 1E are mounted on a chip 520. The semiconductor memory 521 is a DRAM (dynamic random access memory), an SRAM (static random access memory), a FLASH (flash memory), a FERAM (ferroelectric memory), or the like. The level conversion circuit 1E converts a 1.8V-system signal supplied from the semiconductor memory 521 into a 3.3V-system signal, and supplies the same to the logic circuit 522.
[0224]
Any of the level conversion circuits 1 and 1a to 1h of the first to fourteenth embodiments is used as the level conversion circuit 1E. Thereby, the semiconductor device of FIG. 38 can operate reliably even when the threshold voltage of the p-channel MOSFET and the n-channel MOSFET greatly varies in the manufacturing process, and can operate at high speed, reduce power consumption, and reduce the area. Is possible.
[0225]
FIG. 39 is a block diagram showing a fourth example of a semiconductor device using the level conversion circuit of the present invention.
[0226]
In the semiconductor device of FIG. 39, an internal circuit 531 operating at a power supply voltage of 2.5 V is formed inside a chip 530. The internal circuit 531 includes a semiconductor element. The level conversion circuit 1F converts the level of the 2.5V-system signal supplied from the internal circuit 531 into a 3.3V-system signal, and supplies the same to an external circuit 532 operating at a power supply voltage of 3.3V.
[0227]
Any of the level conversion circuits 1 and 1a to 1h of the first to fourteenth embodiments is used as the level conversion circuit 1F. Thereby, the semiconductor device in FIG. 39 can operate reliably even when the threshold voltage of the p-channel MOSFET and the n-channel MOSFET greatly varies in the manufacturing process, and can operate at high speed, with low power consumption, and The area can be reduced.
[0228]
FIG. 40 is a block diagram showing an example of a liquid crystal display device using the level conversion circuit of the present invention.
[0229]
In the liquid crystal display device of FIG. 40, a plurality of scan electrodes Y1, Y2,..., Yn and a plurality of data electrodes X1, X2,. Here, n and m are each an arbitrary integer. At intersections between the plurality of scan electrodes Y1 to Yn and the plurality of data electrodes X1 to Xm, liquid crystal elements 542 are provided via thin film transistors 541, respectively. The thin film transistor 541 is formed using, for example, polycrystalline silicon obtained by polycrystallizing amorphous silicon by a laser annealing method.
[0230]
Further, a scanning line driver circuit 543, a data driver circuit 544, and a voltage conversion circuit 600 are provided over the glass substrate 540. The scanning electrodes Y1 to Yn are connected to a scanning line driving circuit 543, and the data electrodes X1 to Xm are connected to a data driving circuit 544. The voltage conversion circuit 600 converts the levels of the basic clock signals of small amplitudes, which change complementarily to each other, supplied from the external control circuit 545 to clock signals of different voltages, and supplies the clock signals to the scanning line driving circuit 543 and the data driving circuit 544.
[0231]
FIG. 41 is a block diagram showing a configuration of a voltage conversion circuit used in the liquid crystal display device of FIG.
[0232]
In the voltage conversion circuit 600 of FIG. 41, a boost power supply circuit 601, a negative power supply circuit 602, and level conversion circuits 1G, 1H, 1I, and 1J are formed on a glass substrate 540. External power supply voltages of 8 V and 3.3 V are applied to level conversion circuit 1G. Here, the internal circuits are the scanning line driving circuit 543 and the data driving circuit 544 in FIG.
[0233]
The level conversion circuit 1G converts the level of the basic clock signal supplied from the external control circuit 545 in FIG. 40 into a signal that changes in the range of 0 V to 8 V, and supplies the signal to the internal circuit and the level conversion circuits 1H, 1I, and 1J. The level conversion circuit 1H converts the level of the signal supplied from the level conversion circuit 1G into a signal that changes in the range of 0 to 12 V based on the power supply voltage of the boost power supply circuit 601, and supplies the signal to the internal circuit and the level conversion circuit 1J.
[0234]
The level conversion circuit 1I converts the level of the signal supplied from the level conversion circuit 1G into a signal that changes in the range of -3V to 8V based on the negative power supply voltage of the negative power supply circuit 602, and supplies the signal to the internal circuit. The level conversion circuit 1J converts the signal supplied from the level conversion circuit 1H into a signal that changes in a range from -3V to 12V based on the negative power supply voltage of the negative power supply circuit 602, and supplies the signal to an internal circuit.
[0235]
Any of the level conversion circuits 1 and 1a to 1h of the first to fourteenth embodiments is used as the level conversion circuits 1G, 1H, 1I and 1J. Thereby, the liquid crystal display device of FIG. 40 can operate reliably even when the threshold voltage of the p-channel MOSFET and the n-channel MOSFET greatly varies in the manufacturing process, and can operate at high speed and with low power consumption. Small area and high definition can be achieved.
[0236]
FIG. 42 is a block diagram showing an example of an organic EL device using the level conversion circuit of the present invention.
[0237]
In the organic EL device of FIG. 42, a plurality of scan electrodes Y1, Y2,... Yn and a plurality of data electrodes X1, X2,. An organic EL element 552 is provided at an intersection of the plurality of scan electrodes Y1 to Yn and the plurality of data electrodes X1 to Xm via a thin film transistor 551. The thin film transistor 551 is formed using, for example, polycrystalline silicon obtained by polycrystallizing amorphous silicon by a laser annealing method.
[0238]
Further, a scanning line driver circuit 553, a data driver circuit 554, and a voltage conversion circuit 700 are provided over the glass substrate 550. The scanning electrodes Y1 to Yn are connected to a scanning line driving circuit 553, and the data electrodes X1 to Xm are connected to a data driving circuit 554. The voltage converting circuit 700 converts the levels of the basic clock signals having small amplitudes, which change complementarily to each other, supplied from the external control circuit 555 to clock signals having different voltages, and supplies the clock signals to the scanning line driving circuit 553 and the data driving circuit 554. The configuration of voltage conversion circuit 700 is similar to the configuration of voltage conversion circuit 600 shown in FIG.
[0239]
Any one of the level conversion circuits 1 and 1a to 1h of the first to fourteenth embodiments is used for the voltage conversion circuit 700. Thereby, the organic EL device of FIG. 42 can operate reliably even when the variation in the threshold voltage of the p-channel MOSFET and the n-channel MOSFET in the manufacturing process is large, while achieving high-speed operation, low power consumption, Small area and high definition can be achieved.
[0240]
FIG. 43 is a cross-sectional view showing an example in which the level conversion circuit of the present invention is constituted by an SOI (Silicon on Insulator) device.
[0241]
In the SOI device in FIG. 43, an insulating film 571 is formed over a Si (silicon) substrate 570, and an amorphous, polycrystalline, or single-crystal silicon layer 572 is formed over the insulating film 571. In the silicon layer 572, a plurality of pairs of p-type regions 573 and a plurality of pairs of n-type regions 574 are formed.
[0242]
A gate electrode 575 is formed on a region between each pair of p-type regions 573 and on a region between each pair of n-type regions 574. Thus, the SOI device constitutes, for example, the level conversion circuit 1 of FIG.
[0243]
Note that the level conversion circuit of the present invention is not limited to an SOI device, and can be formed by various semiconductor elements.
[0244]
FIG. 44 is a block diagram showing an example of a sensor device using the level conversion circuit of the present invention.
[0245]
In the sensor device of FIG. 44, a plurality of scan electrodes Y1, Y2,... Yn and a plurality of data electrodes X1, X2,. Note that a panel substrate made of plastic or the like may be used instead of the glass substrate 580. A sensor 582 is provided at an intersection of the plurality of scan electrodes Y1 to Yn and the plurality of data electrodes X1 to Xm via a thin film transistor 581. The thin film transistor 581 is formed using, for example, polycrystalline silicon obtained by polycrystallizing amorphous silicon by a laser annealing method.
[0246]
As the sensor 582, for example, a light receiving element can be used. In this case, an image sensor is configured. Further, as the sensor 582, a pressure sensor that detects a pressure difference by resistance or capacitance may be used. In this case, a surface roughness sensor that detects the surface roughness of the object, a pattern detection sensor that detects a pattern such as a fingerprint, and the like are configured.
[0247]
Further, a scanning line driver circuit 583, a data driver circuit 584, and a voltage conversion circuit 710 are provided over the glass substrate 580. The scanning electrodes Y1 to Yn are connected to a scanning line driving circuit 583, and the data electrodes X1 to Xm are connected to a data driving circuit 584. The voltage conversion circuit 710 converts the levels of the small-amplitude basic clock signals supplied from the external control circuit 585 that complementarily change into clock signals of different voltages, and supplies the clock signals to the scan line driving circuit 583 and the data driving circuit 584. The configuration of voltage conversion circuit 710 is similar to the configuration of voltage conversion circuit 600 shown in FIG.
[0248]
Any of the level conversion circuits 1 and 1a to 1h of the first to fourteenth embodiments is used for the voltage conversion circuit 710. Thereby, the sensor device of FIG. 44 can reliably operate even when the threshold voltage of the p-channel MOSFET and the n-channel MOSFET greatly varies in the manufacturing process, and can operate at high speed, reduce power consumption, and reduce the area. And high definition can be realized.
[0249]
In the above embodiment, the configuration of the level conversion circuit in the case where the voltage amplitude of the input signals CLK1 and CLK2 is smaller than the amplitude of the output potential VOUT has been described. A configuration in which input signals CLK1 and CLK2 that change with a voltage amplitude equal to power supply potential VDD and a predetermined potential VEE) or input signals CLK1 and CLK2 that change with a voltage amplitude larger than the amplitude of output potential VOUT is received. You can also.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a level conversion circuit according to a first embodiment of the present invention.
FIG. 2 is a schematic diagram showing an example of a range in which a potential of a first node and a potential of a second node can be taken in the level conversion circuit of FIG. 1;
3 is a schematic diagram showing an example of a range in which a potential of a first node and a potential of a second node can be taken in the level conversion circuit of FIG. 1;
4 is a schematic diagram showing an example of a range in which a potential of a first node and a potential of a second node can be taken in the level conversion circuit of FIG. 1;
FIG. 5 is a voltage waveform diagram showing an operation example of the level conversion circuit of FIG.
FIG. 6 is a circuit diagram showing a first example of a circuit configuration of the level conversion circuit of FIG. 1;
FIG. 7 is a circuit diagram showing a second example of the circuit configuration of the level conversion circuit of FIG. 1;
FIG. 8 is a circuit diagram showing a third example of a circuit configuration of the level conversion circuit of FIG. 1;
FIG. 9 is a circuit diagram showing a fourth example of a circuit configuration of the level conversion circuit of FIG. 1;
FIG. 10 is a circuit diagram showing a fifth example of the circuit configuration of the level conversion circuit of FIG. 1;
FIG. 11 is a circuit diagram showing a sixth example of the circuit configuration of the level conversion circuit of FIG. 1;
FIG. 12 is a circuit diagram illustrating a configuration of a level conversion circuit according to a second embodiment of the present invention.
FIG. 13 is a circuit diagram showing a configuration of a level conversion circuit according to a third embodiment of the present invention.
FIG. 14 is a circuit diagram illustrating a configuration of a level conversion circuit according to a fourth embodiment of the present invention.
FIG. 15 is a circuit diagram illustrating a first example of a circuit configuration of the level conversion circuit in FIG. 14;
FIG. 16 is a circuit diagram showing a second example of the circuit configuration of the level conversion circuit of FIG.
FIG. 17 is a circuit diagram showing a third example of the circuit configuration of the level conversion circuit in FIG. 14;
FIG. 18 is a circuit diagram showing a configuration of a level conversion circuit according to a fifth embodiment of the present invention.
FIG. 19 is a circuit diagram showing a configuration of a level conversion circuit according to a sixth embodiment of the present invention.
20 is a voltage waveform diagram showing an operation example of the level conversion circuit of FIG.
FIG. 21 is a circuit diagram showing a circuit configuration of a level conversion circuit used for a simulation.
FIG. 22 is a voltage waveform diagram showing a simulation result when a transistor made of bulk silicon is used.
FIG. 23 is a voltage waveform diagram showing a simulation result when a thin film transistor made of polycrystalline silicon is used.
FIG. 24 is a voltage waveform diagram showing a simulation result when the threshold voltages of the p-channel MOSFET and the n-channel MOSFET are smaller than a set value.
FIG. 25 is a voltage waveform diagram showing a simulation result when the threshold voltages of the p-channel MOSFET and the n-channel MOSFET are set values.
FIG. 26 is a voltage waveform diagram showing a simulation result when the threshold voltages of the p-channel MOSFET and the n-channel MOSFET are higher than a set value.
FIG. 27 is a circuit diagram showing a configuration of a level conversion circuit according to a seventh embodiment of the present invention.
FIG. 28 is a circuit diagram showing a specific configuration example of the level conversion circuit of FIG. 27;
FIG. 29 is a circuit diagram showing a configuration of a level conversion circuit according to an eighth embodiment of the present invention.
FIG. 30 is a circuit diagram showing a configuration of a level conversion circuit according to a ninth embodiment of the present invention.
FIG. 31 is a circuit diagram showing a configuration of a level conversion circuit according to a tenth embodiment of the present invention.
FIG. 32 is a circuit diagram showing a configuration of a level conversion circuit according to an eleventh embodiment of the present invention.
FIG. 33 is a circuit diagram showing a configuration of a level conversion circuit according to a twelfth embodiment of the present invention.
FIG. 34 is a circuit diagram showing a configuration of a level conversion circuit according to a thirteenth embodiment of the present invention.
FIG. 35 is a circuit diagram showing a configuration of a level conversion circuit according to a fourteenth embodiment of the present invention.
FIG. 36 is a block diagram showing a first example of a semiconductor device using the level conversion circuit of the present invention.
FIG. 37 is a block diagram showing a second example of a semiconductor device using the level conversion circuit of the present invention.
FIG. 38 is a circuit diagram showing a third example of a semiconductor device using the level conversion circuit of the present invention.
FIG. 39 is a block diagram showing a fourth example of a semiconductor device using the level conversion circuit of the present invention.
FIG. 40 is a block diagram illustrating an example of a liquid crystal display device using the level conversion circuit of the present invention.
FIG. 41 is a block diagram illustrating a configuration of a voltage conversion circuit used in the liquid crystal display device of FIG. 40.
FIG. 42 is a block diagram illustrating an example of an organic EL device using the level conversion circuit of the present invention.
FIG. 43 is a cross-sectional view showing an example in which the level conversion circuit of the present invention is configured by an SOI device.
FIG. 44 is a block diagram showing an example of a sensor device using the level conversion circuit of the present invention.
FIG. 45 is a circuit diagram showing a first example of a conventional level conversion circuit.
FIG. 46 is a circuit diagram showing a second example of a conventional level conversion circuit.
FIG. 47 is a circuit diagram showing a third example of a conventional level conversion circuit.
FIG. 48 is a circuit diagram showing a fourth example of a conventional level conversion circuit.
[Explanation of symbols]
1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H, 1I, 1J Level conversion circuit
3 Inverter
10, 10A, 10B control unit
20, 20A, 20B Driver section
100, 100a control circuit
101, 104, 201 p-channel MOSFET
102,103,202 n-channel MOSFET
I1, I2 input node
NO output node
NP first node
NN second node
CLK1, CLK2, CLK input signal
Vout, VOUT output potential
Vtp, Vtn threshold voltage

Claims (23)

A first transistor connected between a first node receiving a first potential and an output node;
A second transistor connected between a second node receiving a second potential different from the first potential and the output node;
Upon receiving a first input signal, both the first and second transistors are turned on, and the degree of the on state of each of the first and second transistors is changed in accordance with the level of the first input signal. A level conversion circuit, comprising: control means for controlling. The level conversion circuit according to claim 1, wherein the first input signal changes with a voltage amplitude smaller than a potential difference between the first potential and the second potential. The first input signal changes between a first level and a second level;
The first transistor is a first conductive channel type field effect transistor, the second transistor is a second conductive channel type field effect transistor,
The control means, wherein an absolute value of a difference between the first potential and a gate potential of the first conductive channel type transistor is equal to or greater than an absolute value of a threshold voltage of the first conductive channel type transistor, and The first input signal is supplied such that an absolute value of a difference between a second potential and a gate potential of the second conductive channel type transistor is equal to or greater than an absolute value of a threshold voltage of the second conductive channel type transistor. 3. The level conversion circuit according to claim 1, wherein a gate potential of the first conductive channel type transistor and a gate potential of the second conductive channel type transistor are set in response to the first and second levels. 4. The level conversion circuit according to claim 3, wherein the first potential is a positive potential, and the second potential is a positive potential, a ground potential, or a negative potential lower than the first potential. 5. The level conversion circuit according to claim 4, wherein the second potential is a second input signal that changes to a first level and a second level complementarily to the first input signal. . The first conductive channel type field effect transistor is a first p channel type field effect transistor having a first threshold voltage,
The second conductive channel type field effect transistor is a first n channel type field effect transistor having a second threshold voltage,
The control means sets a gate potential of the first p-channel field-effect transistor within a range lower than the first potential by an absolute value of the first threshold voltage, and 6. The level conversion circuit according to claim 4, wherein the gate potential of the n-channel type field effect transistor is set within a range higher than the second potential by the second threshold voltage or more. The control means includes a second p-channel field-effect transistor, a second n-channel field-effect transistor, and a control circuit,
The source of the second p-channel field-effect transistor receives the first potential, and the gate and drain of the second p-channel field-effect transistor are connected to the gate of the first p-channel field-effect transistor. And
A source of the second n-channel field effect transistor receives the first input signal or the second potential, and a gate and a drain of the second n-channel field effect transistor are the first n-channel field effect transistor. Connected to the gate of the field effect transistor,
The control circuit controls a potential of a drain of the second p-channel field-effect transistor and a potential of a drain of the second n-channel field-effect transistor according to a level of the first input signal. 7. The level conversion circuit according to claim 6, wherein: The control circuit includes first and second load elements,
One end of the first load element receives the first input signal, and the other end of the first load element is connected to a gate of the first p-channel field effect transistor,
The one end of the second load element receives the first potential, and the other end of the second load element is connected to a gate of the first n-channel field effect transistor. 7. The level conversion circuit according to 7. 9. The level conversion circuit according to claim 8, wherein each of said first and second load elements is a field effect transistor or a resistance element. The control means further includes a third p-channel field effect transistor and a third n-channel field effect transistor,
A source, a gate, and a drain of the third p-channel field-effect transistor are connected to a source of the second p-channel field-effect transistor, the output node, and a drain of the second p-channel field-effect transistor, respectively. And
A source, a gate, and a drain of the third n-channel field-effect transistor are respectively connected to a source of the second n-channel field-effect transistor and a drain of the output node of the second n-channel field-effect transistor. 8. The level conversion circuit according to claim 7, wherein: The control means includes a second n-channel field effect transistor and a control circuit,
A source of the second n-channel field effect transistor receives the first input signal or the second potential, and a gate and a drain of the second n-channel field effect transistor are the first n-channel field effect transistor. Connected to the gate of the field effect transistor,
The control circuit controls a potential of a gate of the first n-channel field-effect transistor and a potential of a drain of the second n-channel field-effect transistor according to a level of the first input signal. 7. The level conversion circuit according to claim 6, wherein: The control circuit includes first, second, and third load elements,
One end of the first load element receives the first potential, and the other end of the first load element is connected to a gate of the first p-channel field effect transistor;
One end of the second load element receives the first input signal or the second potential, and the other end of the second load element is connected to a gate of the first p-channel field effect transistor,
The one end of the third load element receives the first potential, and the other end of the third load element is connected to a gate of the first n-channel field effect transistor. 12. The level conversion circuit according to item 11. 13. The level conversion circuit according to claim 12, wherein each of the first, second, and third load elements is a field effect transistor or a resistance element. A current path from the first node to the second node via the first and second transistors during a transition period between a first level and a second level of the first input signal; 14. The level conversion circuit according to claim 1, further comprising a cut-off means for cutting off. The method according to claim 1, wherein the first transistor, the second transistor, and the control unit are formed of a single crystal, polycrystal, or amorphous semiconductor on an insulating substrate. Level conversion circuit as described. A plurality of logic circuits operating on different power supply voltages,
16. A semiconductor device comprising: the level conversion circuit according to claim 1 connected between the plurality of logic circuits. An internal circuit provided on the chip,
An external circuit provided outside the chip,
16. A semiconductor device comprising: the level conversion circuit according to claim 1 connected between the internal circuit and the external circuit. A semiconductor memory provided on a chip,
A logic circuit provided on the chip,
16. A semiconductor device comprising: the level conversion circuit according to claim 1 connected between the semiconductor memory on the chip and the logic circuit. A plurality of sensors, a plurality of selection transistors for selecting any of the plurality of sensors, a peripheral circuit for driving the plurality of sensors via the plurality of selection transistors, and level conversion of a predetermined signal 16. A semiconductor device comprising: the level conversion circuit according to claim 1, which is applied to the peripheral circuit. A plurality of display elements, a plurality of selection transistors for selecting any of the plurality of display elements, a peripheral circuit for driving the plurality of display elements via the plurality of selection transistors, and a predetermined signal 16. A display device comprising: the level conversion circuit according to claim 1, wherein the level conversion circuit supplies the peripheral circuit with the level conversion signal. 21. The device according to claim 20, wherein the plurality of display elements are liquid crystal elements, and the plurality of liquid crystal elements, the plurality of selection transistors, the peripheral circuit, and the level conversion circuit are formed on an insulating substrate. Display device. The plurality of display elements are organic electroluminescence elements, and the plurality of organic electroluminescence elements, the plurality of selection transistors, the peripheral circuit, and the level conversion circuit are formed on an insulating substrate. Item 21. The display device according to Item 20. 23. The display device according to claim 20, wherein the plurality of selection transistors and the first and second transistors of the level conversion circuit are thin film transistors.

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