JP3578786B2 - EL laminated dielectric layer structure, method for producing the dielectric layer structure, laser pattern drawing method, and display panel - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to an electroluminescent laminate and a method for producing an electroluminescent laminate. The invention also relates to an electroluminescent display panel for making an electrical connection from the electroluminescent laminate to a voltage drive circuit. The invention further relates to a laser for imprinting a pattern on a flat laminate. The pattern is, for example, an address line of a transparent electrode of the electroluminescence laminate.
[0002]
[Prior art]
Electroluminescence (EL) is the emission of light from a phosphor due to the application of an electric field. Electroluminescent devices are useful as lamps or displays. Recently, electroluminescent devices are used in flat panel display devices. This element has a predetermined characteristic shape or individually addressable pixels in a rectangular matrix.
[0003]
Pioneering research on electroluminescence was performed at GTESylvania. An AC voltage is supplied to the powder or scattering EL device. In this device, a light-emitting phosphor powder is embedded in an organic adhesive, which is deposited on a glass substrate and covered with a transparent electrode. These powder or scattering EL devices generally have low brightness and have drawbacks that prevent widespread application.
[0004]
Thin film electroluminescent (TFEL) devices were developed in the 1950's. The basic structure of an AC thin film EL laminate is well known and is described, for example, in Tornqvist, R.A. O. The book is described in "Thin-Film Electroluminescent Display", Society for Information Display, 1989, International Symposium Seminar Notebook and U.S. Pat. No. 4,857,802. The phosphor layers are sandwiched between electrode pairs and are separated from the electrodes by respective insulating / dielectric layers. Most commonly, the fluorescent material is ZnS with Mn as the activator (dopant). ZnS: MnTFEL emits yellow light. Other color phosphors have been developed.
[0005]
Conventional TFEL laminate films are deposited on a substrate, usually glass. The deposition of the film takes place by means of substantially known thin-film techniques, for example electron beam vacuum evaporation or sputtering. Recently, it is performed by atomic film epitaxy (ALE). The overall thickness of the TFEL laminate is on the order of only one or two microns.
[0006]
Various insulating / dielectric materials are known for separating and electrically insulating the phosphor layer from the electrodes and are used as described in detail below.
[0007]
Each of the two electrodes is different depending on whether it is on the "rear" or "front" side (in the viewing direction) of the device. A reflective material such as, for example, aluminum is typically used for the back electrode. Relatively thin and optically transparent indium tin oxide (ITO) is typically used for the front electrode. When applied to a lamp, the two electrodes take the form of a continuous film, whereby the entire phosphor layer is exposed to an electric field between the electrodes. In a typical display application, the front and back electrodes are suitably patterned with conductive address lines that define row and column electrodes. Pixels are defined where the row and column electrodes overlap. Various electronic display elements are known that address individual pixels by simultaneously applying a voltage to one row electrode and one column electrode.
[0008]
Although simple in concept, there are a number of practical difficulties in developing thin film electroluminescent devices. The first difficulty is that the components are formed from individual laminates deposited by thin film technology. This is because thin film technology is a time-consuming and costly technology. Very small defects in the film can also cause failure. Second, these thin film devices are typically operated at relatively high voltages (e.g., 300-450 V peak-to-peak). In fact, this voltage is sufficient to operate the phosphor layer beyond its breakdown voltage, making it conductive and operating. The thin film dielectric layers on both sides of the phosphor layer are required to limit or prevent conduction between the electrodes. The application of a large electric field causes dielectric breakdown between the electrodes and causes a failure of the device.
[0009]
The invention is particularly intended to prevent discharges from passing through the insulating / dielectric and phosphor layers of an electroluminescent device. In order for the electroluminescent element to operate properly, the electrodes (address lines) need to be insulated from the fluorescent layer. This is done by the insulating / dielectric layer. Typically, insulating / dielectric layers are provided on both sides of the phosphor layer and are formed from alumina, yttria, silicon dioxide, silicon nitride or other dielectric materials. During operation of the device, electrons from the interface between the insulating and fluorescent layers are accelerated by an electric field such that they pass through the fluorescent layer and collide with dopant atoms in the fluorescent layer, emitting light as a result of the collision process I do. In conventional TFEL devices, the thickness of the dielectric layer is typically less than or equal to the thickness of the phosphor layer to ensure that the electric field strength through the phosphor is sufficiently high. If the dielectric layer is too thick, most of the voltage applied between the address lines will pass through the dielectric layer instead of the phosphor layer.
[0010]
It is important that the dielectric layer be compatible with the phosphor layer. By "compatible" it is meant herein and in the claims that a first good injection interface is formed. This means that the source of "thermal" electrons is at the fluorescent interface and can be promoted and tunneled into the fluorescent conduction band to initiate conduction and light emission in the phosphor layer based on the application of an electric field. Secondly, compatible means that the dielectric material must be chemically stable so that it does not react with adjacent layers (ie, phosphors and electrodes).
[0011]
In a typical TFEL, the voltage applied is very close to the voltage at which dielectric breakdown occurs in order to obtain sufficient light emission. Therefore, manufacturing control over the thickness and quality of the dielectric and phosphor layers must be strictly controlled to prevent dielectric breakdown. This demand, on the contrary, makes it difficult to obtain high yields.
[0012]
A typical TFEL structure is formed from front to back (in the viewing direction). The thin film is continuously deposited on a suitable substrate. Glass substrates are used for transparency. A transparent front electrode (ITO address line) is deposited on a glass substrate by sputtering to a thickness of about 0.2 micron. The substrate dielectric-phosphor-dielectric layer is typically deposited by sputtering or vacuum evaporation. The thickness of the phosphor layer is typically about 0.5 microns. The thickness of the dielectric layer is typically about 0.4 microns. The phosphor layer is usually annealed at about 450 ° C. after deposition to enhance efficiency. A back electrode is then added, typically in the form of a 0.1 micron thick aluminum address line. The finished TEFL laminate is encapsulated to protect it from external moisture. Epoxy thin cover glass or silicone oil capsules are used. Because the initial substrate used for the deposit is typically glass, the materials and deposition techniques used in the TEFL laminate structure are not capable of high temperature processing.
[0013]
The high electric field strength used to operate TFEL devices places severe demands on the dielectric layers. High dielectric strength is required to avoid dielectric breakdown. A dielectric having a high dielectric constant is advantageous for obtaining luminous efficiency at a driving voltage as low as possible. However, attempts to use high dielectric constant materials have not yielded satisfactory results.
[0014]
In order to lower the driving voltage of the TFEL element, the insulating layer is made of a high dielectric constant material, for example, SrTiO.₃, PbTiO₃, BaTa₂O₃Formed from This is described in U.S. Pat. No. 4,857,802. However, these materials do not exhibit good low dielectric breakdown strength. U.S. Pat. No. 4,857,802 describes that a dielectric layer is formed by a thin film deposition technique to obtain an increased planar orientation (111) from a perovskite crystal structure. In the specification, a high dielectric strength (about 8 × 10⁵~ 1.0 × 10⁶V / cm) is SrTiO₃, PbTiO₃, BaTa₂O₃Are described as being obtained with a dielectric layer of about 0.5 microns thick using They all have a high dielectric constant and a perovskite crystal structure. This device is complex and difficult to control with thin film deposition techniques on the dielectric layer.
[0015]
TFEL devices using thin ceramic insulating layers and thin-film electroluminescence have also been developed (see Miyata, T et al., SID 91 Digest, pp 70-73 and pp 286-289). This element is BaTiO₃It is formed from a ceramic sheet. The sheet is fine BaTiO₃The powder is cast into disks (20 mm diameter) and formed using conventional cold pressing. The disc is fired at 1300 ° C. in air. Next, it is ground to a sheet having a thickness of about 0.2 mm. The emissive layer is deposited as a thin film on a sheet using chemical vacuum deposition or RF magnetron sputtering. Next, a suitable electrode layer is deposited on either side of the structure using thin film technology. Although this device exhibits the desired characteristics, it is not preferred to manufacture commercial TFEL devices from solid ceramic sheets. Polishing a large ceramic sheet to a constant thickness of 0.2 mm is not economically feasible.
[0016]
It is also known to use multilayer insulating / dielectric layers on both sides of the phosphor layer. For example, U.S. Pat. No. 4,897,319 discloses a TFEL in which an EL phosphor layer is sandwiched between a pair of insulating stacks. In this case, one or both of the insulating deposits has a first layer of silicon oxynitride (SiON) and a second, relatively thick layer of barium tantalate (BTO). The first SiON layer has a high insulating property, and the second BTO layer has a high dielectric constant. Overall, this structure is characterized by the high brightness of the phosphor layer at conventional voltages. However, the insulating layer is deposited by RF sputtering, which is disadvantageous for the previously described thin film technology.
[0017]
There is a need for a TFEL device that is advantageous for manufacturing and has higher brightness and lower operating voltage than conventional TFEL devices. This requires obtaining a dielectric layer having a higher dielectric strength than the electric field strength required to drive the device.
[0018]
Fabricating electrode patterns on transparent conductive materials, such as indium tin oxide, often involves large and expensive masking and photolithographic and chemical etching processes. Lasers have been proposed to draw such transparent conductive materials. Generally, carbon dioxide, argon and YAG lasers are used. Such lasers produce light in the visible and infrared regions of the electromagnetic spectrum (generally above 400 nm). However, using such long wavelength light to scribe electrode patterns is problematic, especially when a transparent conductive material is deposited on another transparent layer. In a conventional TFEL display, a transparent electrode material, typically indium tin oxide (ITO), is deposited before the transparent display is deposited and the other layers of the EL laminate are deposited. Insulating or semiconducting materials do not strongly absorb light of a longer wavelength than corresponds to the energy of the electronic band gap in the material. For optically transparent materials, the wavelength corresponding to the band gap is shorter than the wavelength for visible light. Therefore, the transparent electrode material does not absorb much laser light. This is due to the long wavelength of light and the small thickness of the layers, which makes it difficult to use laser energy to directly remove the electrode address lines.
[0019]
U.S. Pat. Nos. 4,292,092 and 4,670,058 describe a process for depositing a transparent electrode pattern on another transparent layer in a solar cell. These patents disclose patterning the electrodes using a pulsed YAG laser. However, the wavelength of the YAG laser is too long to be sufficiently absorbed by the transparent layer. To compensate for the low absorption, a high peak power laser is used to thermally evaporate the transparent electrode. The neodymium YAG laser is operated at 4-5 W, a pulse rate of 36 kHz, and a scan rate of 20 cm / s. In the embodiment described in the patent specification, an ITO layer is thus deposited on the glass. However, the scribed lines are described as having incomplete removal of ITO, where the glass has a depth of up to several hundred Angstroms where it melts. Residual ITO must be removed by a subsequent etching step.
[0020]
Another means for forming an electrode pattern on a transparent electrode material is to use an excimer laser. This laser produces light of a relatively short wavelength in the ultraviolet region of the electromagnetic spectrum. At this wavelength, the laser energy can be absorbed by the transparent electrode material. Lasers of this nature include liquid crystal displays (US Pat. No. 4,980,366 and US Pat. No. 4,927,493), photovoltaic cells (US Pat. No. 4,783,421 and US Pat. No. 4,854,974) and integrated circuits (US Pat. No. 4,854,974). It is known to form a conductive pattern with respect to Japanese Patent No. 509149). WO 90/0970 published on August 23, 1990 describes a process of scribing an electrode dot matrix pattern on a transparent conductor on a transparent substrate by an excimer laser.
[0021]
Excimer lasers emit light of a wavelength short enough to be absorbed by the transparent electrode and can be patterned by directly removing the electrode. However, such lasers are relatively expensive and the scribe process must be carefully controlled so as not to melt or remove the underlying display glass. Further, such a process may result in excessive or incomplete removal of the transparent electrode material. For example, WO 90/0970 describes that if only a part of the material to be removed is removed, the remaining part can be removed by chemical or plasma etching.
[0022]
Another problem with scribing transparent electrode material on a transparent substrate is described in US Pat. No. 4,937,129. It is described that a diffusion barrier layer is provided at the interface to avoid diffusion or cross-contamination between layers.
[0023]
Another patent describes surface treatment of a transparent electrode material to enhance the absorption of laser light. For example, U.S. Pat. No. 4,909,895 describes that a metal film surface is oxidized so as not to be relatively reflected by laser light. U.S. Pat. No. 4,568,409 describes coating a transparent layer to be removed with a dye so that laser light is selectively absorbed where removal is desired.
[0024]
Control circuits for driving EL displays have been developed. Basically, this circuit converts serial video data to parallel data and supplies voltages to the rows and columns of the display. Driver elements (chips) in rows and columns as described above are available.
[0025]
Asymmetric and symmetric drive techniques are used in EL display technology. In the asymmetric driving method, a driving pulse is supplied to an EL panel by simultaneously applying a negative sub-threshold voltage to one column. During each column scan time, a positive voltage pulse is applied to the selected row (i.e., the row to emit) and the non-selected row (i.e., the row to not emit) is supplied with zero voltage. At the intersection of the selected row and column, a voltage equal to the sum of the sub-threshold column voltage and the positive pulse voltage of the row is supplied through the pixel to cause light emission. After all columns of the panel have been addressed, a positive polarity refresh pulse is applied simultaneously to all columns and all rows are held at 0V.
[0026]
In the symmetric driving method, the refresh pulse is omitted. Instead, a set of drive pulses of opposite polarity is supplied to the panel. To keep the panel in operation, the columns are scanned in even and odd frames with alternating polarity pulses. The alternating polarity causes a net zero charge at every display pixel.
[0027]
High voltage driver elements (chips) as described above are available in both asymmetric and symmetric drive technologies.
[0028]
Elements for alternating drive circuits and EL displays are known and have been developed. For example, K. Shoji et al., Bidirectional Push-Pull Symmetric Driving Method of TFEL Disply, Springer Proceedings in Physics, Vol. 38, 1989, 324, and Sutton et al., Recent Developments and Trends in Thin-Film Electroluminescent Dispersive Drivers, Springer Proceedings in Physics, Vol. 38, 1989, 318, and Bolger et al., A Second Generation Chip Set for Driving EL Panels, SID, 1985, 229.
[0029]
The above driving method is called a multiplex (passive) matrix addressing method. Theoretically, other driving methods, such as an active matrix addressing method, can also be used for the EL display. But these have not been developed yet. Such an alternating drive method should be considered within the meaning of the phrase voltage drive circuit used herein.
[0030]
In a conventional EL display, one means of connecting the row and column address lines to the drive circuit is to include a polymeric strip comprising a very large number of very closely adjacent metal sheets with a contact column connected to the display address lines. Pressurizing between the contact rows connected to the driver elements of the drive circuit. The drive circuit is arranged on a separate circuit board (see US Pat. No. 4,508,990). The polymeric strip is a layered elastomeric element (LEE) and is known under the trade names STAX and ZEBRA. LEE consists of alternating layers of conductive and non-conductive elastomeric materials. The polymerized strip avoids the laborious connection of connecting hundreds of individual wires to the contacts using solder or welding. However, this interconnect technique is impractical and does not work well at high temperatures that would cause the polymer material to creep.
[0031]
It is conceivable to use another commonly used means for connecting the row and column address lines to the liquid crystal display (LCD) drive circuit, namely chip-on-glass technology (COG) also for electroluminescence. The drive elements (chips) to which the address lines must be connected are located around the edges of the display. In the case of LCDs, address lines deposited on the back of the display glass extend from the active area of the display. Thus, the address lines terminate at the contact pads arranged in the pattern, so that the chip can be bonded to it. Wire bonding involves attaching the chip to the display glass and separately connecting the fine gold wires to the output pads of the chip and the corresponding contact pads of the address lines.
[0032]
An advantage of COG technology is that the number of contacts between the display glass and the drive circuit can be significantly reduced. This is because there are many more contacts between the driver chip and the address lines. Typically there are only 20 to 30 connections between the driver chip and the rest of the drive circuit, but there are as many as 2000 connections between the address lines.
[0033]
A major drawback of COG technology is the difficulty in wire bonding driver chips to address line thin film pads. Therefore, the production yield is poor. Another disadvantage is that space is needed around the display to mount the driver chip. Thus, the size of the display increases, and multiple display modules cannot be combined into an array to form a large display.
[0034]
Through-hole techniques for direct circuit connection are widely known in the semiconductor art (see, for example, US Pat. No. 3,641,390). U.S. Pat. No. 4,710,395 discloses a method and an apparatus for through-hole substrate printing using a controlled vacuum. However, through-hole printing, to the best of the inventor's knowledge, cannot be successfully applied to EL displays.
[0035]
U.S. Pat. No. 3,504,214 describes a segment storage format for EL elements. Here, the pixels are turned on by light to form a photoelectric layer, and then the fluorescent layer becomes conductive. The complexity of the through-hole conductor is described. This specification suggests that normal through-hole connections do not work with high resolution TFEL displays. This is because the conductive material reacts with the phosphor, thereby reducing the performance of the display.
[0036]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide an electroluminescent element which has good luminous efficiency, is easy to manufacture and is simple.
[0037]
[Means for Solving the Problems]
According to the present invention, the above object is achieved by a flat layer of about 1.0 × 10⁶V / m or more, and a ceramic material having a dielectric constant in which the ratio of the dielectric constant of the dielectric material to the dielectric constant of the phosphor is about 50: 1 or more, wherein the dielectric layer is formed by the dielectric layer and the fluorescent layer. The dielectric layer has a thickness adjacent to the phosphor layer, the surface having a thickness ratio in the range of about 20: 1 to 500: 1, the surface being compatible with the phosphor layer and being sufficiently smooth. The fluorescent layer is solved by an EL laminate dielectric layer structure having a dielectric layer configured to generally emit light uniformly under a predetermined excitation voltage.
[0038]
Summary of the Invention
The electroluminescent layers have different dielectric constants. The potential difference between the layers of the laminate is distributed among the layers in proportion to the thickness of each layer and in inverse proportion to the relative permittivity of the material. For example, if one layer has twice the thickness and dielectric constant of another layer, the voltage is evenly distributed between the two layers. The present invention utilizes this property to combine a thick dielectric layer having a high dielectric constant with a thin fluorescent layer having a significantly lower dielectric constant. In this way, before the conduction by the phosphor layer starts, sufficient voltage across the pixel can be present throughout the phosphor layer if the dielectric layer has a sufficiently high dielectric constant. The present invention provides an EL laminate having a new and improved dielectric layer and a method of making the same. The dielectric layerThickThe film is formed from the following ceramic materials.
[0039]
-Dielectric strength about 1.0 × 10⁶V / m or more.
[0040]
The dielectric constant of the dielectric material (k₂) And the dielectric constant of the fluorescent layer (k₁) Is about 50: 1 or more (preferably 100: 1 or more).
[0041]
The thickness of the dielectric layer (d₂) And the thickness of the fluorescent layer (d₁) Is in the range of about 20: 1 to 500: 1 (preferably 40: 1 to 300: 1).
[0042]
The surface adjacent to the phosphor layer is compatible with the phosphor layer, is sufficiently smooth, and the phosphor layer generally emits uniformly at a given excitation voltage.
[0043]
Laminates comprising a dielectric layer according to the invention are most advantageously those in which the fluorescent layer is a thin film layer. A typical thin film phosphor layer is formed from ZnS: Mn to a thickness of about 0.2 to 2.0 microns, typically about 0.5 microns. The ZnS: Mn material has a dielectric constant of about 5 to 10. . Based on theoretical calculations, based on this most advantageous phosphor layer (see guidelines above), the dielectric layer of the present invention preferably has a dielectric constant of 500 or more, most preferably about 1000 or more. Also, the thickness is in the range of about 10 to 300 microns, preferably in the range of 20 to 150 microns. Ferroelectric materials are advantageous for obtaining a high dielectric constant. Most advantageously they have a perovskite crystal structure. For example, the material is PbNbO₃, BaTiO₃, SrTiO₃, PbTiO₃including.
[0044]
The dielectric layer of the present invention is formed into a laminate, which isFrom back to front (display surface)Be composed. Thus, the rear electrode is deposited on the substrate, most preferably a ceramic such as alumina. It can withstand much higher temperatures during manufacture than glass substrates (glass substrates are used from the front to the back of the TFEL structure for front-side transparency). The following dielectric layer of the present inventionThickDeposited on the back electrode by membrane technology. It is fired at a high temperature, which can withstand the substrate and the back electrode. The use of thick film technology and high temperature firing is important for the overall properties of the dielectric layer. A dense layer with a high degree of crystallinity is obtained, since this improves the overall dielectric constant and the dielectric strength of the layer.
[0045]
In fact, the inventor finds it difficult to produce the desired surface (ie, compatible and smooth) of the dielectric adjacent the phosphor layer using currently available ceramic materials. Thus, in a preferred embodiment of the invention, the dielectric layer is formed as two layers and the first dielectric layer is formed on the back electrode, preferably having a high dielectric strength, and having the above-mentioned dielectric constant value. Is set. The second dielectric layer will be the surface adjacent to the phosphor layer as described above.
[0046]
In an advantageous embodiment of the invention, the first dielectric layer isThickDeposited by membrane technology (preferably screen printing), followed by high-temperature firing (preferably at a temperature below the melting point of all sublayers, preferably below 1000 ° C.). A paste comprising a ferroelectric ceramic, preferably a perovskite crystal structure, is an advantageous material if the paste composition permits firing at high firing temperatures. The second dielectric layer is advantageously deposited by a sol-gel technique and is subsequently fired at high temperature to obtain a smooth surface. The material used for the second layer preferably has a high dielectric constant (preferably 20 or more, more preferably 100 or more) and a thickness of 2 microns or more (preferably 2 to 10 microns). is there. Ferroelectric ceramics having a perovskite crystal structure are most advantageous.
[0047]
The present invention comprises a first dielectric layer screen-printed from lead niobate to a thickness of 30 microns and a second dielectric layer spin-deposited to a thickness of 2 to 3 microns from lead zirconate titanate as a sol. Indicated by The sol-gel layer was also demonstrated by immersion to form multiple layers with an overall thickness of 6 to 10 microns. Lead lanthanate zirconate titanate was also shown as a sol-gel layer.
[0048]
It is advantageous but not essential to use two layers of dielectric. The first dielectric layer has the required high dielectric strength and high dielectric constantThickWhile formed as a film, the second layer has no such limitation. If the second layer has the desired compatible, smooth surface, it can be formed from more different materials than are used in the first layer as a thin film. Much work has been done on altering the properties of the dielectric-fluorescent interface of EL laminates, for example, improving chemical stability or injection. Materials or deposition techniques that include these improvements can be used with the first and / or second dielectric layers of the present invention. Applying a third thin film layer further, for example by changing the surface of the second layer in the choice of material or deposition technique used in the first or second layer, or on top of the first or second layer Can be used.
[0049]
Laminates made according to the invention show good luminous efficiency at low operating voltages without breakdown. Advantageous for dielectric layerThickMembrane and sol-gel deposition techniques are generally simple and inexpensive compared to the previously described thin-film techniques. Another advantage of the dielectric layer of the present invention is that the laminate incorporating the layer does not require a separate dielectric layer between the phosphor layer and the second electrode. However, such additional dielectric layers can be included if desired.
[0050]
Accordingly, the present invention applies a dielectric layer in an electroluminescent laminate of the type that includes a phosphor layer sandwiched between a front electrode and a rear electrode. The rear electrode is formed on the substrate, and the fluorescent layer is separated from the rear electrode by a dielectric layer. The dielectric layer has a flat layer formed from a ceramic material. The dielectric strength of this ceramic material is about 1.0 × 10⁶V / m or more and k₂/ K₁Is a dielectric constant of 50: 1 or more, and the dielectric layer is d₂: D₁Is in the range of 20: 1 to 500: 1. Further, the dielectric layer is compatible with the phosphor layer and has a surface adjacent to the phosphor layer that is sufficiently smooth that the phosphor layer generally emits light uniformly at a given excitation voltage.
[0051]
The invention also relates to a method for producing an electroluminescent laminate of the type comprising a phosphor layer sandwiched between a front electrode and a rear electrode. The rear electrode is formed on a substrate, and the fluorescent layer is separated from the rear electrode by a dielectric layer. The method of the present inventionThickDeposit by membrane technology, then firing the ceramic material. This ceramic material is k₂/ K₁Has a dielectric constant of about 50: 1 or more,⁶V / m or more dielectric strength and d₂/ D₁Is formed having a thickness in the range of about 20: 1 to 500: 1. The dielectric layer forms a surface adjacent to the phosphor layer. This surface is compatible with the phosphor layer and is sufficiently smooth so that under a given excitation voltage, the phosphor layer generally emits uniformly.
[0052]
The invention also relates to a process for scribing a pattern with a laser on a flat laminate having at least one upper layer and at least one lower layer. The process irradiates a focused laser beam to the upper layer side of the laminate, the laser beam having a wavelength that is not substantially absorbed by the upper layer but is absorbed by the lower layer. At least a portion of the lower layer is removed directly, and the upper layer is removed indirectly throughout its thickness.
[0053]
In the context of an EL laminate, the upper layer is a transparent conductive material and a light emitter, the lower layer is one or more of a dielectric layer, and the pattern is an electrode pattern of address lines arranged in parallel.
[0054]
The following definitions apply throughout the specification and claims.
[0055]
Absorption occurs in a material when the amount of radiant energy coincides with the allowed transition to a high energy state in the material, for example, by the promotion of electrons through the band gap for the material.
[0056]
Direct removal of material by the laser beam occurs when the primary cause of the removal is decomposition and / or due to absorption of the radiant energy of the laser beam by the material.
[0057]
Indirect removal of material by the laser beam occurs when the primary cause of the removal is evaporation due to heat generation in the material and when transported from adjacent materials that absorb the radiant energy of the laser beam.
[0058]
The present invention relates to an electroluminescent display panel for making an electrical connection from a flat electroluminescent laminate to the output side of one or more voltage drive elements of a drive circuit using a through-hole connector. A display panel formed on the backside of the substrate, having an electroluminescent luminescent laminate having a front set and a rear set of tolerance address lines of a known type;
A plurality of through holes formed in the substrate adjacent to the end of the address line;
A conductive path forming means for making an electrical connection between each address line and a voltage driving element of a driving circuit to each end of the address line through each through hole of the substrate;
[0059]
Advantageously, the electroluminescent laminate of the display panel is of the present invention.ThickIt has a film dielectric layer. This dielectric layer allows the laminate to be formed from the back substrate to the front (in the viewing direction), which also provides a through-hole connector for connecting the voltage drive elements to the address lines andThickThe membrane circuit pattern can be formed by an alternate combination of a circuit manufacturing step and a manufacturing step for electroluminescence.
[0060]
Such a step cannot be easily realized with a conventional electroluminescent laminate structure. That is because the layers are deposited on the front display glass,ThickThis is because it cannot withstand the temperature at which the film conductive paste is fired.
[0061]
According to the present invention, the voltage driving element or the entire driving circuit is formed on the rear surface of the rear substrate. The use of through-hole connectors provides a more direct and reliable interconnection between address lines and drive circuits. No inactive perimeter around the display panel is required (as was required in the prior art). This allows large displays to be combined from individual display panels, without dark boundaries between modules.
[0062]
[Explanation of the embodiment]
FIGS. 1 and 2 show an EL laminate 10 according to the invention with two dielectric layers combined. The laminate 10 is formed on the substrate 12 from the back side. The back electrode layer 14 is formed on the substrate 12. As shown in the drawing, for display applications, the back electrode 14 comprises a row of conductive address lines centered on the substrate 12 and spaced from the substrate edge. An electrical contact tab 16 protrudes from the electrode 14. A first thick dielectric layer 18 is formed on the back electrode 14, followed by a thinner second dielectric layer 20. Further, a phosphorescent layer 22 is formed on the second dielectric layer 20, followed by a transparent front electrode layer 24. Although the front electrode layer 24 is depicted as solid in the drawing, for practical application, this electrode layer is constituted by a row of address lines arranged perpendicular to the address lines of the back electrode 14. . Laminate 10 is encapsulated by a permeable seal layer 26 to prevent ingress of moisture. An electric contact 28 is provided on the second electrode 24.
[0063]
The EL laminate 10 is activated by connecting an AC power source to the electrode contacts 16,28. The EL laminates according to the present invention have the most applications in displays, but have applications as lamps or displays.
[0064]
Those skilled in the art will appreciate that the laminate 10 can be provided with yet another intermediate layer without departing from the framework of the present invention.
[0065]
The method according to the invention for forming a double dielectric layer on one EL laminate, together with advantageous materials and process steps, will now be described.
[0066]
The laminate 10 is formed from the back surface to the front surface (display surface). Laminate 10 is formed on a suitable substrate 12. Substrate 12 is advantageously a ceramic, which can withstand the high sintering temperatures used in dielectric layers (typically 1000 ° C.). Most advantageous is alumina.
[0067]
A first back electrode 14 is deposited on the substrate 12. Numerous techniques and materials are known for wiring thin rows of address lines. Advantageously, the conductive metal address lines are screen-printed with an Ag / Pt alloy paste using a photosensitive emulsion that can be washed off in the area where the paste is to be printed. Thereafter, the paste is dried and fired. Alternatively, the back electrode 14 can be formed of another noble metal, such as gold, or other metals, such as chromium, tungsten, molybdenum, tantalum, or alloys of these metals.
[0068]
A first dielectric layer 18 is deposited on the back electrode by well known thick film techniques. To provide a dielectric constant higher than that of the phosphor layer 22, the first dielectric layer 18 is preferably made from a ferroelectric material, most preferably from one having a perovskite crystal structure. This material has a minimum dielectric constant of 500 over the appropriate operating temperature for lamination, typically over 20 ° C to 100 ° C. Even more advantageously, the dielectric constant of the first dielectric layer material is 1000 or more. An exemplary material for the first dielectric layer 18 is PbnbO₃  , Batio₃  , SrTiO₃  And PbTiO₃  And especially PbNBO₃  Is preferred.
[0069]
One of ordinary skill in the art will appreciate when selecting a ceramic material for the first dielectric layer 18 (ie, an electrically insulating member having a melting point sufficiently high to provide another layer of the laminate). Next, a material known to have a high dielectric constant and a high dielectric strength is selected. These are inherent properties of the material, but values are generally defined for bulk materials that exist in a dense and transparent shape. These properties can be varied depending on the deposition technique used. With respect to the dielectric constant of the material, a thick film deposition technique followed by high temperature sintering (within the range of about 1 micron to about 2 microns) in order to ensure that the dielectric constant does not fall significantly below that of the starting material. 2.) Large particle size and high transparency in dense structures are maintained overall. Similarly, a high dielectric strength can be obtained by using the thick film deposition technique. However, the dielectric strength of the layer should ultimately be measured by applying an operating voltage to the finished laminate.
[0070]
Thick film deposition techniques are conventionally known as described above. In such a technique, the dielectric material is deposited on the back electrode 14 with a desired thickness in a generally uniform range. Thick film deposition techniques are frequently used in the manufacture of electronic circuits on ceramic substrates. Screen printing is the most preferred technique. Commercially available dielectric pastes can be used in the recommended sintering step performed by the paste manufacturer. The paste should be selected or formed to allow for high temperature sintering, typically around 1000 ° C. However, similar results can be obtained with other techniques. An alternative thick film technique is to use a dielectric as a "green tape" so that it can be wired on the back electrode 14. The green tape has a polymer matrix dielectric powder that can be burned during a subsequent sintering process. Before sintering, the tape is flexible and can be spread flat and pressed onto the electrode layer 14. One possible advantage of a green tape over a screen printed dielectric is that it can be burned and somewhat denser with fewer holes. Currently, green tape dielectrics are not readily available. The dielectric thick film paste can also be spread and applied flat on the back electrode layer 14, or can be applied with a doctor blade. More complex techniques, such as electrostatic deposition of the dielectric powder and subsequent sintering that occurs immediately before the powder loses its electrostatic charge, can also be used incidentally.
[0071]
As shown, the first dielectric layer 18 is advantageously screen printed with a paste. In order to achieve low porosity, high crystallinity and minimal crushing, deposition into multiple layers and subsequent sintering at high temperatures is advantageous. The sintering temperature depends on the particular material used, but should not exceed the temperature that the back electrode 14 or the substrate 12 can withstand. For most electrode materials, a temperature of typically 1000 ° C. is at a maximum. The thickness of the first dielectric layer 18 depends on the dielectric constant of this layer and the dielectric constant and thickness of the phosphorescent layer 22 and the second dielectric layer 20. Generally, the thickness of the first dielectric layer 18 is in the range of 10-300 microns, preferably in the range of 20-150 microns, and more preferably in the range of 30-100 microns. .
[0072]
Generally, the criteria for determining the thickness and permittivity of the dielectric layer are to be calculated so that adequate dielectric strength occurs at the minimum operating voltage. These criteria are interrelated as described below. For the phosphorescent layer, a typical thickness range between about 0.2 and 2.0 microns (d₁  ), And a range of dielectric constant (k) between about 5 and 10 for this phosphorescent layer.₁  ) And about 10 to the dielectric layer⁶  -10⁷  Defining a dielectric strength range of V / m, a typical thickness (d) for the dielectric layer of the present invention.₂  ) And permittivity (K₂  The following equations and calculations can be applied to determine the value of In the event that the above typical ranges are to be changed in a meaningful way, these formulas and calculations can be used without departing from the scope of the present invention.₂  And k₂  Can be used as a guideline for determining the value of.
[0073]
The voltage V applied to a double layer with one uniform dielectric layer and one uniform non-conductive phosphor layer sandwiched between two conductive electrodes is defined by Equation 1:
V = E₂  * D₂  + E₁  * D₁                  (1)
In this case, E2 is the electric field strength in the dielectric layer, E1 is the electric field strength in the phosphorescent layer, d₂  Is the thickness of the dielectric layer, d₁  Is the thickness of the phosphorescent layer.
[0074]
In these calculations, the direction of the electric field is perpendicular to the intervening region between the phosphorescent layer and the dielectric layer. Equation 1 applies as long as a voltage lower than the threshold voltage is applied. At this threshold voltage, the electric field strength in the phosphorescent layer is high enough that the phosphorescent layer begins to break down electrically and the device begins to emit light.
[0075]
According to electromagnetic theory, the component of the electric displacement (electric flux density) D perpendicular to the intervening region between two insulating materials having different dielectric constants is continuous over the intervening region. This electrical displacement component in a material is defined as the product of the dielectric constant and the electric field component in the same direction. From this relationship, Equation 2 is derived for the intervening region in the double layer structure:
k₂  * E₂  = K₁  * E₁                      (2)
In this case, k₂  Is the dielectric constant of the dielectric material, k₁  Is the dielectric constant of the phosphorescent material.
[0076]
Equations 1 and 2 can be combined to give Equation 3:
V = (k₁  * D₂  / K₂  + D₁  ) * E₁        (3)
In order to minimize the threshold voltage, the first term of Equation 3 needs to be reduced for practical use. In order to maximize the light emitted by the phosphorescent layer, the second term is dictated by the choice of the thickness of the phosphorescent layer. In determining these values, the first term is chosen to be one tenth the size of the second term. Substituting this condition into Equation 3 gives Equation 4:
d₂  / K₂  = 0.1 * d₁  / K₁              (4)
Equation 4 gives the ratio of the thickness of the dielectric layer to its dielectric constant with respect to the properties of the phosphorescent layer. This thickness is uniquely determined by the requirement that when the phosphorescent layer conducts above the threshold voltage, the dielectric strength of the insulating layer is sufficient to hold the entire applied voltage. The thickness is calculated using Equation 5:
d₂  = V / S (5)
In this case, S is the dielectric strength of the dielectric material.
[0077]
The above equation and d₁  , K₁  , S, the appropriate range for the thickness and permittivity of the dielectric layer described in the present specification and claims is obtained.
[0078]
As mentioned above, the first dielectric layer 18 has a sufficiently smooth surface adjacent to the phosphorescent layer (ie, for the subsequently deposited phosphorescent layer to emit light generally uniformly at a given excitation voltage). The second dielectric layer 20 is unnecessary if it has a sufficiently smooth surface) and is compatible with the phosphorescent layer 22. Generally, it is sufficient if the relief of the surface does not vary by more than about 0.5 microns over about 1000 microns (which is approximately equal to one pixel width). It is even more preferable that the surface undulation is 0.1 to 0.2 microns at this interval. If the first dielectric layer 18 has a sufficiently smooth surface but does not have the desired compatibility with the phosphorescent layer 22, a further layer of material (preferably a dielectric Layers, but need not be) may be added, for example, by thin film technology.
[0079]
If a second dielectric layer 20 is required, this layer is created on the first dielectric layer. The second dielectric layer 20 can have a dielectric constant less than the dielectric constant of the first dielectric layer 18 and typically has a thinner layer (preferably greater than 2 microns and more preferably between 2 and 10 microns). Micron). The desired thickness of the second dielectric layer is generally a function of the smoothness, i.e., if a smooth surface is obtained, this layer can be as thin as possible. In order to obtain a smooth surface, a sol-gel deposition technique is advantageously used, followed by sintering at a high temperature. Sol-gel deposition technology is well known in the art, for example,
"Fundamental Principles of Sol Gel Technology", R.A. W. See Jones The Institute of Metals, 1989. In general, the sol-gel process allows the materials to be mixed at the molecular level in the sol, while still retaining the solvent, before being removed from solution as a colloidal gel or polymerized polymer network. Removal of the solvent leaves a solid with a high level of dense porosity. Thus, the value of surface free energy is increased, and the solids can be sintered and concentrated at lower temperatures than would be done with most other techniques.
[0080]
The sol-gel material is deposited on the first dielectric layer 18 to obtain a smooth surface. This sol-gel process allows pores on the sintered thick film layer to be filled in addition to producing a smooth surface. Spin deposition or immersion is most preferred. These are technologies that have been used in the semiconductor industry for many years, primarily in photolithographic processes. In the case of spin deposition, the sol material is dropped onto the spinning first dielectric layer 18 at high speed-typically at several thousand revolutions per minute. The sol can be deposited in several steps if desired. The thickness of layer 20 is controlled by changing the viscosity of the sol-gel and by changing the spin rate. After spinning, a thin layer of wet sol-gel is created on the surface. The sol-gel layer 20 is sintered at a temperature typically below 1000 ° C. to produce a ceramic surface. Sols can also be deposited by immersion. The surface to be coated is immersed in the sol and then withdrawn at a constant rate-usually very slowly. The thickness of the layer is controlled by changing the viscosity and withdrawal rate of the sol. In addition, the sol may be screen printed or spray coated, but with these techniques it is relatively difficult to control layer thickness.
[0081]
The material used for the second dielectric layer 20 is preferably a ferroelectric ceramic material, which preferably has a perovskite crystal structure in order to produce a high dielectric constant. Advantageously, this dielectric constant is similar to that of the first dielectric layer in order to avoid voltage fluctuations in the two dielectric layers 18,20. Nevertheless, for the thinner layers used in the second dielectric 20, the permittivity can be used as low as about 20, but is preferably greater than 100. Illustrative materials include zirconate-lead titanate (PZT), lanthanate-zirconate-lead titanate (PLZT), and the titanates of Sr, Pb and Ba used in the first dielectric layer 18. Included, in which case PZT and PLZT are most preferred.
[0082]
In order to produce a smooth ceramic surface suitable for the deposition of the next layer, PZT or PLZT is advantageously prepared by spin deposition and subsequent sintering at temperatures below about 600 ° C. Will be deposited as
[0083]
The next layer to be deposited is typically the phosphorescent layer 22, but as described above, for the purpose of further improving the intervening region with the phosphorescent layer, within the framework of the present invention the second dielectric layer 20 Further layers may be provided thereon. For example, a thin film layer of a material known to have good injectability and compatibility can be used.
[0084]
The phosphorescent layer 22 is deposited by a known thin film deposition technique such as vacuum deposition or sputtering using an electron beam evaporator. The preferred phosphorescent material is ZnS: Mn, but other phosphors that emit light of different colors are known. Phosphorescent layer 22 typically has a thickness of about 0.5 microns and a dielectric constant of about 5-10.
[0085]
A separate transparent dielectric layer over the phosphorescent layer 22 is not required, but may be provided if desired.
[0086]
The front electrode layer 24 is deposited directly on the phosphorescent layer 22 (if provided, another dielectric layer). This front electrode is transparent and is advantageously made from indium tin oxide (ITO), which is known from thin film deposition techniques such as vacuum evaporation in an electron beam evaporator.
[0087]
The laminate 10 is typically annealed and then sealed with a sealing layer 26 such as glass.
[0088]
Advantageous laminates having typical thickness values according to the invention are as follows from back to front:
Substrate layer Alumina
Back electrode Ag / Pt address line 10 microns
First dielectric layer Lead niobate 30 microns
Second dielectric layer Zirconate-lead titanate 2 microns
Phosphorescent layer ZnS: Mn 0.5 micron
Front electrode ITO 0.1 micron
Seal layer glass 10-20 microns
For large EL displays, the layer thickness can be varied. For example, the thickness of the sol-gel layer is typically increased by about 6-10 microns to obtain the desired smoothness. Similarly, the thickness of the ITO layer can be increased to 0.3 microns for large displays.
[0089]
According to the invention, the connection between the address lines on the front and back of the electroluminescent laminate and the voltage drive circuit is advantageously made by penetrating through holes in the back substrate. Most preferably, the EL laminate has the thick dielectric layer of the present invention-although this is not required.
[0090]
The voltage drive circuit has a voltage drive component (typically referred to as a high voltage drive chip). The outputs of this component are connected to the individual row and column address lines of the back and front electrodes to selectively excite the pixels in response to the video input signal. Voltage drive circuits and components are generally known in the prior art. To illustrate the present invention, through-hole connections are provided for a well-known packaged high-voltage drive chip, which is mounted on a back substrate by well-known reflow soldering techniques. Surface mounted. High voltage drive chips of this type are known as conventional symmetric and asymmetric pulse drive types.
[0091]
However, as will be appreciated by those skilled in the art, special driver circuits or driver components can be modified, and thus, of course, the pattern of through holes and the circuit pattern provided for connection to the driver circuit. May have an effect. The present invention, as an example, allows the entire driver circuit or only a portion thereof to be mounted on a rear substrate. For example, instead of using a high voltage package chip, a bare silicon die (chip) can be used on the substrate using conventional die attach methods, and the chip can be mounted on the substrate using conventional wire bonding techniques. Can be connected to a circuit. In this case, the driver chip occupies only a small area on the substrate, and the entire driver circuit can be disposed on the substrate. As a result, the ultra-thin display panel can be interfaced directly to a video signal and connected directly to a DC power source. Such displays are useful in ultra-thin portable products that require a display. Of course, the ability to mount the driver circuit on the back side of the board can be applied to displays of any size, and a relatively large display provides more space for mounting the drive circuit directly on the back side of the board. be able to.
[0092]
The circuit connection state of the present invention is shown in FIGS. As mentioned above, special through holes and circuit patterns are provided for mounting the high voltage driver chip 30 on the opposite side of the rear substrate for illustration purposes. A special chip selection is that Supertex HV7022PJ is for connection to column address line 14 and Supertex HV8308PJ and HV8408PJ (Supertex, Sunnyvale, CA) are for connection to row address line 24. The latter two chips differ in that one lead pattern is a mirror image of the other.
[0093]
Referring to the figures, the EL laminate 10 is advantageously (but not necessarily) comprised of the two dielectric layers 18 and 20 of the present invention, and thus from the rear substrate 12 to the front. It is configured toward the viewing side. The rear substrate 12 is perforated with through-holes 32 so that the pattern is such that the substrate 12 and the through-hole 32 are closest to both ends of the address lines 14, 24 (to be formed later). Have been. Alternatively, additional through-holes can be provided at predetermined intervals along the address lines. This is useful for making connections to the high resistance front ITO address lines. The pattern in FIG. 4 is for connection to the EL laminate 10 on the square substrate 12, and the square substrate 12 is provided with column address lines (rear electrodes) 14 along a relatively long dimension, and row address lines. (Front electrode) 24 is provided along a relatively short dimension.
[0094]
The through hole 32 is advantageously formed by a laser. Holes 32 are typically extended on one side due to the nature of the laser drilling process, which may be on the rear or opposite side to facilitate passing conductive material into the holes. Selected as is.
[0095]
The substrate 12 used in the EL laminate should be capable of reducing the temperatures encountered in subsequent processing steps. Typically, the substrate used is sufficient to firmly support the laminate, and to temperatures above 850 ° C. to withstand subsequent firing sintering for thin film paste and sol-gel materials. It is stable against it. Therefore, the substrate should be impermeable to laser light, so that laser drilling can form through-holes 32. Finally, the substrate should provide good adhesion of the thin film paste used in subsequent steps. Crystalline ceramic materials and non-conductive glassy materials are used. Alumina is particularly advantageous.
[0096]
The circuit pattern 34 of the conductive material is printed on the rear surface of the substrate 12 in the pattern shown in FIG. In this step, the conductive material is drawn through the through holes 32 as described above. The circuit pattern 34 on the rear surface of the substrate 12 includes a rear connector pad 36 around each of the through holes 32, a chip connector pad 38 for outputting a high-voltage driver chip (not shown), and a drive circuit (shown in FIG. (Not shown) for connection to the rest of the connector pads (not labeled), and electrical leads (unlabeled) between a number of connector pads as shown.
[0097]
The conductive material is advantageously a conductive thin film paste applied by screen printing.
[0098]
A vacuum is applied on the front side of the substrate 12 to form a conductive path through each through hole 32, while the circuit 34 is printed on the back side. This is advantageously achieved by placing the substrate 12 on a vacuum table having a master plate, the master plate having holes drilled between the substrate 12 and the vacuum in the pattern of FIG. are doing. Each hole in the master plate is aligned and somewhat larger than the hole in substrate 12. No vacuum is applied until the circuit is printed to ensure that the vacuum is applied uniformly. The vacuum is continued until the conductive material is pulled through to the front side of the substrate. At that point, a small amount of conductive material is pulled through the front side of substrate 12 to cover the through-hole wall. The thin film paste is then fired according to known procedures.
[0099]
Following this step, the circuit pad reinforcement pattern 42 is advantageously (but not necessarily) printed as shown in FIG. As with the conductive material, the printing and firing steps are continued.
[0100]
The column address lines 14 and the connector pads 40a, 40b are then formed on the front side of the substrate 12, preferably by screen printing a thin film conductive paste, such as a silver / platinum paste. The address line pattern is shown in FIG. 6 and has a row extending along the length of the substrate 12 and ending with a front (row) connector pad 40a. During this same step, a front (row) connector pad 40b is provided to ultimately connect the row address line to the drive circuit via the through hole 32. The conductive paste is advantageously withdrawn through the through-holes 32, as described above, wherein a vacuum is applied from the rear circuit side of the substrate.
[0101]
The means for forming the conductive path through the through-hole 32 has been described in detail above, since it is formed from a thin film conductive paste, but the conductive paste may, as is known in the prior art, be used to form an electrically plated through-hole. As such, or such that the through-holes are formed by non-electrical plating, an electroplated material is provided that is properly adhered to the substrate, and subsequent layers are provided to the plate conductor. Is attached.
[0102]
The thin-film dielectric layer 18 of the present invention is then advantageously formed and fired as described above.
[0103]
The rear circuit surface of the substrate is then advantageously sealed with a rear sealant 44, for example, by screen printing with thin-film glass paste, connecting the connector pads for mounting high-voltage driver chips, and The connector pins 45 are left exposed for attachment to the rest of the driver circuit (not shown). The sealing pattern is shown in FIG.
[0104]
The EL laminate is then complemented by a sol-gel layer 20, a phosphor layer 22, and a front row address line 24. The pattern for the front row address line 24 is shown in FIG. It comprises parallel rows across the thickness of the substrate 12 terminating near the front (row) connector pads 40. Optionally, electrical interconnections 46 between row address lines 24 and front (row) connector pads 40 are provided for reliable electrical connection. These are advantageously formed by printing a conductive material, such as silver, through a shadow mask in the pattern shown in FIG.
[0105]
The above-described front sealing layer 26 is provided for the purpose of preventing moisture transmission.
[0106]
According to the invention, the front ITO address lines 24 of the EL laminate 10 are advantageously formed by laser writing. This laser writing technique is shown in connection with the advantageous EL laminate 10 of the present invention. However, it should be understood that laser writing techniques are more widely applied when patterning planar laminates having upper and lower layers. In this regard, the ITO and phosphor layers 24, 22 have upper layers that do not substantially absorb laser light. Furthermore, the thick rounded niobium dielectric layer 18 and the rounded zirconate titanate sol-gel layer 20 have a lower layer that does not absorb laser light. Another typical material is SnO as a transparent (translucent) conductor.₂, In₂O₃including.
[0107]
Usually, in the spirit of the present invention, the upper layer is a material that transmits visible light, and the lower layer is a material that does not transmit visible light. The lower material is therefore directly perforated and the upper layer is indirectly perforated. In this case, drilling is performed with a laser beam having a wavelength in the visible region or in the infrared region of the electromagnetic spectrum. This laser perforation method is widely used in semiconductors, liquid crystal displays, solar cells and EL displays.
[0108]
Materials to control the accuracy and resolution of laser writing (depth and width of cut) and to avoid explosive delaminating of layers and to minimize interdiffusion between layers The specified properties and layer thickness should be observed.
[0109]
The following relationship is maintained for a two-layer laminate.
[0110]
Where α_uT_u> Α_oT_o,
α_u= Absorption coefficient of lower layer,
α_o= Absorption coefficient of upper layer,
T_u= Thickness of lower layer,
T_o= Thickness of upper layer,
Product α_uT_uIs the product α_oT_oIt is even more advantageous to be significantly larger than.
[0111]
When a plurality of upper transparent layers and / or a plurality of opaque layers are provided, the product α for each layer_uT_uIs the product α for each layer_oT_oShould be greater than the sum of
Σ_iα_uiT_ui> Σ_iα_oiT_oi
When the above function is maintained, the steps of the present invention should directly perforate only a portion of the lower layer without cutting through its entire thickness, and It should be drilled indirectly through the thickness.
[0112]
Explosive delamination can occur if heat or vapor pressure builds in the lower layer before the upper layer can soften and / or evaporate due to indirect perforation. Therefore, the material in the upper layer should melt and vaporize at a lower temperature than the temperature at which the material in the lower layer melts and vaporizes.
[0113]
For the purpose of improving the high resolution cutting performance, it is advantageous if the thermal conductivity of the material in the lower layer is smaller than that of the material in the upper layer. The thermal conductivity of both layers is selected from the area being perforated so that no significant heat is dissipated while this area is being irradiated with laser light.
[0114]
In order to avoid interdiffusion of material between the layers, the diffusion time for this process should be longer than the time when the area to be drilled is irradiated with a laser beam.
[0115]
The aforementioned properties are known for the materials and can provide an advance notice of which materials are suitable for the laser writing process of the present invention.
[0116]
Laser cutting resolution, explosive delamination and interdiffusion are also affected by the energy and scanning speed of the laser beam. However, if the foregoing relationship is maintained, these other laser conditions are usually maintained, and these other laser conditions are controlled and controlled to achieve the desired results of direct and indirect drilling. Change is possible.
[0117]
Laser beams that provide a laser beam having a wavelength in the visible or infrared region are known. Carbon dioxide lasers, argon lasers and YAG lasers are examples. All lasers have wavelengths greater than 400 nm. Pulsed or continuous wave lasers can be used. The latter is advantageous for forming sharp high-resolution notches. The laser beam is focused by a suitable lens device. Its purpose is to ensure sufficient local density for complete removal of the upper layer. Normally, the energy density of the laser beam is set such that the groove to be cut is sufficiently larger than the thickness of the upper transparent layer. When the transparent layer includes electrode address lines, this ensures that the address lines are clearly defined and electrically isolated.
[0118]
Writing is performed by moving a laser beam with respect to the material to be written. More advantageously, this is done by placing the material to be written on an xy coordinate table that is movable relative to the laser beam.
[0119]
To write the address lines, a table movable in the x-direction (ie, perpendicular to the address line to be written) is advantageous, and the laser beam is movable in the y-direction, ie, along the address lines.
[0120]
Materials that are vaporized or decomposed during laser writing can be removed from the written material by a vacuum provided near the laser beam.
[0121]
An advantageous EL laminate 10 according to the invention, a thin layer 24 of indium tin oxide, is deposited on the phosphor layer 22 in a known manner. Vacuum deposition methods for depositing ITO or methods for depositing ITO are disclosed in U.S. Pat. Nos. 4,568,578 and 4,849,252. It is also possible to use tin oxide doped with a material other than ITO, for example, fluorine. An optically transparent dielectric layer can be provided between the ITO and the phosphorus layers 24,22. An advantageous sol-gel layer 20 of PZT and a thick-film dielectric layer of blunt niobium are provided below the phosphorus layer. The EL laminate 10 is formed in the reverse sequence to the conventional TFEL device, as described above. This leaves an ITO layer 24 and a phosphor layer 22 suitable for laser writing according to the invention as conventional, as an upper transparent layer above the lower opaque dielectric layers 18,20.
[0122]
Each row address line 24 is laser written as previously described. The laser beam directly removes at least a portion of the sol-gel layer 20 and a small portion of the thick underlying dielectric layer 18 and indirectly removes the ITO and phosphor layers 24, 22 over their thickness. This leaves a reliable insulating gap between adjacent address lines.
[0123]
The row address line 24 is connected to the driving circuit described above. In particular, with the advantageous through-hole connection described above, the electrical interconnect 46 (prior to laser writing) will eventually form the address lines by depositing silver in the pattern shown in FIG. It is formed at a position overlapping a part of the ITO layer.
[0124]
Next, the address lines are written as described above.
[0125]
The completed EL laminate can be sealed by spraying a protective polymer seal on the front visible surface, as described above, or by bonding a glass plate to the front surface.
[0126]
The use of indirect perforations for writing a transparent conductor material offers several advantages. Instead of an ultraviolet pulse laser with a high instantaneous output, a very low energy coupled wave laser that emits light in the visible region can be used. This laser not only reduces cost, but also creates a smoother line on the deleted cut. This is significantly important for high resolution EL displays. Direct drilling of a transparent material requires significantly higher instantaneous laser energy to deliver the energy required for drilling in a time short enough to prevent heat from spreading from the area where drilling occurs. In prior art attempts to directly drill a transparent conductor provided on a transparent substrate, only a small portion of the laser energy is provided directly by the transparent conductor material; Pass through different layers. In many cases, indirect perforations minimize the problem of interdiffusion between layers. This is because the heat for vaporizing the transparent layer is generated from the bottom of the transparent layer. This facilitates the removal of the perforated material to the outside, rather than the diffusion of the material into the underlying layer. This is important for maintaining the quality of the dielectric and phosphor layers in the EL display.
[0127]
The invention is further illustrated by the following variant embodiment.
[0128]
Example 1
This example shows that simple printing of a thick film layer of barium titanate (a material used as a ceramic sheet in Miyata et al.) Is subject to electrical breakdown under conditions. .
[0129]
Single pixel electroluminescent devices were formed on an alumina substrate (5 cm square, 0.1 cm thick) obtained from Coors ceramic (Grand Junction, Colorado, USA). A back electrode layer is in contact with the center of the substrate at a distance from the edge. The material used is a silver / platinum conductor. This is conventionally printed as an address line in electronics. Specifically, Cermalloy # C4747 (available from Cermalloy, Conshohocken, Pa.) Was screen printed as a thick film paste on a 320 mesh stainless steel screen and coated with a photosensitizer. This photosensitizer was irradiated with ultraviolet light through a photomask. The purpose is to expose areas of the photosensitizer that have been maintained for printing. Unexposed photosensitizer was removed by dissolving in water. The paste is printed through this screen at this point. The remaining photosensitizer was then further cured by additional light irradiation. The printed paste was dried in a 150 ° C. oven for several minutes and heated in air in a BTU model TFF142-790A24 belt oven at the temperature profile recommended by the paste maker. The maximum process temperature was 850 ° C. The resulting thickness of the heated electrode conductor layer was about 9 microns.
[0130]
The dielectric layer is formed on this electrode layer as follows. Barium titanate (ESL # 4520-ElElectroscience Laboratories, available from King of Prussia, Pennsylvania, dielectric constant 2500-3000) is printed in a square pattern through a 200 mesh screen. As a result, everything was covered except for the electrical contact pads in the electrode lines. The printed dielectric paste was heated in air in a BTU furnace according to the temperature profile recommended by the manufacturer (maximum temperature 900-1000 ° C.). The thickness of the resulting heated dielectric is in the range of 12-15 microns. The second and third layers of dielectric were then printed and heated on the first layer in the same manner. The combined thickness of the three printed and sintered dielectric layers is 40-50 microns.
[0131]
A phosphorus layer was deposited directly on the dielectric layer by known thin-film techniques. Specifically, a 0.5 micron thick layer of copper sulfide doped with 1 mole percent of manganese is deposited over the dielectric layer using a UHV Instruments Model 6000 e-beam evaporator. These layers are heated under vacuum in a deposition apparatus and maintained at a temperature of 150 ° C. during the deposition for about 2 minutes.
[0132]
A phosphor layer is coated with a 0.5 micron layer of a transparent electrical conductor made of indium tin oxide. This layer is deposited by known thin film deposition techniques, in particular using an electron beam evaporation apparatus at 400 ° C. under vacuum.
[0133]
The laminate is then treated in air at 450 ° C. for 15 minutes to anneal the indium phosphorus indium oxide conductor layer. Indium braze contacts are provided to the ITO layer. This element is sealed with a silicon sealing material (Silicone Resin Clear Lacqver, cat. # 419.MG Chemicals).
[0134]
The device is tested by applying a DC voltage between the two electrodes. The device is observed to fail if a voltage is applied that causes electrical breakdown of the dielectric layer in the region immediately adjacent to the indium tin oxide contact.
[0135]
It is presumed that this device failure occurred because the dielectric layer did not form the smooth surface required for the phosphorus layer. Fine cracks may be observed on the surface. However, this may be due to the presence of interfering materials in commercially available dielectric pastes. As such, barium titanate is not an indicator that it cannot be used as a single or first dielectric layer according to the present invention.
[0136]
Example 2
This example demonstrates that a screen-printed dielectric layer consisting of a paste containing bleached niobate, which is known to have a higher dielectric constant and a lower sintering temperature than barium titanate, is suitable, Gives a dielectric constant but does not emit light.
[0137]
The device has the same configuration as in the first embodiment. However, it has a dielectric layer composed of a dielectric paste of niobate, Cermalloy # IP9333 (dielectric constant is about 3500, thickness is the same as Example 1). When tested, this device did not suffer from dielectric breakdown when a DC voltage of 400 V was applied. However, no light emission occurred even when an AC voltage was applied.
[0138]
The lack of light emission is due to compatibility problems in connection with the phosphor layer. This should not be an indication that blunt niobate cannot be used as a single or first dielectric layer according to the present invention.
[0139]
This example shows a two-layer dielectric constructed according to the present invention. A first dielectric layer of blunt niobate (as in the second embodiment) and a second dielectric layer of blunt zirconate. The desired luminescence was achieved.
[0140]
An element similar to that in the second embodiment is formed. However, there is an additional step of applying a layer of round zirconate (PZT) to the printed and heated dielectric layer using a sol-gel process before the phosphorus layer is applied. The sol was prepared as follows. Acetic acid is dehydrated at 105 ° C. for 5 minutes. Twelve grams of acetic acid tuna was melted into 7 ml of 80 ° dehydrated acid to form a colorless solution. The solution was cooled and 5.54 g of propoxylated zirconium was mixed into the solution to form a blue-yellow solution. The solution was left at 60 ° -80 ° for 5 minutes, after which 2.18 g of titanium isopropoxylated was added with stirring. The resulting solution remains. Stirred in an ultrasonic bath to ensure that the solute melted. Then 1.75 ml of a 4: 2: 1 solution of ethylene glycol, propanol, water was added to form a stable sol. More ethylene glycol was added prior to coating to adjust the viscosity to the desired value for spin coating or dipping. The prepared dielectric layer was spin coated or dipped with a sol. In the case of spin coating, the sol was dropped at 3000 rpm onto the spinning first dielectric layer in a horizontal plane. In the case of dipping, a higher viscosity sol was used. The substrate was lifted from the sol at a speed of 5 cm / min for the dipping step. The resulting coated assembly was then heated in a furnace air at a temperature of 600 ° C. for 30 minutes to convert the sol to PZT. The thickness of the PZT layer was about 2-3 microns. The surface of the PZT layer was observed to be significantly smoother than the surface of the screen printed and sintered first dielectric layer.
[0141]
Following the deposition of the PZT layer, a phosphorus layer and a transparent layer are deposited as in Example 1.
[0142]
The finished laminate was manufactured with properties similar to or better than those reported by Miyata et al. In emission-voltage characteristics. The threshold voltage for minimum brightness for display was 110V. The luminous intensity at 50 V above the threshold (ie, 160 V, 60 Hz) was 57 foot Lambert.
[0143]
In this embodiment, changes in the thickness of the dielectric layer affect the operating voltage and the brightness of the display.
[0144]
The display was configured as in Example 3. The difference is that only two instead of three screen printed dielectric layers were applied. The thickness of the first dielectric layer was correspondingly reduced to 25-30 microns.
[0145]
The threshold voltage for the minimum luminance was expected to be 70 V (110 candlelight in Example 3) from theoretical considerations. The luminance at 50 V above the threshold was also reduced to 35 footlamberts (57 candlelight footlamvers, Example 3).
[0146]
Example 5
This embodiment shows an advantageous embodiment of connecting the row and row address lines of an EL laminate to a drive circuit using through holes.
[0147]
The addressable EL display is constructed using the same sequence of layer deposition shown in Example 3. The substrate was 0.025 inch thick rectangular alumina. The alumina was obtained from Coors Ceramics (Grand Junction, Colorado, U.S.A.) having dimensions of 2 inches long by 2 inches wide. The substrate was drilled with a 0.006 inch diameter through hole using a carbon dioxide laser in the pattern shown in FIG. The substrate was inspected to ensure that all holes were clear. The hole was found to be about 0.008 inches in diameter on the side facing the laser and about 0.006 inches on the opposite side. The side with the larger hole was selected on the back side of the substrate to facilitate the insertion of conductive material into the through hole.
[0148]
Following this, the circuit pattern shown in FIG. 5 was printed with a 325 mesh stainless steel stainless screen using Cermalloy # 4740 silver platinum paste. During this printing process, the substrate is centered with a master plate having 0.040 inch holes drilled in the same pattern as shown in FIG. 4 and drawing a conductive pace through through holes in the substrate. For this purpose, a vacuum is applied below the master plate (i.e., over the whole surface as viewed from the paper side of the substrate). This step formed the circuit pattern of FIG. 5 with the conductive paths through each of the through holes in the substrate. To ensure uniformity in applying the vacuum, the vacuum is only applied after the substrate has been printed. This part ensures that the through holes are filled.
[0149]
Subsequent to printing, the substrate is heated in a BTU model TFF142-790A24 with a temperature profile advanced by the paste manufacturer. The maximum temperature was 850 ° C.
[0150]
Following this step, the circuit reinforcement pattern shown in FIG. 7 is printed and the circuit backside of the substrate is heated (using the same Cermalloy conductive paste). This step makes the circuit pattern thicker in certain areas where electrical connections are to be made substantially.
[0151]
The column address lines and front column and row connector pads were then screen printed on the front side of the substrate. The lines extended the length of the substrate to the column connector pads shown in FIG. The row connector pads shown in FIG. 5 are printed in this same step. The column address lines and connector pads were formed from the same conductive paste (Cermalloy # 4740) using the same printing and heating conditions. The substrate was positioned on the same master plate by the through-holes of FIG. 4 and vacuum was applied from below to draw the conductive paste through the through-holes to the backside of the substrate. The thickness of the heated electrode layer was about 8 micrometers. 52 address lines were formed per inch, and the total number of address lines was 68. This part was inspected to ensure that the through holes were filled.
[0152]
Three layers of dielectric paste (Cermalloy # IP9333) were printed and heated as described in Example 3 with the purpose of forming a dielectric layer having a thickness of about 50 micrometers.
[0153]
Next, the circuit back side of the substrate was sealed. A thick film glass paste (Heraeus IP9028, Heraeus-Cermalloy, Conshohocken, Pa.) Was screen printed using a 250 mesh screen in the pattern shown in FIG. Connector pads for connecting to high voltage drive chips and other drive circuits were not covered. The glass seal layer was then heated in a BTU belt furnace at a temperature of up to 700 ° C. using the temperature profile recommended by the manufacturer.
[0154]
During the aforementioned heating, the substrate was supported on a ceramic material part in order to avoid contact between the printed material on the circuit side and the belt of the furnace.
[0155]
The sol-gel layer is formed substantially by immersion as described in Example 3. Three or four sol-gel layers are typically used. It is used with a pooling rate of 10 to 25 sec / in from a mixture having a viscosity of approximately 100 cP, measured for example by a falling ball viscometer. The sol-gel is dried at 110 ° C. for 10 minutes between the dipping layers. Vacuum chucking is performed over the active area of the laminate, and the sol-gel is rinsed off the remaining area. The layer is then sintered in a belt furnace at about 660 ° C. for 25 minutes. This achieves a total sol-gel thickness of between 3 and 10 μm. This is taken over by the phosphorescent layer of Example 3 doped with 1% manganese and using 0.5-1.0 μm thick zinc sulfide.
[0156]
The rows of address lines are those with indium-tin-oxide deposited as described in Example 3 (the pattern is shown in FIG. 9). There are approximately 52 address line rows per inch, for a total of 256 rows. The spacing between the lines is 0.001 inches and the line width is 0.019 inches (center to center).
[0157]
As in the pattern shown in FIG. 10, silver is deposited on the substrate through a hole conductor through a shadow mask to form an electrical connection of a row of address lines to a row connector pad.
[0158]
The visible surface of the laminate is sealed with a silicone sealant. This silicone sealant is sprayed over the entire front surface of the display. This sealant contains M.P. G. FIG. Chemical silicone resin clear lacquer Cat # 419 is used.
[0159]
The entire display is tested by connection to a pulse generator that provides a 60 Hz 160 V square wave signal across a pair of column and row pads on a circuit provided on the back side of the substrate. Each pixel of the display is based on individual illumination and has the same consistent intensity as measured in Example 3 when supplied with voltage. Functionally impaired pixels are found out of all 17408 pixels.
[0160]
Example 6
This embodiment shows an advantageous embodiment of a laser in which the indium-tin-oxide-address lines of the EL laminate according to the invention are scribed.
[0161]
A matrix display that can be called by an address is configured on a ceramic substrate used in the following process. The ceramic substrate is 0.025 inches thick, 6 inches long and 2 inches wide, rectangular alumina and is obtained from Coors Ceramics (Grand Junction, Colorado, USA). A hole having a diameter of 0.006 inch is formed in this substrate by using a carbon dioxide laser. This pattern is shown in FIG. Some of these holes are inspected to ensure that they are all penetrated.
[0162]
Following this step, the circuit pattern shown in FIG. 5 is printed on a 325 mesh stainless steel screen (Cermalloy (Conshocken Pnnsylvania, USA) # 4740 silver platinum paste is used for this screen. ). During the printing process, the substrates are arranged on a master plate. The master plate has 0.04 inch holes drilled with the same pattern as the substrate to facilitate the supply of vacuum to the substrate holes during printing. The vacuum absorbs the paste through holes to facilitate the formation of a conductive path through the ceramic substrate after some sintering. Part of this is sintered in the atmosphere in a BTU model TFF 142-790A24 belt furnace with the temperature data recommended by the paste manufacturer, ie a maximum temperature of 850 ° C.
Following this step, the circuit reinforcement pattern shown in FIG. 7 is printed and sintered on the circuit side behind the substrate (again, using the same "Cellmalloy" conductive paste described above). This step results in a relatively thick circuit pattern in certain areas where electrical connections are subsequently made.
[0163]
Following this, the set of address lines and the connector pads are printed on the visible front side of the board. These lines extend along the entire length of the board to the connector pads (FIG. 6). Rows of connector pads are formed in this step (FIG. 6). The row of address lines and the row of column connector pads are formed from the same silver-platinum paste used in the same printed and sintered state. The substrate is located on the same master plate having the through holes of FIG. Vacuum is supplied to push out the conductive paste from below through the through holes toward the rear side of the substrate. The thickness of the sintered electrode layer is about 8 μm. There are 52 address lines per inch, for a total of 68 address lines.
[0164]
The next three layers of lead-niobate dielectric paste (Cermalloy # IP9333) are then printed and sintered at the top of the address line row with the temperature conditions (maximum temperature 850 ° C.) recommended by the manufacturer in the belt furnace. Is done. The bonding thickness of the dielectric layer is 50 μm.
[0165]
Following this step, the circuit side behind the substrate is sealed according to Example 5 whose pattern is shown in FIG.
[0166]
Next, a 3-10 μm thick layer of lead zirconate titanate (PZT) is deposited on the lead niobate dielectric paste to form a smooth surface. The sol-gel technique used and dipped according to Example 5 is used. The phosphorescent layer in the form of a thin film is deposited by known evaporation using an electromagnetic beam. The phosphorescent layer is zinc sulfate doped with 1% manganese. It is deposited over a thickness between 0.5-1 μm.
[0167]
The next step is to deposit a 300 nm thick layer of indium tin oxide (ITO) over the phosphorescent layer using known methods of electromagnetic beam evaporation.
[0168]
This ITO layer is patterned into 256 address lines using a 2 watt CW (continuous wavelength) of an argon ion laser inverted to a wavelength of 514.5 nm. The EL laminate is mounted on a movable X-axis table. This X-axis table moves the laminate perpendicular to the line scribed by the laser beam. The laser beam is moved in the Y-axis direction to scribe the line. The laser beam is focused on a 12 macrometer spot and the laser power is adjusted as follows. That is, the indium tin oxide, the underlying phosphorescent layer, and about 10% of the underlying bonded dielectric layer are adjusted to be removed at the scanned location of the (about 1.8 W) laser beam. . The scanning speed is controlled at about 100 mm / sec and 500 mm / sec to provide an address line with a gap of about 40 μm or 25 μm and a depth of 6-8 μm or 3-4 μm, respectively. The interval between address lines (for example, between line centers) is about 500 μm. Vacuum near the substrate stops evaporation and removal of material. In the pattern of the transmission electrode, as shown in FIG. 9, the removal is performed completely at once. On all displays, there are approximately 50 rows of address lines per inch, for a total of 256 columns.
[0169]
Before the ITO column lines are scribed, the silver interconnect between the front (row) connector pad and the first ITO address line is removed from the silver through the shadow mask as shown in the pattern diagram of FIG. Screen printed.
[0170]
After laser scribing, the front view side of all displays is sprayed with a protective polymer coating (silicon lysine clear lacquer manufactured by MG Chemical, cat # 419).
[0171]
The display is then tested for voltage across the selected pixel, supplied by connection to a pulsed power supply. This pulse power supply supplies a pulse voltage of 160 V at a repetition frequency of 64 Hz. Each pixel is reliably lit with a luminosity corresponding to the single pixel device of the previous embodiment.
[0172]
According to the address line of this embodiment, a higher level can be basically obtained than that obtained by the photolithographic technology.
[0173]
A typical example of a device that can be actually used has a width of the ITO address line of 180 to 205 μm and a gap between the lines of 65 to 80 μm. Starting from the above, according to the invention, gaps of 25 μm and 40 μm are produced depending on the scanning speed of the laser. Such a high solution allows for a relatively high ratio of active areas to the entire display. This is because a relatively wide ITO address line with a relatively small gap can be used.
[0174]
Example 7
This embodiment is represented by two layers that are dielectrically configured according to the present invention. However, in this embodiment, the first dielectric layer is formed from a paste having a higher dielectric constant than the paste used in the third and fourth embodiments.
[0175]
This device is constructed starting from Example 3 above, however, the first dielectric layer is formed from a lead-niobate paste. This paste is obtained as a high capacitance paste K from an electrochemical experiment using the number 4210. The sintered paste has a dielectric constant of about 10,000. The first dielectric layer has a thickness of about 50μ. A thickness of about 5μ is applied to the PTZ sol-gel layer as described in Example 3.
[0176]
This device works with a threshold voltage of 91V for minimum brightness and a luminous intensity of 50 footlamberts at 150V.
[0177]
Example 8
This embodiment is represented by two dielectrically configured layers. In this case, the first dielectric layer is formed of a lead / niobate paste, and the second dielectric layer is formed of a lead / lanthanum / zirconate / titanate paste (PLZT). This PLZT has a dielectric constant of about 1000. In this PLZT, the mass ratio of zirconium: titanium: lanthanum is 52:32:16.
[0178]
An apparatus configured as starting from Example 3 has a sol-gel layer generated as follows.
[0179]
Dissolve 120 grams of 99.5% pure lead acetate in 50 ml of glacial acetic acid. This solution is heated to 90 ° C. It is then kept at this temperature for 2 minutes before being cooled to 70 ° C. Then 55.4 grams of zirconium propoxide are added and the solution is heated to 80 ° C and held at this temperature for 1 minute. After cooling to 70 ° C., 21.8 grams of titanium isopropoxy seed are added. Next, 11.4 grams of lanthanum nitrate are dissolved in 20 ml of glacial acetic acid and added to the solution. Finally, 10 ml of ethylene glycol, 5 ml of propane-2ol and 2.5 ml of demineralized water are added to stabilize the solution and adjust the viscosity to the appropriate value.
[0180]
The PLZT sol-gel layer is used for the first dielectric layer formed by dipping by means similar to that described in Example 3 above. The dipped part is sintered at 600 ° C. to convert to a second layer for PLZT. Four layers of PLZT are used by continuous dipping and sintering as described above to create a sufficiently smooth surface for the deposition of the phosphorescent layer. A total thickness of 5μ is obtained.
[0181]
The device works with a threshold voltage of 75V and a luminosity of 37 footlamberts at 150V.
[0182]
All statements made so far are indicative of the level of skill required in the art requiring skill. All descriptions are embodied with the same scope of reference as each individual description is set forth in detail and individually to be referred to herein by relationship.
[0183]
The technical terms and expressions used herein are used as terms of description and are not intended to be limiting. Neither is the use of such terminology and language emphasized to the extent corresponding to the features illustrated and described above. It is to be understood that the scope of the invention is to be limited and expressly defined in the appended claims.
[0184]
【The invention's effect】
In accordance with the present invention, there is provided an improved electroluminescent laminate dielectric layer structure and a method of producing the same.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a laminate structure including two dielectric layers of the present invention.
FIG. 2 is a plan view of the laminate structure of FIG.
FIG. 3 is a cross-sectional view of a laminate structure taken along a row electrode, showing an advantageous embodiment of connecting a column electrode address line and a row electrode address line to a voltage drive component of a voltage drive circuit.
FIG. 4 is a plan view of a rear substrate provided with an advantageous pattern of through holes for electrically connecting an address line and a voltage driving component of a driving circuit.
FIG. 5 is a plan view of an advantageous drive circuit pattern printed on the back side of the back substrate.
FIG. 6 is a plan view of column electrodes and row paths printed on the front side of the back substrate.
FIG. 7 is a plan view of a circuit path reinforcement pattern advantageously printed on the drive circuit pattern of FIG. 5;
FIG. 8 is a plan view of a sealing glass pattern advantageously printed on the drive circuit patterns and circuit path reinforcement patterns of FIGS. 5 and 7;
FIG. 9 is a plan view of a row electrode line pattern.
FIG. 10 is a plan view of the electrical connections printed between the row tracks of FIG. 9 and the row paths of FIG. 6;
[Explanation of symbols]
10 Dielectric layer structure
12 Substrate
14 Back electrode
18. First dielectric layer
20 Second dielectric layer
22 phosphorescent layer
24 Front electrode
26 Seal layer

Claims (99)

An EL laminate having a rear substrate that is sufficiently rigid to support the following layers that are sequentially formed,
A back electrode,
A flat dielectric layer on the back electrode,
A flat phosphorescent layer,
A flat front electrode,
Has,
The dielectric layer has a dielectric strength S of greater than about 1.0 × 10 ⁶ V / m and a dielectric constant such that the ratio of the dielectric constant of the dielectric layer to the dielectric constant of the phosphorescent layer is greater than about 50: 1. to have the door, smooth second to fill the first dielectric layer surface of the hole provided in the first dielectric layer and the first dielectric layer on a thick film formed by generated by a ceramic material that is sintered With a dielectric layer of
The dielectric layer comprising the first dielectric layer and the second dielectric layer has a thickness defined by the formula d ₂ = V / S and sufficient to prevent dielectric breakdown during operation, wherein: d ₂ is the first dielectric layer and the thickness of the dielectric layer comprising a second dielectric layer, V is the maximum applied voltage,
The EL laminate, wherein the smooth second dielectric layer plane has a surface undulation that has not changed by more than about 0.5 microns over about 1000 microns. Wherein _{d 2} is laminate according to claim 1, characterized in that in the range of 10 to 300 microns. The laminate of claim 2, wherein said phosphorescent layer has a thickness in the range of 0.2 to 2 microns. Wherein _{d 2} is laminate according to claim 2 or 3, wherein the in the range of 20 to 150 microns. The dielectric layer is the dielectric layer thickness and the phosphorescent layer thickness ratio of about 20: 1 to 500: according to claim 2 or 4, characterized in that it has a thickness such that is within the first range The laminate according to any one of the above. The ratio of the dielectric constant of the dielectric layer to the dielectric constant of the phosphorescent layer is greater than about 100: 1, and the dielectric layer has a ratio of the dielectric layer thickness to the phosphorescent layer thickness of about 40: 1 to 300: 1. 6. A laminate according to claim 5, having a thickness in the range of: The phosphorescent layer is a thin film layer sandwiched between a front electrode and a back electrode, the front electrode is made transparent, and the phosphorescent layer is separated from the back electrode by the dielectric layer. The laminate according to claim 3, wherein The laminate of claim 7, wherein the dielectric layer has a dielectric constant greater than about 500. Laminate according to claim 1 or 8, wherein the dielectric layer is formed by at least two layers. The laminate of claim 9, wherein the first and second dielectric layers are comprised of a ferroelectric ceramic material. The laminate of claim 10, wherein the second dielectric layer has a dielectric constant of at least 20 and a thickness of at least about 2 microns. The laminate of claim 11, wherein the first dielectric layer has a dielectric constant of at least 1000 and the second dielectric layer has a dielectric constant of at least 100. The laminate of claim 12, wherein said second dielectric layer has a thickness in the range of about 2 to 10 microns. 14. The laminate according to claim 13, wherein the first dielectric layer and the second dielectric layer are made of a ferroelectric ceramic material having a perovskite crystal structure. 15. The laminate according to claim 1, wherein the back substrate is capable of withstanding the sintering temperature of the dielectric layer. The substrate and the back electrode are formed from a material capable of withstanding a temperature of about 850 ° C., and the first dielectric layer is formed by thick film technology and subsequent melting of the back electrode and the substrate. The laminate according to claim 15, produced by sintering at a low temperature. 17. The laminate according to claim 15, wherein the first dielectric layer is created by screen printing. 18. A laminate according to claim 16 or claim 17, wherein the second dielectric layer is produced by a sol-gel technique, followed by sintering at a temperature below the melting point of the back electrode and the substrate. . 18. The laminate according to claim 16 or 17, wherein the second dielectric layer is produced by a sol-gel technique including spin deposition or immersion followed by sintering at a temperature below the melting point of the back electrode and substrate. . 20. The device of claim 9, wherein the first dielectric layer comprises lead niobate and the second dielectric layer comprises lead zirconate-titanate or lanthanate-zirconate-lead titanate. A laminate according to any one of the preceding claims. The laminate according to any one of claims 15, 19, or 20, wherein the substrate is alumina. 22. The laminate according to claim 19, wherein the back electrode comprises a baked silver / platinum address line on an alumina substrate and the front electrode comprises an indium tin oxide address line. The laminate according to claim 22, further comprising a seal layer on the front electrode. The dielectric layer is a laminate of any one of claims 1, 2 or 8, characterized in that it has a contact with and and compatible with the phosphorescent layer. 22. The laminate according to any one of claims 9, 15, 19, and 21, wherein the second dielectric layer is in contact with and compatible with the phosphorescent layer. The laminate of claim 9, further comprising a dielectric layer between the phosphorescent layer and the front electrode. A method of forming a dielectric layer structure in an electroluminescent laminate of the type having a phosphorescent layer sandwiched between a front electrode and a back electrode, wherein the phosphorescent layer is separated from the back electrode by a dielectric layer.
Forming a rear substrate that is sufficiently rigid to support the rear electrode, the dielectric layer, the phosphorescent layer, and the front electrode that are sequentially formed;
The dielectric layer has a dielectric strength S greater than about 1.0 × 10 ⁶ V / m and a dielectric constant such that the ratio of the dielectric constant of the dielectric layer to the dielectric constant of the phosphorescent layer is greater than about 50: 1. And the dielectric layer has a thickness defined by the formula d ₂ = V / S sufficient to prevent dielectric breakdown during operation, where d ₂ is the thickness of the dielectric layer and V is One or two of thick film technology and sol-gel technology so that the maximum applied voltage and the plane of the dielectric layer has a surface relief that does not change by more than about 0.5 microns over about 1000 microns. Depositing a ceramic material in one or more layers on a rigid substrate having a back electrode by one or more techniques, followed by sintering to form a dielectric layer A method of forming a structure. The method of claim 27, wherein said _{d 2} is characterized in that in the range of 10 to 300 microns. 29. The method of claim 28, wherein said phosphorescent layer has a thickness in the range of 0.2-2 microns. Wherein _{d 2} is claim 27 or 28 method wherein a is in the range of 20 to 150 microns. 29. The method of claim 28 , wherein the dielectric layer has a thickness such that a ratio of the thickness of the dielectric layer to the thickness of the phosphorescent layer is in a range of about 20: 1 to 500: 1. 30. The method according to any of 30 . The ratio of the dielectric constant of the dielectric layer to the dielectric constant of the phosphorescent layer is greater than about 100: 1, and the ratio of the dielectric layer thickness to the phosphorescent layer thickness is in the range of about 40: 1 to 300: 1. 32. The method of claim 31 , wherein: The dielectric layer is formed in an electroluminescent laminate of the type having a thin phosphor layer sandwiched between a front electrode and a back electrode and separated from the back electrode by the dielectric layer, wherein the front electrode is transparent. 30. The method of claim 29 , wherein the method comprises: The method of claim 33, wherein the dielectric constant of the dielectric layer is greater than about 500. 35. The dielectric layer is deposited as a thick film technique on a back electrode and formed as at least two layers of a first dielectric layer and a second dielectric layer having a dielectric strength and a dielectric constant value according to claim 34 , wherein the first dielectric layer and the second dielectric layer has the surface relief provides and the thickness d ₂ combined, where, S is sum of the first and second dielectric layers 35. The method of claim 34 , wherein the dielectric strength is reduced. The method of claim 35, wherein the first dielectric layer and the second dielectric layer are made of a ferroelectric ceramic material. The method of claim 36, wherein the second dielectric layer has a dielectric constant of at least 20 and a thickness of at least about 2 microns. 38. The method of claim 37 , wherein said first dielectric layer has a dielectric constant of at least 1000 and said second dielectric layer has a dielectric constant of at least 100. The method of claim 38, wherein said second dielectric layer has a thickness in the range of about 2 to 10 microns. 40. The method of claim 39, wherein said first dielectric layer and said second dielectric layer are formed of a ferroelectric ceramic material having a perovskite crystal structure. The substrate and the back electrode are formed from a material capable of withstanding a temperature of about 850 ° C., and the first dielectric layer is deposited by a thick film technique, and then has a melting point of the back electrode or the substrate. 41. The method of claim 40 , wherein the sintering is also performed at a low temperature. 42. The method of claim 40 or claim 41, wherein the first dielectric layer is deposited by screen printing. 43. The method of claim 41 or claim 42, wherein the second dielectric layer is deposited by a sol-gel technique and then sintered at a temperature below the melting point of the back electrode or the substrate. Said second dielectric layer, claim, characterized in that the deposit in sol-gel techniques, including spin di positions or dipping, is then sintered at a temperature lower than the melting point of the rear electrode or the substrate 43 The described method. 36. The method according to claim 35, wherein the first dielectric layer is made of lead niobate and the second dielectric layer is made of lead zirconate-lead titanate or lanthanic acid-zirconate-lead titanate . 45. The method according to any one of 40 or 44 . The method according to any one of claims 40, 44, or 45 , wherein the substrate is alumina. The dielectric layer is formed in a laminate having a back electrode formed of fired silver / platinum address lines on an alumina substrate and a front electrode formed of indium tin oxide address lines. 47. The method of claim 40, 44, and 46 . The method of claim 47 , wherein the dielectric layer is formed in a laminate having a seal layer over the front electrode. 35. The method according to any one of claims 27, 29 and 34 , wherein the dielectric layer is in direct contact with the phosphorescent layer. 49. The method according to any one of claims 35, 40 and 48 , wherein the second dielectric layer is in direct contact with the phosphorescent layer. Prior to forming the dielectric layer, further forming the backing electrode on the substrate by forming the substrate that is sufficient to firmly support the laminate, and then by sintering the thick film technique The method according to any one of claims 27, 35, 40, 44, and 46 . The substrate and the back electrode are formed from a material capable of withstanding a temperature of about 850 ° C., and the first dielectric layer is deposited by a thick film technique, and then lower than the melting point of the back electrode or the substrate. The method of claim 51 , wherein the method is sintered at a temperature. The method of forming a dielectric layer structure according to claim 27 ,
The electroluminescent laminate is in an electroluminescent display, the laminate is electrically connected to a voltage drive circuit, and the laminate is a phosphorescent layer sandwiched between a front set and a back set of intersecting address lines. Wherein the back address line is formed on a substrate that is sufficient to securely support the laminate, wherein a phosphorescent layer is separated from the back address line or the front address line by said dielectric layer;
(A) a substrate which is sufficient to firmly support the laminate, and in which a plurality of through holes patterned to be located near the ends of the subsequently formed address lines are formed; Forming,
(B) forming a conductive path through each of the through holes in the substrate for electrically connecting each subsequently formed address line to a voltage drive circuit;
(C) forming a back address line separated on the substrate, the back address line having one end terminated near the through hole and being electrically connected to the conductive path;
(D) forming and sintering a dielectric layer on said back address line by thick film technology;
(E) forming a phosphorescent layer on the dielectric layer;
(F) optionally, forming a transparent dielectric layer on the phosphorescent layer;
(G) forming a spaced front address line on the underlay phosphor or the transparent dielectric layer, one end of which is terminated close to the through hole and electrically connected to the conductive path; Forming a track,
A method of forming a dielectric layer structure, further comprising: The voltage driving circuit includes a voltage driving component, and in the step (b), the voltage driving component is provided in a circuit pattern on a back surface of a substrate, and an output side of the component is connected to a front surface by a conductive path passing through each through hole. 54. The method of claim 53 , wherein the circuit pattern is printed on the back surface of the substrate in a pattern such that it is connected to the address lines and the back address lines. In the step (b), a conductive material is deposited in each of the through holes to form a front connector path and a rear connector path on both sides of the board, and the rear connector path has a rear address line printed thereon. Connected to the voltage driving component via a circuit pattern, and in the steps (c) and (g), one end of the front address line and the back address line covers the front connector path, or the additional conductive material is connected to the front connector line. 55. The method of claim 54 , wherein a deposit is made between the road and one end of the front address line and the back address line. The method of claim 55, wherein the substrate and the back address lines are formed of a material capable of withstanding a temperature of about 850 ° C. 57. The method of claim 56, wherein said substrate is opaque and said through holes are formed by a laser. The method of claim 57 , wherein said substrate is alumina. The substrate may be generally rectangular, and the through-holes may be formed around the substrate adjacent to the front and rear address line ends that are subsequently formed on at least two sides. Item 59. The method according to Item 56 or 58 . The method of claim 59 , wherein the conductive material used in steps (b) and (c) is a fired thick film paste. The conductive material in the conductive paths, the back circuit pattern, and the front and back connector paths is a fired silver / platinum paste, and the conductive material used to connect the front address lines to the front connector paths is silver. 61. The method of claim 60 , wherein In step (b), conductor paths through each of the through holes are formed from a thick film conductive paste printed in a circuit pattern on the back of the substrate to form front and rear connector paths on both sides of the substrate. The rear connector path is electrically connected to a voltage driving circuit, and the front connector path is formed by the rear address line formed in step (c). 55. The method according to claim 54 , wherein said front address line is electrically connected to a front connector track having a second conductive material in step (g). 63. The method of claim 62 , wherein said substrate and said back address line are formed of a material capable of withstanding a temperature of about 850C. 63. The substrate according to claim 62, wherein the substrate is generally rectangular and the through holes are formed around the substrate adjacent to the front address line end and the rear address line end on at least two sides of the substrate. Or the method of 63 . The thick film paste in steps (b) and (c) is a baked silver platinum paste, and the second conductive material in step (g) is silver. 64. The method of claim 64 . 54. The dielectric layer is formed as at least two layers, the first dielectric layer is deposited and sintered on the back electrode by thick film technology, and has a dielectric strength and dielectric constant value according to claim 53 , Here, the dielectric strength is the combined dielectric strength of the first dielectric layer and the second dielectric layer, and the second dielectric layer is deposited on the first dielectric layer by a sol-gel technique and subsequently fired. 54. A surface coupled to and adjacent to the phosphorescent layer of claim 53 , wherein the first dielectric layer and the second dielectric layer have a combined thickness of claim 53. A method according to claim 53 or 65 . The first dielectric layer and the second dielectric layer are made of a ferroelectric ceramic material having a perovskite crystal structure, the first dielectric layer has a dielectric constant of at least 1000, and the second dielectric layer 67. The method of claim 66 , wherein has a dielectric constant of at least 100 and a thickness of about 2-10 microns. 68. The method of claim 67, wherein the first dielectric layer is created by screen printing and sintering of a thick film dielectric paste, and wherein the second dielectric layer is created by a sol-gel technique followed by firing. the method of. 69. The method of claim 68 , wherein said first dielectric layer comprises lead niobate and said second dielectric layer comprises lead zirconate-zirconate-titanate. One or more dielectric layers are formed in an electroluminescent laminate having a phosphorescent layer sandwiched between a set of front and back sets of intersecting address lines, wherein the back address lines are formed on a back substrate. Overlying, wherein the phosphorescent layer is separated from a back address line by one or more dielectric layers, and wherein the front address line is formed in an electrode pattern from a transparent conductive material;
A focused laser beam is applied to the area of the pattern to be removed of the transmissive conductive material, the phosphorescent layer is removed directly throughout its thickness, and a portion of one or more dielectric layers is directly applied. The laser beam is substantially removed by the transparent conductive material such that the transparent conductive material is removed indirectly and indirectly throughout its thickness, and the removal occurs in the area of the pattern to be removed. Having a wavelength that is not absorbed but is absorbed by one or more dielectric or phosphorescent layers,
29. The method of claim 27 , wherein the electrode pattern is formed by moving one or both of the laminate and the laser beam relative to each other. The dielectric layer comprises at least two layers, a first dielectric layer is formed on the back electrode, has a dielectric constant greater than about 500, and a second dielectric layer is formed on the first dielectric layer. are generated, claim 70 has adjacent surfaces phosphorescence layer, wherein the first dielectric layer and the second dielectric layer ranging from a total of 10 to 300 microns thickness d ₂ 71. The method of claim 70, wherein S is the combined dielectric strength of the first dielectric layer and the second dielectric layer. The first dielectric layer and the second dielectric layer are made of a ferroelectric ceramic material having a perovskite crystal structure, the first dielectric layer has a dielectric constant of at least 1000, and the second dielectric layer 72. The method of claim 71 , wherein has a dielectric constant of at least 100 and a thickness of about 2-10 microns. Said first dielectric layer is produced by sintering a screen printed thick film dielectric paste and the second dielectric layer according to claim 72, wherein the produced by calcination followed by the sol-gel technique the method of. 74. The method of claim 73 , wherein said first dielectric layer comprises lead niobate and said second dielectric layer comprises lead zirconate-lead titanate or lanthanate-zirconate-lead titanate. 75. The method of claim 70 or claim 74, wherein the transparent conductive material is indium tin oxide. An EL laminate having a rear substrate that is sufficiently rigid to support the following layers that are sequentially formed,
A back electrode,
A flat dielectric layer on the back electrode,
A flat phosphorescent layer,
A flat front electrode,
Has,
The dielectric layer has a first dielectric layer created by a thick film technique and a second dielectric layer created by a sol-gel technique, wherein the second dielectric layer is provided on the first dielectric layer. The dielectric layer, which fills the holes in the dielectric layer and comprises the first and second dielectric layers, has a dielectric strength S of greater than about 1.0 × 10 ⁶ V / m ; dielectric layer and before comprises the second dielectric layer Ki誘 conductive layer dielectric and phosphor layers of the dielectric constant of the ratio of about 50: to have a larger such permittivity than 1, the sintered Produced by ceramic material,
The dielectric layer comprising the first dielectric layer and the second dielectric layer has a thickness defined by the formula d ₂ = V / S and sufficient to prevent dielectric breakdown during operation, wherein: d ₂ is characterized in that said first dielectric layer and the thickness of the dielectric layer comprising a second dielectric layer, V is the maximum applied voltage, EL laminate. Said d ₂ 77. The laminate of claim 76, wherein is in the range of 10 to 300 microns. 78. The laminate of claim 77, wherein said phosphorescent layer has a thickness in the range of 0.2 to 2 microns. Said d ₂ 79. The laminate of claim 77 or 78, wherein is in the range of 20 to 150 microns. 80. The method of claim 77 or 79, wherein the dielectric layer has a thickness such that a ratio of the thickness of the dielectric layer to the thickness of the phosphorescent layer is in a range of about 20: 1 to 500: 1. The laminate according to any one of the above . The ratio of the dielectric constant of the dielectric layer to the dielectric constant of the phosphorescent layer is greater than about 100: 1, and the dielectric layer has a ratio of the dielectric layer thickness to the phosphorescent layer thickness of about 40: 1 to 300: 1. 81. The laminate of claim 80 having a thickness such that the thickness is within the range: The phosphorescent layer is a thin film layer sandwiched between a front electrode and a back electrode, the front electrode is made transparent, and the phosphorescent layer is separated from the back electrode by the dielectric layer. 79. The laminate of claim 78, wherein the laminate is: 83. The laminate of claim 82, wherein said dielectric layer has a dielectric constant greater than about 500. 84. The laminate according to claim 76 or claim 83, wherein said dielectric layer is formed by at least two layers. 85. The laminate of claim 84, wherein said first dielectric layer and said second dielectric layer are comprised of a ferroelectric ceramic material. 86. The laminate of claim 85, wherein said second dielectric layer has a dielectric constant of at least 20 and a thickness of at least about 2 microns. 87. The laminate of claim 86, wherein said first dielectric layer has a dielectric constant of at least 1000 and said second dielectric layer has a dielectric constant of at least 100. 88. The laminate of claim 87, wherein said second dielectric layer has a thickness in the range of about 2 to 10 microns. 89. The laminate of claim 88, wherein said first and second dielectric layers are made of a ferroelectric ceramic material having a perovskite crystal structure. The substrate and the back electrode are formed from a material capable of withstanding a temperature of about 850 ° C., and the first dielectric layer is formed by thick film technology and subsequent melting of the back electrode and the substrate. 90. The laminate of claim 89, produced by sintering at a low temperature. The laminate of claim 90, wherein the first dielectric layer is created by screen printing. 92. The laminate according to claim 90 or 91, wherein the second dielectric layer is created by a sol-gel technique, followed by sintering at a temperature below the melting point of the back electrode and the substrate. . 93. The system according to claim 84, wherein the first dielectric layer comprises lead niobate and the second dielectric layer comprises lead zirconate-titanate or lanthanate-zirconate-lead titanate. A laminate according to any one of the preceding claims. The laminate according to any one of claims 90, 92, and 93, wherein the substrate is alumina. 95. The laminate of any of claims 92 or 94, wherein the surface of the second dielectric layer has a surface relief of less than about 0.5 microns over about 1000 microns. The laminate of claim 95, wherein the back electrode comprises a fired silver / platinum address line on an alumina substrate and the front electrode comprises an indium tin oxide address line. The laminate according to claim 96, further comprising a seal layer on the front electrode. The laminate of claim 84, further comprising a dielectric layer between the phosphorescent layer and the front electrode. A method of forming a dielectric layer structure in an electroluminescent laminate of the type having a phosphorescent layer sandwiched between a front electrode and a back electrode, wherein the phosphorescent layer is separated from the back electrode by a dielectric layer.
Forming a rear substrate that is sufficiently rigid to support the sequentially formed back electrode, the dielectric layer, the phosphorescent layer, and the front electrode;
Depositing a ceramic material by a thick film technique to create a first dielectric layer on a rigid substrate having a back electrode, followed by sintering, and then creating a second dielectric layer on said first dielectric layer The dielectric layer is formed by depositing the ceramic material by the sol-gel technique and then sintering, the dielectric layer combined by the two layers having a thickness of less than about 1.0 × 10 ⁶ V / m. Have a large dielectric strength S and a dielectric constant such that the ratio of the dielectric constant of the dielectric layer to the dielectric constant of the phosphorescent layer is greater than about 50: 1, and wherein the dielectric layer has the formula d ₂ = V / S defined having a sufficient thickness to prevent dielectric breakdown during operation, where, d ₂ forming a dielectric layer structure, wherein a thickness of said dielectric layer, V is the maximum applied voltage how to.

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