JP3558746B2 - Nonvolatile memory test method and test apparatus - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for testing a nonvolatile memory, and more particularly to a method and an apparatus for performing a data read test on a mask ROM, an EPROM, an E ² PROM, and the like.
[0002]
[Prior art]
In recent years, with the increase in the capacity of nonvolatile memories such as mask ROMs, EPROMs, and E ² PROMs, the amount of data used as an expected value in a data read test has become enormous. On the other hand, there is a strong demand for shorter delivery times for supplying products to customers. For this reason, in a data read test of a nonvolatile memory, it is necessary to efficiently perform a test using a plurality of different address patterns in order to detect a failure in various modes or to shorten a test time. It becomes.
[0003]
FIG. 4 shows a configuration diagram of a ROM tester according to a conventional example. In FIG. 4, reference numeral 300 denotes a ROM tester, and 1 denotes an expected value data memory for storing expected value data. 2 is an address pattern generator for generating an address pattern, 3 is a 0/1 determiner for determining "0" or "1" of read data (DATA) of the memory under test 18, and 4 is expected value data. Is a comparator for comparing the output signal of the comparator 4 with the read data. Reference numeral 6 denotes a CPU (Central Processing Unit) that controls input / output of the expected value data memory 1 and the address pattern generator 2.
[0004]
The memory 1 stores expected value data in which a value expected to be read from the memory under test 18 is compared in units of one address when a storage address of a write value to the memory under test 18 is specified in a specific order. ing. For example, the expected value data is a value that will be read when a certain address #X is specified, and is equal to the value written to the address #X when the memory under test 18 is programmed.
[0005]
Next, the operation of the ROM tester will be described. First, while the address output terminal of the ROM tester 300 is connected to the address input terminal of the memory under test 18, and the data output terminal of the memory under test 18 is connected to the data input terminal of the ROM tester 300, the control of the CPU 6 is performed. According to the instruction, the address pattern generator 2 generates an address pattern (ADD), for example, # 0000 to #FFFF. Then, the generator # 2 specifies the address # 0000 in the memory under test 18, and the CPU 6 points the address (ADD) # 0000 of the expected value data memory 1 by the pointer.
[0006]
The data read from the memory under test 18 is determined by the 0/1 determiner 3 as “0” or “1” for each output bit, and the data, for example, “# 00” is compared with the comparator 4. Is output to The comparator 4 compares the expected value data of the address # 0000, for example, “# 00” with the read data = “# 00”. This comparison is sequentially performed for each address, and the result is determined by the determiner 5. Thereby, the quality of the memory under test 18 is determined.
[0007]
[Problems to be solved by the invention]
However, in the method of sequentially comparing read data and expected value data in address units, the test time increases because the number of data comparisons becomes enormous with the increase in the capacity of the nonvolatile memory. In addition, since the memory 1 must store expected value data for all addresses of the memory under test 18, it is necessary to prepare a memory having the same capacity as the memory under test 18. An increase in the memory capacity of the memory under test 18 necessitates an increase in the expected value data memory 1.
[0008]
Therefore, when the expected value data memory for the capacity of the memory under test cannot be prepared, the address area of the memory under test 18 must be divided and the data read test must be performed a plurality of times, and the test process and the test cost are reduced. This leads to a problem that the product delivery to a customer is delayed.
The present invention has been made in view of the problems of the conventional example, and makes it possible to perform a read test in a short time and easily without successively comparing read data and expected value data in address units. It is an object of the present invention to provide a method for testing a nonvolatile memory and a test apparatus therefor.
[0009]
[Means for Solving the Problems]
According to the method for testing a nonvolatile memory of the present invention, a value expected to be sequentially read from a memory under test in which a predetermined data pattern is written by a plurality of addressing patterns including at least one addressing pattern including an overlapping address Were prepared by a specific calculation, and when testing the memory under test, one expected value was selected from the plurality of expected values, and the selected expected value was created. The values sequentially read out from the memory under test by the same addressing pattern are combined by the specific calculation to create an actual value, and the selected expected value is compared with the actual value created in the previous period. And
[0010]
In the above-described method for testing a nonvolatile memory, the plurality of addressing patterns include at least a first pattern in which addresses are sequentially increased or decreased one by one from the lowest or highest address, and discrete addresses. And a second pattern designating the second pattern, wherein the second pattern includes an overlapping address.
[0011]
Further, in the above-described method for testing a nonvolatile memory, the specific calculation is performed by any one of addition, subtraction, multiplication, or division, or a combination of these arithmetic operations.
The non-volatile memory test apparatus according to the present invention is configured such that a value to be sequentially read from a memory under test in which a predetermined data pattern is written by a plurality of addressing patterns including at least one addressing pattern including an overlapping address is provided. Storage means for storing a plurality of expected values obtained by a specific calculation, a selection means for selecting one of the plurality of expected values from the storage means, and the expected value selected by the selection means Designating means for designating an address of the memory under test by the corresponding address designating pattern; calculating means for creating an actual value by combining the values sequentially read from the address designated by the designating means by the specific calculation; Comparing means for comparing an expected value from the storage means with an actual value from the calculating means; Characterized in that the output stage includes a judging means for judging correctness of the value written to the memory under test.
[0012]
In the method for testing a nonvolatile memory according to the present invention, in order to prepare in advance a criterion for determining whether a value written to the memory under test is correct, values expected to be sequentially read from the memory under test are first summarized by a specific calculation. Create expected values. The specific calculation at this time is performed by addition, subtraction, multiplication, division, or a combination of these arithmetic operations. The storage addresses of the memory under test are specified in a specific order.
[0013]
When testing the memory under test, the storage address is specified for the actual memory under test in the same specific order as when the expected value was created, and the values sequentially read out by this specification are specified. The actual value is created collectively by the calculation of. Thereafter, the expected value is compared with the actual value to determine whether the value written to the memory under test is correct.
[0014]
As described above, according to the test method of the present invention, the expected value obtained by summing the values expected to be read from the memory under test in a specific order by the specific calculation and the sequential reading from the actual memory under test in the same order as the expected value are obtained. Since the output value is compared with an actual value obtained by a specific calculation, as in the conventional example, one value sequentially designated and read out for each storage address and one expected value expected therefrom are compared with one expected value. Can be compared at once without comparing values stored in the storage address group unit. Therefore, since the number of comparisons can be greatly reduced, even if the capacity of the memory under test is increased, it is possible to mask ROM, EPROM, a simple data reading test, such as E ² PROM performed in a short time.
[0015]
Further, in the second test method of the present invention, a plurality of expected values are created when the order of designating the storage addresses of the memory under test is changed to several types, and one expected value is created from the plurality of expected values. Values are selected, and the storage addresses of the memory under test are specified in the order in which the storage addresses were specified when the expected value was created.
Therefore, by changing the order in which the storage addresses of the memory under test are specified, the storage addresses of the memory under test can be stored in a plurality of different orders, as compared with the case where the storage addresses of the memory under test are specified in a single specific order. The test can be performed by imitating the user's usage. As a result, it is possible to perform a data read test in consideration of the device characteristics depending on the address designation order of the memory under test, for example, the read speed and the power supply margin.
[0016]
Further, according to the test apparatus of the present invention, it is sufficient to secure a memory capacity for storing an expected value obtained by a specific calculation of a value expected to be read from the memory under test. The capacity can be reduced. By reducing the memory capacity, the cost of the test apparatus can be reduced.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, an embodiment of the present invention will be described with reference to the drawings. 1 to 3 are explanatory diagrams of a method for testing a nonvolatile memory and an apparatus for testing the same according to an embodiment of the present invention.
(1) First Embodiment FIG. 1 is a configuration diagram of a ROM tester according to a first embodiment of the present invention, and FIG. 2A shows the relationship between the address pattern and the expected checksum value. An explanatory diagram is shown. In FIG. 1, reference numeral 11 denotes a checksum expected value memory for storing a checksum expected value D1 obtained by adding a value expected to be read from the memory under test 18 in advance, and is an example of a storage unit. The checksum expected value D1 serves as a criterion for determining whether the value “0” or “1” written in the memory under test 18 is correct.
[0018]
In the present embodiment, as shown in FIG. 2A, the expected checksum value D1 is, for example, “# 3FFFFF”. This value “# 3FFFFF” is the storage address of the write value “0” or “1” for each bit in the memory under test 18, for example, address # 0000 when the memory capacity is 256K (64K words × 8 bits). When values # 0 to #FFFF are specified in a specific order, values "0" or "1" for each output bit expected to be read from the memory under test 18 are added in advance for all specified addresses. “# 3FFFFF” is a value represented by a hexadecimal number, and is represented by “0011 1111 1111 1111 1111 1111” in a binary number. The expected checksum value is obtained by taking the one's complement or the two's complement of the sum of the values "0" or "1" expected to be read from the memory under test 18 for each output bit.
[0019]
Reference numeral 12 denotes an address pattern generator that specifies storage addresses of the memory under test 18 in a specific order, and is an example of a specifying unit. The generator 12 generates, for example, address patterns in the order shown in FIG. Reference numeral 13 denotes a 0/1 determiner for determining "0" or "1" of read data (DATA) of the memory under test 18 for each output bit. Reference numeral 14 denotes a memory under test specified by the address pattern generator 12. This is a checksum value calculator that sequentially adds values (readout data) from storage addresses of 18 and outputs a checksum value Dx, and is an example of an adding unit.
[0020]
A comparator 15 compares the expected checksum value D1 with the checksum value Dx, and is an example of a comparing unit. Reference numeral 16 denotes a determiner for determining the quality of the memory under test 18 from the output signal of the comparator 15, and is an example of a determination unit. Reference numeral 17 denotes a CPU (Central Processing Unit) that controls input / output of the checksum expected value memory 11 and the address pattern generator 12. The CPU 17 outputs, for example, a control signal S1 for starting the designation start to the address pattern generator 12, a control signal S2 for permitting reading to the checksum expected value memory 11, and an output to the comparator 15. A control signal S3 for permitting is output, and a control signal S4 for permitting the determination is output to the determiner 16.
[0021]
Next, the operation of the test apparatus for the ROM test method according to the present embodiment will be described. First, with the checksum expected value D1 serving as a criterion for determining whether the value “0” or “1” written in the memory under test 18 is stored in the memory 11, the address pattern generator 12 is controlled by the control signal S1 from the CPU 17. 2 generates addresses # 0000 to #FFFF in the order shown in FIG. 2A, and sequentially assigns these address addresses # 0000 to #FFFF to the actual memory under test 18 in the same manner as when the checksum expected value D1 is created. Specify for. As a result, the data (DATA) sequentially read from the memory under test 18 is determined for each bit by the 0/1 determiner 13, and the read data “0” or “1” determined here is sent to the arithmetic unit 14. Is output.
[0022]
In the arithmetic unit 14, all the data sequentially read out according to the designation of the addresses # 0000 to #FFFF are added, and the added value is output to the comparator 15 as a checksum value Dx. The comparator 15 reads the expected checksum value D1 from the memory 11 based on the control signal S2 from the CPU 17, and compares whether the expected checksum value D1 matches the checksum value Dx. You. This comparison is performed only once for all designated addresses by the control signal S3 from the CPU 17, and the result is determined by the determiner 16 by the control signal S4 from the CPU 17.
[0023]
For example, when the expected checksum value D1 and the checksum value Dx match, the memory under test 18 is determined to be “good”, and when D1 and Dx do not match, it is determined to be “bad”. Thus, the correctness of the value “0” or “1” written in the memory under test 18 can be comprehensively determined.
In this manner, in the ROM tester according to the first embodiment of the present invention, the checksum expected value D1 obtained by adding the value expected to be read from the memory under test 18 and the read-out value from the actual memory 18 under test are sequentially read. Since the checksum value Dx obtained by adding the output values is compared, one read data sequentially designated and read for each storage address as in the conventional example and one expected value data expected therefrom are compared. Can be compared with each other without individually comparing the sum values of all the designated addresses.
[0024]
Therefore, even if the capacity of the memory under test 18 is increased, it is possible to mask ROM, ^EPROM, a simple data reading test, such as E 2 PROM performed in a short time.
Further, according to the apparatus of the present embodiment, it is sufficient to secure a memory capacity for storing the expected checksum value D1, so that the memory can be reduced as compared with the conventional example, and the test apparatus can be reduced in cost.
[0025]
(2) Second Embodiment FIG. 3 is a configuration diagram of a ROM tester according to a second embodiment of the present invention, and FIG. 2B is a diagram for explaining the contents of the checksum expected value memory. Is shown.
In the second embodiment, unlike the first embodiment, n kinds of checksum expected values are prepared in advance, selected, and a data read test of the memory under test 18 is performed.
[0026]
In FIG. 3, reference numeral 200 denotes a second ROM tester, and reference numeral 21 denotes a checksum expected value memory for storing n types of expected checksum values D1 to Dn, which is an example of a storage unit. In the present embodiment, the expected checksum value D1 is “# 1FFFFF”, as shown in FIG. The expected value "0" or "1" for each bit is added in advance for all designated addresses.
[0027]
The checksum expected value D2 is, for example, “# 3FFFFF”. When the addresses # 0000 to #FFFF are specified in the same order as in the first embodiment, the checksum is read out from the memory under test 18 for each bit. The expected value "0" or "1" is added in advance for all designated addresses.
The expected checksum value D3 designates the start address # 0000 and the end address #FFFF, designates the address # 0000 again, then designates the next address # 0001, and designates the address in this order. Then, the value "0" or "1" expected to be read for each bit from the memory under test 18 is added in advance for all designated addresses. Thus, the checksum expected values D1 to Dn are created and changed by changing the address designation. The expected values D1 to Dn are stored in the memory 21.
[0028]
A selector 22 selects one of the expected checksum values from the expected checksum memory 21 and is an example of a selection unit. For example, the selector 22 selects one expected checksum value from n types of expected checksum values D1 to Dn according to the control signal S2. The control signal S2 is output from the CPU 28, and the signal S2 is correlated with the control signal S1. For example, when selecting the checksum expected value D1, the CPU 28 outputs to the address pattern generator 23 a control signal S1 for sequentially specifying the addresses # 0000 to #FFFF. Note that components having the same names as those in the first embodiment have the same functions, and a description thereof will be omitted.
[0029]
Next, the operation of the test apparatus for the ROM test method according to the present embodiment will be described. For example, when a data reading test is performed by selecting the checksum expected value D3 from the n types of checksum expected values D1 to Dn, first, whether the value “0” or “1” written in the memory under test 18 is correct or not is determined. With the checksum expected values D1 to Dn stored in the memory 21, the address signal generator 23 generates the checksum expected value D3 for the memory 18 under test by the control signal S1 from the CPU 28. Thus, the address is specified for the actual memory under test 18. As a result, the data (DATA) sequentially read from the memory under test 18 is determined for each bit by the 0/1 determiner 24, and the read data “0” or “1” determined here is sent to the arithmetic unit 25. Is output.
[0030]
In the arithmetic unit 25, all the data sequentially read out according to the designation of the address are added, and the added value is output to the comparator 26 as a checksum value Dx. Further, the selector 22 selects the expected checksum value D3 from the memory 21 according to the control signal S2 from the CPU 28, and outputs this expected value D3 to the comparator 26. The comparator 26 compares whether the expected checksum value D3 matches the checksum value Dx. This comparison is performed only once for all designated addresses by the control signal S3 from the CPU 28, and the result is determined by the determiner 16 by the control signal S4 from the CPU 28.
[0031]
For example, when the selected checksum expected value D3 and the calculated checksum value Dx match, the memory under test 18 is determined to be “good”, and when D3 and Dx do not match, the memory 18 is determined to be “bad”. Is determined. Thus, the correctness of the value “0” or “1” written in the memory under test 18 can be comprehensively determined.
In this manner, in the ROM tester according to the second embodiment of the present invention, one out of n types of checksum expected values D1 to Dn when the order of designating the storage addresses of the memory under test 18 is changed. One of the two expected checksum values is selected, and the storage addresses of the memory under test 18 are specified in the order in which the storage addresses were specified when the checksum expected values were created.
[0032]
For this reason, for example, in the case where the test is performed using the checksum expected values D1 to Dn, a plurality of orders having different storage addresses of the memory under test 18 are compared with the case where the test is performed using the single checksum expected value D1. , A test can be performed that simulates the usage situation of a user who does not always read data in the same order.
As a result, it is possible to perform a data read test in consideration of device characteristics depending on the address pattern of the memory under test 18, for example, a read speed and a power supply margin. Further, the quality of the memory under test 18 can be determined using a plurality of address patterns without holding the expected value data for all the addresses unlike the conventional example.
[0033]
In the present embodiment, the method of selecting the expected checksum value from the memory 21 in accordance with the control signal S2 from the CPU 28 has been described. However, the identification signal S5 is transferred from the address pattern generator 23 to the selector 22, and The corresponding expected checksum value may be selected from the memory 21. This identification signal S5 is a signal for identifying which address pattern has been applied, and as shown in FIG. 2B, it is necessary to associate the address pattern with the expected checksum value in advance.
[0034]
Further, in each embodiment of the present invention, a case has been described in which a test is performed using a checksum expected value obtained by adding all values that would be read when all the storage addresses of the memory under test 18 are specified in a specific order. However, it is also possible to perform a test for each memory cell block using a checksum partial expected value obtained by adding a partial value that would be read when the storage address is divided and specified.
[0035]
Furthermore, in each embodiment of the present invention, the case of addition has been described for a specific calculation. However, the present invention is not limited to this, and may be performed by any of subtraction, multiplication, division, or a combination of these arithmetic operations.
[0036]
【The invention's effect】
As described above, in the test method of the nonvolatile memory of the present invention, the values that are expected to be read in a specific order are specified by the specific calculation, and the values that are actually read are specified in the same order. Is compared with the actual value summarized by the calculation of the above, so that one value sequentially designated and read for each storage address of the memory under test and one expected value expected therefrom are individually Values can be compared at once without storing the values in the storage address group unit. Therefore, since the number of comparisons can be greatly reduced, a data read test can be performed in a short time even when the capacity of the memory under test increases.
[0037]
According to the test method of the present invention, one expected value is selected from a plurality of expected values when the order of designating the storage addresses of the memory under test is changed, and when the selected expected value is created. Since the storage address of the memory under test can be specified in the same order, it is possible to perform a test imitating the use situation of the user, and it is also possible to detect a defect depending on the address pattern.
[0038]
Furthermore, in the test apparatus of the present invention, the expected value obtained by collecting values expected to be read from the memory under test in a specific order by specific calculation may be stored, so that the memory capacity of the storage unit can be reduced. Therefore, the mask ROM of a large capacity, simple and inexpensive test device to enable data reading test, such as EPROM and ^E 2 PROM can be provided.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a ROM tester according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram showing a relationship between an address pattern and a checksum expected value memory according to each embodiment of the present invention.
FIG. 3 is a configuration diagram of a ROM tester according to a second embodiment of the present invention.
FIG. 4 is a configuration diagram of a ROM tester according to a conventional example.
[Explanation of symbols]
1 Expected value data memory, 11, 21 Checksum expected value memory, 2, 12, 23 ... Address pattern generator, 3, 13, 24 ... 0/1 decision unit, 4, 14, 25 ... Adder, 15 , 26 ... Comparator, 5, 16, 27 ... Judge, 6, 17, 28 ... CPU, 100, 200, 300 ... ROM tester.

Claims (4)

A plurality of expected values obtained by sequentially calculating values expected to be sequentially read from a memory under test in which a predetermined data pattern is written by a plurality of addressing patterns including at least one addressing pattern including an overlapping address by a specific calculation Has been created,
When testing the memory under test, one expected value is selected from the plurality of expected values,
Creating an actual value by combining the values sequentially read from the memory under test by the specific calculation by the same addressing pattern as when the selected expected value was created,
A method for testing a non-volatile memory, comprising comparing the selected expected value with an actual value created in the previous period. The plurality of addressing patterns include at least a first pattern of sequentially increasing or decreasing addresses one by one from the lowest or highest address, and a second pattern of discretely specifying addresses. The method according to claim 1, wherein the second pattern includes an overlapping address. The method according to claim 1, wherein the specific calculation is performed by any one of addition, subtraction, multiplication, or division, or a combination of these arithmetic operations. A plurality of expected values in which values expected to be sequentially read from a memory under test in which a predetermined data pattern is written by a plurality of addressing patterns including at least one addressing pattern including an overlapping address are collected by a specific calculation Storage means for storing
Selecting means for selecting one of the plurality of expected values from the storage means,
Specifying means for specifying an address of the memory under test by the addressing pattern corresponding to the expected value selected by the selecting means;
Calculating means for creating an actual value by combining the values sequentially read from the address specified by the specifying means by the specific calculation;
Comparison means for comparing the expected value from the storage means and the actual value from the calculation means,
A non-volatile memory test device, comprising: a determination unit configured to determine whether a value written to the memory under test is correct or not based on an output result of the comparison unit.

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