JP2004199827A - Data write-in device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data write-in device in which common data written in a memory for reading only and individual data are written in a chip with one process and which is suitable for mass production. <P>SOLUTION: A data write-in part 20 in the data write-in device 1 is provided with a write-in part 30 writing data in a chip 10, a common data memory part 40 storing common data such as firmware or the like, an individual data memory part 50 storing individual data such as MAC address or the like, a user interface part 60 specifying write-in regions of common data for each chip and individual data, and a control part 70 delivering the common data or the individual data to the write-in part with chip specification and a write-in address based on the discrimination of the region in which the common data or the individual data is written. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a data writing device for a read-only memory, and more particularly to a data writing device for writing common data commonly used by devices such as firmware and individual data individually used such as a MAC address to a read-only memory chip in one step. Equipment related.
[0002]
[Prior art]
A read-only memory such as a FLASH memory, an EPROM, and an NVRAM stores common data such as firmware and BIOS and individual data such as a MAC address for identifying a device. The same data is stored in the common data storage portion in common to many devices, and the individual data storage portion stores different data for each device. Each device has a read-only memory chip. A data writing device that takes into account writing of common data and individual data on one chip and mass production of the chip corresponding to the device is required.
[0003]
For this reason, in the related art, a step of creating a master including common data and individual data and a step of writing the master to a chip are separately performed.
[0004]
The first example is divided into a process of creating a master ROM in which common data and individual data are merged into a storage pattern, and a process of copying the master ROM to a new ROM (for example, refer to Patent Document 1). 1).
[0005]
A second example is a step of creating a master memory including control information indicating a storage area and data to be stored, and reading data from the master memory via a writing device based on the control information into a ROM. (See, for example, Patent Document 2).
[0006]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2000-30479, FIG.
[Patent Document 2]
Japanese Patent Application Laid-Open No. 1-185898 FIG.
[0007]
[Problems to be solved by the invention]
2. Description of the Related Art In general, home appliances including personal computers are equipped with a ROM in which software is written. Therefore, the operation of writing individual data to a part that does not apply mass copying, that is, a chip that requires individual data such as a MAC address, creates a master consisting of common data such as firmware and individual data for each device and stores it in ROM. Writing or writing the common data and the individual data to the chip in separate steps are performed in separate steps. Therefore, this is a factor that increases the manufacturing cost. Accordingly, a data writing device that separately creates common data and individual data, writes the data in a ROM chip in one process, and is suitable for mass production is provided.
[0008]
SUMMARY OF THE INVENTION An object of the present invention is to provide a data writing device for writing individual data and common data in a single step to a read-only memory in order to reduce the cost of manufacturing the ROM chip.
[0009]
Still another object is to simplify the operation by writing common data and individual data in a single step by serially writing data to a plurality of read-only memory chips when the data to be written to the chips has a series. In the data writing device.
[0010]
Further, another object is to manufacture a large number of read-only memory chips for individual devices, so that a portion to be duplicated is duplicated in parallel to a plurality of chips, and individual data is written in a single step by writing data for each chip in one step. In the device.
[0011]
[Means for Solving the Problems]
Therefore, in the data writing device for writing data to the chip of the read-only memory of the present invention, a writing unit for writing data by designating the chip and the address and common data to be commonly stored in the device are stored in a plurality of chips. User interface for specifying a common data memory unit to be stored, an individual data memory unit to store individual data to be individually stored in the device, a chip to be written, and a writing area for common data and individual data for each chip And control for passing the common data or the individual data to the writing unit together with the chip designation and the write address based on the determination of whether the write address of the common data and the individual data indicates an area in which the common data or the individual data is written. And a unit.
[0012]
Further, the common data section stores designation of a chip to which data is to be written, common data such as firmware, and an address for writing the common data to the chip.
[0013]
Further, the individual data section stores designation of a chip to which data is to be written, individual data such as a MAC address, and an address for writing the individual data to the chip.
[0014]
Further, the control unit includes a common data memory current address indicating an address for sequentially reading the common data memory unit, a counter for incrementing the common data current address for each read, and an address for sequentially reading the individual data memory unit. , A counter that increments the individual data current address for each read, and a write address of the common data and a write address of the individual data are stored in a common data area or an individual data area of a specified chip. A discriminating unit for discriminating which one is pointing, and selecting common data or individual data based on the discrimination result of the discriminating unit, and specifying a chip designation, the selected data, and a write address to the data writing unit. Having a selection unit to send And butterflies.
[0015]
Further, the writing unit arranges a plurality of chips of the read-only memory in order of address, and writes the common data and the individual data while maintaining a series of addresses.
[0016]
Further, the writing unit is characterized in that a plurality of chips of the read-only memory are arranged in parallel, common data is written in common to each chip in parallel, and individual data is individually written in different data for each chip.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention will be described with reference to the drawings. Referring to FIG. 1 showing a first embodiment of the present invention, a data writing device 1 includes a read-only memory chip 10 to which data is to be written, and a data writing unit 20.
[0018]
The data writing unit 20 is connected to a read-only memory chip 10 such as a FLASH memory, an EPROM, or an NVRAM, and performs a write operation. The writing unit circuit 30 performs common write processing. The common data memory stores common data to be written in the read-only memory chip 10. Unit 40, an individual data memory unit 50 for storing individual data to be written to the read-only memory chip 10, and a display area for writing common data and individual data, an instruction input of a write operation, and a write state and a write result. It is configured to include a user interface unit 60 and a control unit 70 that controls the common data memory unit 40, the individual data memory unit 50, and the writing unit 30 based on instructions from the user interface unit 60.
[0019]
Further, referring to FIG. 2 showing details of the control unit 70, a common data memory current address 71 for generating an address indicating the common data stored in the common data memory unit 40, and the current address is incremented every time the common data is read. Counter 72, an individual data memory current address 73 for generating an address indicating the individual data stored in the individual data memory unit 50, a counter 74 for incrementing the current address each time the individual data is read, and a user interface unit 60. A determination unit 75 for determining the write data based on the common data area, the individual data area, and the chip designation from the CPU, and a selection unit 76 for transferring the common data or the individual data to the writing unit 30 based on the determination result. .
[0020]
Further, referring to FIG. 3A, the common data memory unit 40 includes a chip 41 to which common data is written, an address 42 in the chip, and data 43 to be written.
[0021]
Further, referring to FIG. 3B, the individual data memory unit 50 includes a chip 51 to which individual data is written, an address 52 in the chip, and data 53 to be written.
[0022]
Next, the operation of this embodiment will be described with reference to FIG. 4 and with reference to FIGS. 1, 2 and 3. The operator sets a common data area, an individual data area, and a chip designation from the user interface unit 60 (step 701). Read the address 42 from the common data memory unit 40 and the address 52 from the individual data memory unit 50, which are indicated by the common data current address 71 and the individual data current address 73, and determine whether they correspond to the individual data area. It is determined whether or not it is (step 702). If it is not an individual data area (N in step 702), the common data 43 is written to the specified address 42 of the specified chip 41 (step 703), and the common data current address is updated (step 74). If it is the individual data area (Y in step 702), the data 53 of the individual data is written to the specified address 52 of the specified chip 51 (step 705), and the individual data current address is updated (step 706). When both the common data current address 71 and the individual data current address 74 indicate the end (Y in step 707), the chip writing ends. When either of them does not indicate the end (N in step 707), the process returns to step 702 to continue writing.
[0023]
Next, a second embodiment of the present invention will be described with reference to FIG. 5. When the plurality of read-only memory chips 100 to 102 maintain a series of addresses, the data writing device 2 Obviously, it is possible to connect the read-only memory chips 100 to 102 to 30 and write data to all the chips in one step.
[0024]
Next, referring to FIG. 6 for a third embodiment of the present invention, the data writing device 3 writes data to a plurality of read-only memory chips 10 to 12 having the same common data and different individual data. Obviously, the individual data of the individual data memory unit 50 of the unit 22 can be written for each chip, and the common data of the common data memory unit 40 can be written identically for each chip.
[0025]
Further, in the first, second, and third embodiments, it is apparent that the description of the address 42 and the address 52 for specifying the address in the chip can be changed so as to specify only the start and end addresses. It is.
[0026]
【The invention's effect】
The effect of the present invention is that the common data and the individual data corresponding to the device can be written to the read-only memory chip in one step, and the program development cost and the manufacturing cost can be reduced. The reason is that it is possible to omit the step of creating a master in which common data and individual data are arranged in the order of writing.
[0027]
Still another advantage is that data writing over a plurality of chips can be performed in one step, so that development costs and manufacturing costs can be reduced. The reason is that a plurality of chips are connected, and required data can be written to each chip in one process, thereby shortening the process and simplifying the operation.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a data writing device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing details of a control unit of FIG. 1;
3A is a diagram showing a common data memory unit in FIG. 1; FIG. 3B is a diagram showing an individual data memory unit in FIG. 1;
FIG. 4 is a diagram showing the operation of the first embodiment.
FIG. 5 is a diagram illustrating a configuration of a data writing device according to a second embodiment.
FIG. 6 is a diagram illustrating a configuration of a data writing device according to a third embodiment.
[Explanation of symbols]
1, 2, 3 Data writing device 10, 11, 12 Read only memory chip 20, 21, 22 Data writing unit 30 Writing unit 40 Common data memory unit 50 Individual data memory unit 60 User interface unit 70 Control unit 71 Common data memory current Address 72 counter 73 individual data memory current address 74 counter 75 discriminator 76 selector

Claims (6)

In a data writing device that writes data to a read-only memory chip,
A writing unit that writes data by designating the chip and an address to a plurality of chips;
A common data memory unit for storing common data to be commonly stored in the device,
An individual data memory unit for storing individual data to be individually stored in the device,
A user interface unit for specifying a chip to be written and a write area for common data and individual data for each chip,
A control unit that passes the common data or the individual data to the writing unit together with the chip designation and the write address based on the determination as to whether or not the write address of the common data and the individual data indicates an area in which the common data or the individual data is written;
A data writing device comprising: The common data section includes:
2. The data writing device according to claim 1, wherein a designation of a chip to which data is written, common data such as firmware, and an address for writing the common data to the chip are stored. The individual data section includes:
2. The data writing apparatus according to claim 1, wherein a designation of a chip to which data is written, individual data such as a MAC address, and an address for writing the individual data to the chip are stored. The control unit includes:
A common data memory current address indicating an address for sequentially reading the common data memory unit;
A counter that increments the common data current address for each read,
An individual data memory current address indicating an address for sequentially reading the individual data memory unit;
A counter that increments the individual data current address for each read,
A determination unit configured to determine whether the write address of the common data and the write address of the individual data point to a common data area or an individual data area of a specified chip;
A selection unit that selects common data or individual data based on the determination result of the determination unit, sends a chip designation, the selected data, and a write address to the data writing unit;
The data writing device according to claim 1, further comprising: The writing unit,
3. The data writing device according to claim 2, wherein a plurality of chips of the read-only memory are arranged in order of address, and the common data and the individual data are written while maintaining a series of addresses. The writing unit,
3. The data writing device according to claim 2, wherein a plurality of chips of the read-only memory are arranged in parallel, common data is written to each chip in parallel, and individual data is individually written to different data for each chip.

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