JP3530599B2 - Image reading apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus and method for reading both sides of an original at the same time.

[0002]

2. Description of the Related Art In recent years, along with the development of information processing devices for handling images such as electronic files, image reading devices called scanners for optically reading a document have been developed. Many of the originals handled by these devices are sheet-shaped and have information written on both sides. Further, as an example of such an original, there are a slip, a check, and the like, but in general, these require a large number of sheets to be processed in a short time, and high speed processing is required. For these reasons, as a function of the image reading apparatus, it is becoming an important function to read both sides of a sheet-shaped document at high speed.

FIG. 6 shows an example of a conventional double-sided image reading apparatus.

In FIG. 6, a document 6-2 placed on a document table 6-1 is separated by a feed roller 6-3 and a separation roller 6-.
Sent to 4. Since the upper side of the separating roller rotates in the feeding direction and the lower side rotates in the returning direction, the documents are separated one by one. The separated document is conveyed by the feed roller 6-5. During this time, the original is illuminated by the lamp 6-6, and the images on both sides (front side and back side) of one line perpendicular to the drawing are line-shaped CC by the mirror 6-7 and the lens 6-8.
Image on D6-9.

The CCD 6-9 is a CCD drive circuit 6-
It is driven by the drive signals 6-a and 6-c from 11 to obtain outputs 6-b and 6-d, which are combined line by line by the analog switch 6-10 to become 6-e.

FIG. 7 shows the timing of each output of FIG.
A description will be given accordingly. CCD drive signals 6-a, 6-c
Of the shift pulses 6-a ′ (included in 6-a), 6
-C '(included in 6-c) is set to a pulse interval twice as long as usual, and after the front image signal 6-b has been output from the CCD, the back pulse 6-c' is input, Next, the back image signal 6-d is obtained. This obtained 6-b, 6
An image signal 6 in which the front and back are combined into one line by alternately switching out -d with an analog switch
-E is obtained.

This image signal is digitized by the A / D conversion circuit 6-12, and then binarized into black and white by the image processing circuit 6-13 by image processing such as edge enhancement and pseudo multi-value processing to compress the image. It is compressed by the circuit 6-14 and output as double-sided image data.

In the above method, since the front and back signals are made to be one line, the circuit after synthesis may be one set, so that the circuit can be simplified.

[0009]

However, in the above-mentioned conventional example, since the length of one line is apparently doubled as compared with the case of reading on one side, there is a drawback that the reading speed is halved.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide an image reading apparatus and method for reading an image without slowing the reading speed even in double-sided reading.

Another object of the present invention is to provide an image reading apparatus and method for reading an image without slowing the reading speed even in double-sided reading by using a first-in-first-out type memory.

Still another object of the present invention is to provide an image reading apparatus and method capable of efficiently using the first-in-first-out type memory.

[0013]

In order to achieve the above-mentioned object, the invention according to claim 1 has a first sensor and a second sensor, and at a first time from each of the first and second sensors. the first is <br/> output, in the image reading apparatus of the second signal temporally staggered composite image processing, and the first, second FiFo a writable data amount with each other are different, the
For the first and second FiFo , write the first and second signals to the first and second FiFo , respectively .
Write clock at 1 speed shorter than the first time
Supplying time, wherein the first, and a clock generating means for supplying a read clock a second signal at a second speed to read each said clock generating means, the second
Writable data amount than FiFo is written in small the first FiFo said first signal reading end
The first signal so that the reading of the second signal is started.
The second frequency is higher than the write clock, which is the speed of
The read clock is supplied to the first and second FiFo at the speed of .

[0014] The invention according to claim 2, in claim 1, wherein the write clock is a first speed said
The clock is common to the first and second FiFo .

Further, the invention according to claim 3 is the same as claim 1.
In or 2, wherein the first, the second sensor for each line first, a second signal output, respectively, before and after the clock generating means starts reading of the first signal
It is characterized in that the supply of the write clock of the signal of the next line is started to the first FiFo .

Furthermore, the invention according to claim 4 is the invention according to claim 3.
In the above, the clock generation means is configured to generate the second FiFo.
Then, start supplying the write clock for the signal of the next line
Characterized by starting the supply of the read clock of the second signal after. Furthermore, the invention according to claim 5 is
5. The method according to claim 3, wherein the second speed read clock is n (n: a positive integer) times faster than the first speed write clock.
The number of words in FiFo is 1 + 1 / n times or more the number of pixels in one line of the first sensor. Furthermore, the invention according to claim 6 is the invention according to claim 1 or 2.
In the above, the clock generation means starts the supply of the read clock after the supply of the write clock of the first signal is started. Further, in the invention according to claim 7, in claim 6, after the clock generation means starts the reading of the second signal, the supply of the write clock of the signal of the next line to the second FiFo is started. It is characterized by Further, in the invention according to claim 8, in claim 6 or 7, the read clock which is the second speed is n (n: a positive integer) times faster than the write clock which is the first speed. In one case, the number of words of the first FiFo is 1-1 / n times or more the number of pixels of one line of the first sensor. Further, the invention according to claim 9 has the first and second sensors, and temporally outputs the first and second signals output from the first and second sensors at the first time, respectively. In an image reading method of shifting and synthesizing to perform image processing, first and second FiFo having different writable data amounts, and the first and second FiFo are provided with the first from the clock generating means. A write clock of speed is supplied for a time shorter than the first time to write the first and second signals, and the data is written to the first FiFo having a smaller writable data amount than the second FiFo. After the reading of the first signal is completed, the read clock of the second speed, which is higher than the write clock of the first speed, is applied to the first and second FiFo so as to start the reading of the second signal. To the clock And supplying the supply means. Further, the invention according to claim 10 is characterized in that, in claim 9, the write clock having the first speed is a clock common to the first and second FiFo. Further, the invention according to claim 11 is the invention according to claim 9 or 10, wherein the first and second sensors respectively output the first and second signals for each line, and the clock generating means outputs the first and second signals. After the reading of the signal is started, the supply of the write clock of the signal of the next line to the first FiFo is started. Furthermore, the invention according to claim 12 is the invention according to claim 11.
At the second F by the clock generating means.
It is characterized in that the supply of the read clock of the second signal is started after the supply of the write clock of the signal of the next line is started to the iFo. Further, the invention according to claim 13 is the method according to claim 11 or 12, wherein the read clock at the second speed is n (n: a positive integer) times faster than the write clock at the first speed. In one case, the number of words of the second FiFo is 1 + 1 / n times or more the number of pixels of one line of the first sensor. Further, the invention according to claim 14 is characterized in that in claim 9 or 10, the supply of the read clock is started after the supply of the write clock of the first signal is started by the clock generating means. Further, the invention according to claim 15 is the same as claim 14
In the above, the clock generation means starts the reading of the second signal, and then the supply of the write clock of the signal of the next line to the second FiFo is started. Furthermore, the invention according to claim 16 is the invention according to claim 14 or 15, wherein the read clock at the second speed is n (n: a positive integer) times faster than the write clock at the first speed. In some cases, the first
The number of FiFo words is 1 / n times or more the number of pixels in one line of the first sensor.

[0017]

【Example】

(First Embodiment) FIG. 1 shows an embodiment of the present invention. In this embodiment, the driving clock of the CCD is 5 MHz and the operation clocks of the image processing circuit and the compression circuit are 10 MHz. or,
For the sake of explanation, one side of the double-sided original is set as the front side and the other side is set as the back side. In FIG. 1, 1-1 is a clock generation circuit for generating each driving clock, 1-2 is a CCD for surface reading, 1-
3 is a CCD for reading the back surface, 1-4 is a CCD drive circuit for generating various CCD drive signals including 1-a shift pulses,
Reference numeral 1-5 is an A / D conversion circuit for converting the output analog signals from the CCDs 1-2 and 1-3 into digital signals, and 1-6 is a first in first out memory for the surface (hereinafter, FiFo), A word width equal to or larger than the number of bits of the A / D conversion circuit, CCD1-2
The number of words is equal to or more than the number of pixels of. 1-7 is the same word width as FiFo 1-6, CC
The back-side FiFo 1-8 having a word number which is 1.5 times or more the number of pixels of D1-3 is a synthesizing circuit for synthesizing the outputs of FiFo 1-6 and 1-7. Reference numeral 1-9 is an image processing circuit for performing image processing such as edge enhancement, pseudo multi-value processing, and binarization, and 1-10 is an image compression circuit for performing image compression. Further, FIG. 2 shows each signal waveform. In FIG. 2, 1-
Although a is a CCD drive signal, a shift pulse is shown here as a representative. 1-b is a surface CCD output waveform,
1-c is the front and back FiFo writing clock, 1-d
Is the front FiFo read clock, 1-e is the front FiF
o read waveform, 1-f back surface CCD output waveform, 1-g back surface FiFo read clock, 1-h back surface FiFo
The read waveform, 1-i, is the output waveform of the synthesis circuit 1-8. However, since 1-e, 1-h, and 1-i are digital signals, they are different from the actual ones, but for the sake of explanation, they are shown by D / A converted waveforms.

The embodiment of FIG. 1 will be described according to the waveform timing of FIG. Similar to the conventional example, CCD 1-2, 1-3
The image of the first line formed on the upper side is the CCD 1-2, 1
-3 is photoelectrically converted, and according to the timing of the shift pulse 1-a, the front surface is output as 1-b (F-1) and the back surface is output as 1-f (B-1). These signals are converted into digital signals by the A / D conversion circuit 1-5, and FiFo1- is set in accordance with the FiFo write clock 1-c (5 MHz).
6, 1-7. Next, FiFo1-for the surface
In No. 6, (F-1) is read by the read clock (10 MHz) before the image (F-2) of the next line is input.
It is read like (F-1) 'of e. Further, even if the image (F-2) of the next line is input, the read clock is faster, so there is no problem, and FiFo1-6 to (F-1)
Can be read.

Since the FiFo 1-7 for the back surface has a length (the number of words) of 1.5 times the number of pixels of the CCD 1-3,
At the time when the writing of the data of the line is finished (in FIG. 2), only 2/3 of the entire data is written as shown by the slanted line in (1) of FIG. Since the FiFo 1-7 generally has a ring format in which it is the first address after the last address, it is indicated by a circle as shown in FIG.

Next, the image data of the next line (B-2)
Is written in the FiFo1-7 and (F-1) is read from the FiFo1-6 as (F-1) '(FIG. 2), the reading of the back-side FiFo1-7 starts. The state of FiFo 1-7 at this time is (2) in FIG. Like the front-side FiFo, reading is faster than writing, so the data of (B-1) is read out smoothly, and when the writing of the image data (B-2) of the next line is completed, FiFo1 The content of -7 is (3) in FIG.
As described above, all of (B-1) is read out, and an area (a portion without hatching) where the image data of the next line is input is secured.

The data (F-1) 'and (B-1)' read from the respective FiFo are combined into one line by the combining circuit 1-8 and input to the image processing circuit 1-9. Then, it is input to the image compression circuit 1-10. Since these circuits also perform processing with the clock of 10 MHz, the processing can be completed and output by the time the data of the next line is output from FiFo 1-6 and 1-7.

In this embodiment, the write clock is set to 5 MHz and the read clock is set to 10 MHz for the sake of explanation. However, it is not necessary to set these frequencies, and when the read clock is n times the write clock, it is for the back side Fi
It is clear that Fo requires 1 + 1 / n times as many words as one CCD line.

(Second Embodiment) In the first embodiment, a CCD is used.
After inputting the data for one line of
The iFo was read, but in the second embodiment, the CCD
When the data from is input to the FiFo for 1/2 line, the reading from FiFo is started. As a result, the front-side FiFo can be realized with a word number that is half the number of pixels for one line of the CCD, and the back-side FiFo with the same number of words as the number of pixels for one line of the CCD.

The hardware configuration of the second embodiment is F
The iFo is the same as the first embodiment (FIG. 1) except for the length (word number), and a timing chart is shown in FIG.
Here, description will be given according to FIG.

Similar to the first embodiment, the front and back surfaces CC
The image data of the first line imaged on D is 1-from the front CCD depending on the timing of the shift pulse 1-a.
(F-1) of b, 1-f (B-1) from the back CCD
Is output. These signals are similarly A / D converted and written into the respective front and back FiFo according to the 5 MHz clock 1-c. Next, in the second embodiment, the time when the image data from the CCD is written in the FiFo for the front surface and the back surface for 1/2 line (in FIG. 4).
Then, by 10MHz clock 1-d, FiF for surface
Data is read from o as 1-e. At this point,
In the front-side FiFo, data is written just up to the final address as shown in (1) of FIG. 5, but by reading from the front-side FiFo with a clock having a speed twice that of writing,
The data area sequentially becomes free from the start address of the FiFo. Next, FIG. 5 shows the state of the front-side FiFo at the time when the front-side FiFo data is read out by about 3/4 (in FIG. 4).
(2) of. As shown in the figure, since the reading speed is faster than the writing speed, it can be seen that an empty area is formed in FiFo. The state of the front-side FiFo at the time when the writing of the CCD data is near the end (in FIG. 4) is shown in (3) in FIG. As shown in the figure, the address distance to the final address is double for the read address and for the write address. In this way, when the data for one line is written, the write address and the read address become equal to the final address, that is, the same state as the initial state, and the next line (F-2) It is ready for writing. Regarding the data on the back side, the FiFo for the back side is for one line, and since the first line is read before the second line is written, reading and writing can be performed without problems.

As described above, the front side data (F-1) 'and the back side data (B-2)' are read at high speed and combined as one line of front and back data.

In the first embodiment, the signal (horizontal synchronizing signal) indicating the beginning of one line can be shared with the shift pulse of the CCD, but in the second embodiment, it is necessary to create it separately. However, there is an advantage that FiFO is small.

In the second embodiment, the write clock is 5 MHz and the read clock is 10 MH for the sake of explanation.
However, it is clear that it is not necessary to use these frequencies, and when the read clock is n times the write clock, the front-side FiFo needs to be (1-1 / n) for one CCD line. .

[0029]

As described above, according to the present invention, it is possible to read an original image without slowing the reading speed even when reading both sides.

Further, according to the present invention, by using the first-in-first-out type memory, it is possible to provide an image reading apparatus for reading an image without slowing the reading speed even when reading both sides.

Further, according to the present invention, it is possible to provide an image reading apparatus which can efficiently use the first-in-first-out type memory.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit of each embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation timing of the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a data state of FiFo according to the first embodiment of this invention.

FIG. 4 is a diagram illustrating an operation timing of the second embodiment of the present invention.

FIG. 5 is a diagram illustrating a data state of FiFo according to the second embodiment of this invention.

FIG. 6 is a diagram illustrating a configuration of a conventional double-sided reading device.

FIG. 7 is a diagram for explaining the operation timing of a conventional example.

[Explanation of symbols] 1-1 Clock generation circuit 1-2, 1-3 CCD 1-5 A / D conversion circuit 1-6, 1-7 FiFo

Claims (16)

(57) [Claims] 1. A first and a second sensor are provided, and the first and second sensors are provided.
In an image reading apparatus that performs image processing by synthesizing first and second signals respectively output from a second sensor at a first time by shifting them temporally, the first and the second writeable data amounts are different from each other. F of 2
For the iFo and the first and second FiFo, a write clock is applied at a first speed for writing the first and second signals to the first and second FiFo, respectively, from the first time. A clock generator for supplying a read clock at a second speed so as to read the first and second signals respectively for a short time, and the clock generator is writable more than the second FiFo A higher frequency than the write clock that is the first speed so that the reading of the second signal is started after the reading of the first signal written in the first FiFo having a small data amount is completed. An image reading apparatus, wherein a reading clock is supplied to the first and second FiFo at a speed of 2. 2. The image reading apparatus according to claim 1, wherein the write clock having the first speed is a clock common to the first and second FiFo. 3. The method according to claim 1, wherein the first,
The second sensor outputs the first and second signals for each line, and after the clock generating means starts reading the first signal, the signal of the next line is written to the first FiFo. An image reading apparatus characterized by starting supply of a clock. 4. The clock generation means according to claim 3, wherein the supply of the read clock of the second signal is started after the supply of the write clock of the signal of the next line to the second FiFo. Characteristic image reading device. 5. The method according to claim 3, wherein the second speed read clock is n (n: positive integer) times faster than the first speed write clock. 2. The image reading apparatus, wherein the number of FiFo words of 2 is 1 + 1 / n times or more the number of pixels of one line of the first sensor. 6. The image reading apparatus according to claim 1, wherein the clock generation means starts the supply of the read clock after the supply of the write clock of the first signal is started. 7. The method according to claim 6, wherein the clock generating means starts reading the second signal, and then the second signal is output.
The image reading apparatus characterized in that the supply of the write clock of the signal of the next line is started to the FiFo. 8. The method according to claim 6, wherein the second speed read clock is n (n: positive integer) times faster than the first speed write clock. An image reading apparatus, wherein the number of words of 1 FiFo is 1-1 / n times or more the number of pixels of one line of the first sensor. 9. A first sensor and a second sensor are provided, and the first sensor and the second sensor are provided.
In an image reading method in which first and second signals respectively output at a first time from a second sensor are shifted in time and combined to perform image processing, first and second different writable data amounts are provided. F of 2
In the case of an iFo, the first and second FiFo are supplied with a write clock of a first speed from a clock generation means for a time shorter than the first time, and the first and second signals are written. At the first speed, the reading of the second signal is started after the reading of the first signal written in the first FiFo having a smaller writable data amount than the second FiFo is completed. A read clock having a second speed higher than a certain write clock is used as the first and second Fi.
An image reading method, wherein Fo is supplied from the clock supply means. 10. The image reading method according to claim 9, wherein the write clock having the first speed is a clock common to the first and second FiFo. 11. The method according to claim 9 or 10, wherein the first and second sensors output the first and second signals for each line, and the clock generating means reads the first signal. An image reading method, characterized in that, after starting, supply of a write clock for a signal of the next line to the first FiFo is started. 12. The supply of the read clock of the second signal is started after the supply of the write clock of the signal of the next line to the second FiFo is started by the clock generation means according to claim 11. Characteristic image reading method. 13. The method according to claim 11, wherein the second speed read clock is n (n: positive integer) times faster than the first speed write clock. The number of words of FiFO of 2 is the first
The image reading method is characterized in that the number of pixels in one line of the sensor is 1 + 1 / n times or more. 14. The image reading method according to claim 9, wherein the supply of the read clock is started after the supply of the write clock of the first signal is started by the clock generating means. 15. The method according to claim 14, wherein after the second signal is read by the clock generation means, the supply of the write clock for the signal of the next line to the second FiFo is started. Image reading method. 16. The method according to claim 14, wherein the second speed read clock is n (n: positive integer) times faster than the first speed write clock. The number of words in one FiFo is the first
The image reading method is characterized in that the number of pixels on one line of the sensor is 1-1 / n times or more.