JP3526408B2 - Semiconductor integrated circuit test signal generation method and generation device, medium recording test signal generation program - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal generation method for a semiconductor integrated circuit capable of automatically generating a test signal sequence for fault detection and failure cause analysis during development or initial manufacturing of a semiconductor integrated circuit. The present invention relates to a generator. The present invention also relates to a medium in which the inspection signal generation program for the semiconductor integrated circuit as described above is recorded.

[0002]

2. Description of the Related Art Conventionally, various methods have been used to detect a failure in a semiconductor integrated circuit. For example, regarding the failure of the circuit characteristics, the target circuit network is modeled with logic elements, and while the input signal to the model is traced in the forward direction (in the case of the output signal, the backward direction), the failure is confirmed by comparison with actual data. There is a system for estimating elements.
Further, a device for detecting a fault in a complicated sequential circuit characteristic has been proposed (for example, Japanese Patent Laid-Open No. 6-162).
136).

By the way, in a semiconductor integrated circuit, it is necessary to consider not only that the circuits are integrated but also the influence between the elements due to its structure. That is, due to the manufacturing process, not only the failure of the element itself, but also the failure between the elements causes the failure of the circuit characteristics,
There is no guarantee that the detection / analysis method based on the model of the failure of a single element will find the true cause.

That is, in the conventional device level inspection,
It only detects which one of the circuit elements has failed. Therefore, this is sufficient in the case of a circuit in which elements are soldered on a board, but in an integrated circuit, even the individual terminals that make up the circuit elements and the wiring between the circuit elements are all made of silicon or the like. Therefore, in addition to the defect of the element, a defect due to the interference between the elements may occur. Since such a defect between elements does not appear in the circuit expressed at the element level, it is not possible to generate an inspection signal for detecting a defect between terminals with the conventional technology.

FIG. 7 is a circuit diagram of a dynamic RAM which is an example of a semiconductor integrated circuit. In FIG. 7, B
IT1 and BIT3 are circuit elements (memory elements), respectively, and these circuit elements BIT1 and BIT3 are terminals W that form capacitors DT1 and DT3 and a transistor.
It is composed of C1, WC3 and BC1, BC3. The circuit elements BIT1 and BIT3 are connected by word lines WL1 and WL2 and bit lines BL1 and BL2. However, FIG. 7 cannot represent the interference between the circuit elements BIT1 and BIT3, for example. In order to show the interference between the circuit elements BIT1 and BIT3, as shown in FIG.
Although it is necessary to newly introduce a resistance element R that does not normally exist between T1 and BC3, it is difficult to automatically perform this using an electronic computer from an electronic circuit representation.
Therefore, in the prior art, a technique for easily generating an inspection signal for detecting a failure indicating interference between circuit elements using an electronic computer has not been realized.

[0006] In the model constructed from the material level, the cause of the failure is also investigated by numerical analysis using a high performance computer, but this is mainly done after the diagnosis of the failure. It is a method that should be used for investigation, and it is not realistic in terms of equipment, cost, and diagnostic time to be used to check for "no failure".
Therefore, under the present circumstances, a person inputs the inspection signal with reference to the accumulated know-how, investigates the failure characteristics of the output signal of the semiconductor integrated circuit, and further prepares the inspection signal while estimating each failure cause. It is the actual situation that the verification is repeated.

[0007]

As described above, there is a demand for automating failure detection / analysis (diagnosis), which must be said to be performed by humans at present, as far as possible. As described in the above-mentioned conventional technique, the following two problems are problems.

(1) Since it is an integrated circuit, a complicated sequential circuit must be used as a precondition for its operation, and therefore failure detection becomes complicated. (2) Since an integrated circuit is manufactured by using a semiconductor material without clarifying the element division, not only the failure of the elements alone but also the failure between the elements exist as failures without distinction.
Failure factors and expressions are complicated, and failure detection is difficult.

Due to these problems, it is extremely difficult to create an inspection signal to be input "on occasion" in order to actually confirm the failure even in the failure detection / analysis work of a person. .

The present invention has been proposed in order to solve the above-mentioned problems of the prior art, and its object is, when a model of a terminal-level failure of a semiconductor integrated circuit is given, that failure. It is an object of the present invention to provide a semiconductor integrated circuit inspection signal generation device and a generation method capable of automatically generating an inspection signal for surely detecting.

Another object of the present invention is to construct each test signal candidate even if a test signal candidate created in advance does not include a detection signal sequence that can be actually used. It is an object of the present invention to provide a test signal generation device and a generation method for a semiconductor integrated circuit that can generate a series of signals that can be used as detection signals by selecting and combining signals that satisfy certain conditions.

[0012]

According to a first aspect of the present invention, the terminal arrangement data of a fault-inspected semiconductor integrated circuit and the normal inter-terminal coupling data describing the coupling relationship between the terminals when the integrated circuit has no fault. Abnormal connection data including data describing a connection relationship between terminals of the integrated circuit in which the integrated circuit is suspected to operate abnormally, and the normal connection data between terminals, or The terminal condition calculation rule for calculating the terminal condition of each terminal of the integrated circuit based on the abnormal connection data between terminals, and the data regarding the candidate of the inspection signal to be input to the integrated circuit are acquired, and For each of the test signal candidates for each terminal, the branching relationship of all terminal conditions based on the normal coupling data and the abnormal coupling data between the terminals is defined as the terminal condition calculation rule. According to the above, a normal condition branch table and an abnormal condition branch table are generated, and the generated normal condition branch table and abnormal condition branch table are compared to search for conditional branch points different from each other, and candidates for the respective inspection signals are obtained. With respect to the condition of the initial state before the inspection of the integrated circuit, the one reaching the abnormal condition branch point detected by the abnormal branch search means is selected, and the abnormal condition is changed from the initial state to the abnormal condition. The input signal sequence corresponding to the branch point is output as a pre-abnormal branch signal sequence, and one of the inspection signal candidates that reaches the abnormal condition branch point is selected, and the corresponding one after the abnormal condition branch point is selected. An input signal sequence of the candidate inspection signal is output as a post-abnormal branch signal sequence, and a signal sequence corresponding to the abnormal condition branch point is selected from the pre-abnormal branch signal sequence and the post-abnormal branch signal sequence. It generates a signal sequence of the non-arbitrary length, characterized in that the abnormality detection signal sequence.

Further, the invention of claim 4 is the invention of claim 1 which is grasped from the viewpoint of an apparatus, and includes a terminal arrangement data storage means for storing terminal arrangement data of a fault-tested semiconductor integrated circuit, Normal coupling data storage means for storing data describing a coupling relation between terminals when the integrated circuit has no failure; and the normal coupling data between terminals, in addition to the suspected abnormal operation of the integrated circuit. Abnormal coupling data storage means that also stores data describing the coupling relationship between terminals of the integrated circuit, inspection signal candidate data storage means that stores candidates of inspection signals to be input to the integrated circuit, and normal coupling between the terminals. A rule for calculating the terminal condition of each terminal of the integrated circuit is stored based on the inter-terminal coupling data stored in the data storage means or the inter-terminal abnormal coupling data storage means. Child condition calculation rule storage means, and for each terminal, for each test signal candidate stored as the search signal candidate data, any terminal condition based on normal coupling data between the terminals and abnormal coupling data Of the normal condition data based on the normal connection data obtained from the conditional branch table generation means for calculating the branch relation of the terminal condition calculation rule and outputting the normal condition branch table and the abnormal condition branch table. An abnormal branch search means for comparing a conditional branch table with an abnormal conditional branch table based on the abnormal connection data to search for different conditional branch points, and data created in the inspection signal candidate list data storage means. For each candidate of the inspection signal, the abnormal condition component detected by the abnormal branch search means is checked from the condition of the initial state of the integrated circuit before the inspection. Pre-abnormality branch signal sequence generation means for selecting a signal reaching a point and outputting an input signal sequence corresponding to the abnormal condition branch point from the initial state of the selected inspection signal as a pre-abnormality branch signal sequence, Of the inspection signal candidates stored in the inspection signal candidate data storage means, one that reaches the abnormal condition branch point is selected, and the input signal series of the candidate inspection signal corresponding to the abnormal condition branch point and thereafter is abnormal. An arbitrary length including a signal sequence corresponding to the abnormal condition branch point from the abnormal post-branch signal sequence generation means for outputting as a post-branch signal sequence, the initial or pre-abnormal branch signal sequence, and the abnormal post-branch signal sequence And an anomaly detection signal sequence generation means for generating the anomaly detection signal sequence as an anomaly detection signal sequence.

Further, the invention of claim 6 is the same as claim 1
Alternatively, a computer program for implementing the invention of claim 4 is recorded on a medium.

According to the invention of claim 1, claim 4 or claim 6 having such a configuration, the terminal arrangement data storage means detects the potential, charge, etc. in the layout of the semiconductor integrated circuit subject to the failure inspection. Abnormal terminal-to-terminal abnormal coupling data is stored by storing the terminal arrangement data as a base point, and the terminal-to-terminal normal coupling data storage means by storing data describing the coupling relationship between terminals when there is no failure in the integrated circuit. There is a possibility that the integrated circuit will operate abnormally, the memory is not described in the normal connection data between terminals, or the connection is in a state different from normal connection due to an open failure or short circuit failure between terminals. Is also stored as data, and the terminal condition calculation rule storage means is a terminal stored in the inter-terminal normal coupling data storage means or the inter-terminal abnormal coupling data storage means. Based on the binding data of each pin state stores the terminal condition calculation rule for calculating a terminal condition indicating (potential, the amount of such charges). In addition, the inspection signal candidate data storage means determines and stores a signal to be input to the integrated circuit in consideration of restrictions imposed by operating conditions of the integrated circuit and the like.

Then, the conditional branch table generating means calculates, for each terminal, all branch relationships of the terminal conditions that change depending on the inter-terminal coupling state corresponding to the search signal candidate list according to the calculation rule. The abnormal branch searching means outputs the conditional branch table, and the abnormal branch searching means compares the normal conditional branch table and the abnormal conditional branch table obtained from the conditional branch table generating means to search for abnormal conditional branch points which are different conditional branch points. The pre-abnormal branch signal sequence generation means is detected by the abnormal branch search means from the pre-test initial state condition of the integrated circuit in association with each candidate test signal created from the data stored in the test signal candidate data storage means. For those that reach the abnormal condition branch point, the input signal sequence corresponding to the initial condition to the abnormal condition branch point is output as the initial or pre-abnormal branch signal sequence. When the abnormal branch signal sequence generation means reaches the abnormal condition branch point in the abnormal branch search means, outputs the input signal sequence of the candidate inspection signal corresponding to the abnormal condition branch point and after as the post-abnormality or observed branch signal sequence. . The abnormality detection signal sequence generation means generates an arbitrary length signal sequence including a signal sequence corresponding to an abnormal condition branch point from the initial to pre-abnormal branch signal sequence and the post-abnormality to observed branch signal sequence to detect abnormality. Signal sequence. As a result, it becomes possible to automatically generate an inspection signal sequence capable of detecting a failure at each terminal level forming a semiconductor device by a computer.

According to a second aspect of the present invention, in the inspection signal generating method according to the first aspect, in generating the post-abnormality branch signal sequence, an abnormal coupling that takes the same value as the post-branch condition of the abnormal condition branch as a pre-branch condition. The signal that is common to the signal in the conditional branch table in and the signal in the conditional branch table in the normal coupling that has the same value as the post-branch condition of the normal conditional branch as the pre-branch condition is the signal that constitutes the abnormal branch signal sequence. Is selected, and these are combined to create a post-abnormality branch signal sequence.

According to a fifth aspect of the invention, the invention of the second aspect is grasped from the viewpoint of an apparatus. In the invention of the fourth aspect, the abnormal post-branch signal sequence generation means is an abnormal conditional branch. The signal in the conditional branch table in the abnormal connection that takes the same value as the post-branch condition as the pre-branch condition and the signal in the conditional branch table in the normal connection that takes the same value as the post-branch condition in the normal condition branch as the pre-branch condition It is characterized in that a common signal is selected as a signal forming a post-abnormality branch signal sequence and these are combined to create a post-abnormality branch signal sequence.

According to the invention of claim 2 or claim 5 having such a configuration, even if there is no signal that can be used as an abnormality detection signal as it is among the candidates of the inspection signal, the inspection of a plurality of candidates is performed. It is possible to obtain a detection signal sequence that can be actually used by selecting the signals that form the post-abnormality branch signal sequence from the conditional branch table for normal coupling and abnormal coupling of signals and combining them.

According to a third aspect of the present invention, in the inspection signal generating method according to the second or third aspect, the abnormal post-branch signal sequence includes an observation signal sequence capable of determining a terminal condition. According to the invention of claim 3 as described above,
It is possible to generate not only a signal sequence for detecting a failure between terminals, but also an inspection signal sequence that allows external observation of which part of the failure.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention (hereinafter referred to as "embodiments") will be described with reference to the drawings. Note that the present invention is generally considered to be realized by controlling a computer having peripheral devices with software. In this case, the software is made by combining the instructions according to the description of this specification, and the method described in the prior art is also used for the common part with the above-mentioned prior art. The software includes not only the program code but also data prepared in advance for use when executing the program code.

[1. Configuration] FIG. 1 is a functional block diagram showing the configuration of the first embodiment of the present invention, and conceptually shows that the operation of the software S as described above is realized by the computer C. . That is, the computer C includes a CPU (C1), a main memory C2 using a RAM and the like, an auxiliary storage device C3 such as a hard disk device, and an input device C such as a keyboard and a mouse.
4 and an output device C such as a CRT display or printer
5, the software S as described above realizes the operation and effect of the present invention by utilizing physical resources such as these hardware.

However, the specific software and hardware configurations for implementing the present invention can be changed in various ways. For example, the software format is a compiler,
There are various kinds of interpreters, assemblers, etc. For exchanging information with the outside, various kinds of removable recording media such as floppy disks, network connecting devices, etc. are also conceivable. Further, a recording medium such as a CD-ROM that records software or a program for realizing the present invention,
Independently, it is one embodiment of the present invention. Further, some of the functions of the present invention can be realized by a physical electronic circuit such as an LSI.

As described above, various modes of implementing the present invention using a computer are conceivable. Therefore, in the following, a virtual circuit block that implements each function included in the present invention and the embodiment is used to implement the present invention. The invention and embodiments will be described.

That is, the semiconductor integrated circuit inspection signal generating apparatus 10 of this embodiment includes a terminal arrangement data storage unit 11 for storing terminal arrangement data of a fault-tested semiconductor integrated circuit,
In addition to the normal coupling data storage unit 12 for storing data describing the coupling relation between terminals when the integrated circuit has no failure, and the normal coupling data between the terminals, the integrated circuit operates abnormally. Data that you suspect
An abnormal terminal-to-terminal data storage unit 13 that also stores data that describes a connection relationship between terminals of the integrated circuit that is not defined in the normal-coupling data storage unit 12 or is different from the normal-coupling data storage unit 12 or A terminal condition calculation rule storage unit 14 for storing a terminal condition calculation rule for calculating a terminal condition of each terminal of the integrated circuit based on the terminal connection data stored in the abnormal connection data storage unit 13;
The inspection signal candidate data storage unit 15 stores and determines a signal to be input to the integrated circuit.

Further, for each of the terminals, with respect to the search signal candidate list data, branch relations of all terminal conditions based on the inter-terminal coupling data are calculated by the terminal condition calculation rule, and a directed graph (hereinafter referred to as a conditional branch table). ), A conditional branch table based on the normal join data (hereinafter, normal conditional branch table) obtained from the conditional branch table generator 16, and a conditional branch based on the abnormal join data. Tables (hereafter, abnormal condition branch tables) are compared and different from each other conditional branch points (hereafter, abnormal condition branch points)
And an abnormal branch search unit 17 for searching.

Further, the inspection signal candidate data storage unit 1
For each candidate inspection signal created from the data stored in 5, the initial state of the one that reaches the abnormal condition branch point detected by the abnormal branch search unit from the condition of the pre-inspection initial state of the integrated circuit To the abnormal condition branch point, and outputs the input signal sequence corresponding to the abnormal condition branch point as a pre-abnormal condition branch signal sequence; and, when the abnormal condition branch point is reached, after the abnormal condition branch point Post-abnormality branch signal sequence generation unit 19 that outputs an input signal sequence of the corresponding candidate inspection signal as a post-abnormality branch signal sequence
From the initial to pre-abnormality branch signal sequence and the post-abnormality to observed branch signal sequence, a signal sequence of arbitrary length including a signal sequence corresponding to the abnormal condition branch point is generated, and an abnormality detection signal sequence Each unit constituting the semiconductor integrated circuit inspection signal generation device 10 including the abnormality detection signal sequence generation unit 20 will be sequentially described below.

[1-1. Terminal Arrangement Data Storage Unit] The terminal arrangement data storage unit 11 stores terminal arrangement data in a semiconductor integrated circuit. That is, FIG.
3 and FIG. 3 are schematic diagrams showing an element structure and a terminal arrangement in the semiconductor memory circuit, which is an arrangement diagram as a source of data stored in the terminal arrangement data storage unit 11.

FIG. 2 is a schematic diagram of the semiconductor integrated circuit when viewed from above, and FIG. 3 is a schematic diagram showing a cross section thereof. Also, WL1, WL2, WL3, WL4, ... and BL
1, BL2, ... Represent electric wirings for reading / writing from / to the memory, and electric charges are stored in the electrodes DT1, DT2, DT3, DT4 ,. I am doing it. In a semiconductor memory, the electrode DT of the capacitor
1, DT2, DT3, DT4, ...
Data is controlled from BL1, ... Via points WC1, ..., BC1 ,. At this time, for example, BC1, WC1, and DT1 are grouped into a set and considered as “BIT1” to form one data unit (bit).

Hereinafter, DT1, ..., WC1, ..., BC1,
When referring to ... without making a distinction, they may be referred to as "nodes". Further, in the terminal arrangement data storage unit 11, the coordinates (X coordinate, Y coordinate) of the plane viewed from above the semiconductor memory are
Assuming that the coordinates are given, the data indicating the arrangement of each node and the relationship with each wiring is stored in the format shown in Table 1 below.

[0031]

[Table 1]

Therefore, the terminal arrangement data in the range shown in FIG. 2 is as shown in Table 2.

[0033]

[Table 2]

Here, for example, the function indicating the X coordinate of the node is x (), the function indicating the Y coordinate is y (), and the type (BC or W
If the function indicating C or DT) is k (), the membership relationship between the wiring and the node is expressed as follows.

[0035]

[Equation 1]

As described above, by selecting and labeling arbitrary positions in the integrated circuit, it is possible to express the mutual relationship between the respective positions.

[1-2. Normal Coupling Data Storage Unit] The normal coupling data storage unit 12 uses the expression format defined by the terminal arrangement data storage unit 11 described above to express each normal normal operation of the integrated circuit. It stores data indicating how the terminals are related.
Similar to the above, a semiconductor memory will be described below as an example.

The electrical characteristics of ordinary semiconductor integrated circuits are roughly as follows: Wiring characteristics: Unconditionally coupled (conducted) 2. Switch characteristics: There are two cases in which they are coupled (conducted) when a specific condition is satisfied. Now node N (i)
And the node N (j) is connected

[Equation 2] connect (N (i), N (j)) (3) Shall be expressed as

(A. In the case of wiring) For example, in FIG. 2, if a current flows through the wiring BL1, nodes N (1) and N (6) on the wiring BL1 (“BC1”, respectively)
“BC2” (see Table 2) is the wiring B if the circuit is normal.
The relationship of conducting to L1 and coupling with each other always holds. Using Equation 3 of the above-mentioned combination expression, it becomes as follows.

[Equation 3] connect (N (1), L (5)) connect (N (6), L (5)) connect (N (1), N (6))… (4)

(B. In case of switch) For example, WC1 has a high potential due to transistor characteristics (hereinafter,
Only in the case of “p”), when BC1 and DT1 are in a combined state, a conditional part is added to Expression 3 and expressed as follows.

[Equation 4] connect (N (1), N (3)): value (N (2)) = p… (5)

As described above, it is assumed that the normal connection data storage unit 12 stores the connection relation between the nodes regarding the normal operation in the form of the equations 4 and 5. In addition, ":" indicates that the part after that is a conditional part,
"Value ()" indicates the value that the node has, and "= p" is
It indicates that the value is “high” within a predetermined range. Also, it is of course possible to divide into various levels, not only in the case of "high value" as described here, but about that, connec
Along with the detailed description of t () and value (), [1-4. Conditional branch table generation unit].

[1-3. Abnormal Binding Data Storage Unit] The abnormal binding data storage unit 13 is the normal binding data storage unit 12 described above.
It stores an abnormal connection relation of the integrated circuit, which is not defined in. Here again, a semiconductor memory will be described as an example. Note that the following are usually assumed to be the cause of failure. 1. Open 2. Short circuit 3. Parasitic transistor

(A. Opening and Shorting) For example, the opening and the shorting are expressed as follows for the node N (i) and the node N (j).

[Equation 5] open (N (i), N (j)) (open)… (6) short (N (i), N (j)) (short circuit)… (7)

(B. In the case of parasitic transistor) In FIG. 2, depending on the operating condition of the memory of BIT1, for example,
When an abnormal operation occurs such that DT3 is switched by BC1 and WC1 (in this case, it causes a failure because it affects BIT3), the expression in the case of the switch described in the normal coupled data storage unit 12 (expression 5)), it can be expressed as the following Expression 8.

[Equation 6] connect (N (1), N (7)): value (N (2)) = p… (8)

As described above, it is assumed that the abnormal connection data storage unit 13 stores the connection relation between the nodes regarding the abnormal operation in the form of the expressions 6 to 8. It is needless to say that the cause of failure described above depends on the layout pattern of the semiconductor integrated circuit, and causes other than those described here may be described. Also, open (), sho
For a detailed description of rt (), see [1-5. Conditional branch table generation unit].

[1-4. Inspection Signal Candidate Data Storage Unit] The inspection signal candidate data storage unit 15 stores the input signal sequence to the integrated circuit which is the source of the abnormality detection signal sequence finally obtained by the present invention. Then,
A semiconductor memory will be described as an example.

(A. Reading / Writing Bits) Since the semiconductor memory holds and changes the signal indicating the state of "0" or "1" in BIT1, BIT2, ..., As described above, Focusing on one bit, there are only three types of operations: reading the held value or writing either "0" or "1". Therefore, there are only three types of input signals for one bit, which are expressed by the following equations 9, 10, and 11.

[Equation 7] read (B (i)) (read)… (9) write0 (B (i)) (Write 0) (10) write1 (B (i)) (write 1) (11)

For example, when actually reading / writing data from / to the BIT1, it is necessary to perform a sequential operation of switching the value at a certain timing by controlling an amplifier around the wirings WL1 and BL1, and to the wirings WL1 and BL1. Terminal WC in BIT1
1, BC1 is controlled to change the electrical characteristics in BIT1 to control the capacitor terminal DT1. At this time, it is also important to make a condition not to control other bits at the same time. For example, when the wiring BL1 is conducting in BIT1, the control of BIT2 via the wiring BL1 is performed. Since there is a possibility of this, there is a need for processing such as turning off the wiring WL4 at this time. In addition,
Such conditioning is called exclusive control.

Therefore, in the description of the above equations 9, 10, and 11, it is assumed that not only the state of the directly related wiring but also the state (condition) of the related wiring is described at the same time.
Further, the condition of each wiring is expressed as shown in Table 3 below.

[0050]

[Table 3]

At this time, for example, the input "write1 (B (1))" for writing "1" to BIT1 is described by the following expression 12. Note that this only relates to the write operation to BIT1.

[0052]

[Equation 8]

Here, AMP indicates the control value of the amplifier of the integrated circuit which is in charge of BIT1. Further, γ _{1 to} γ ₄ respectively show timings when setting the value of the wiring. For example, in γ ₂ , p is given to L (1), and L
N is given to (2) to L (4), and u is given to L (5) and L (6).
And n is given to AMP. A series of sets set at each of these timings is one control for one bit.

(B. Signal sequence) A signal for fault inspection has one control for one bit (for example, write1 (B
Not only 1))), but a series of control to some bits. Therefore, the inspection signal candidate data storage unit 15 not only stores the control operation for one bit as described above, but also stores the input signal for performing a series of control on several bits. Prepare some series and memorize them. For example, these signal sequences are represented as shown in Table 4 below.

[0055]

[Table 4]

It should be noted that it is not necessary to use a specific rule or knowledge in creating the test signal sequence candidate. Further, what kind of inspection signal sequence candidate is applied to various failures is not particularly limited. For example, in the inspection of the semiconductor memory of the present embodiment, the inspection signal sequence candidate can be created by randomly combining the write and read signals for the bit to be inspected. Therefore, it is possible that the candidate list of inspection signals does not include the one that can be used as an actual inspection signal as it is.

[1-5. Conditional Branch Table Generation Unit] The conditional branch table generation unit 16 determines the value (condition) of each node under the influence of the control of each wiring from the terminal arrangement of the semiconductor integrated circuit, the connection relation between the terminals, and the inspection signal candidate. Is calculated to determine whether each bit value (condition) is satisfied.

(A. Conditional branching) The values (conditions) that can be taken by each wiring are shown in Table 3, but it is assumed that the nodes and bits also satisfy any of the conditions (4) shown in the same table.
Therefore, if the total number of bits in the integrated circuit is Q,
The number Z that can be taken for all bits is

[Equation 9] Z = 4 ^Q (13) That is, the conditional branch table generation unit 16
Then, how will the bit become one of these conditions depending on the wiring condition (conditional branch)?
Is calculated.

First, [1-2. Normal combined data storage section] and [1-3. Abnormal coupling data storage section],
Connect (), open (), short (), val for the rough meanings of the calculation of the condition of each node or the condition between nodes
It is represented by ue (). These will be described.

Before that, in the integrated circuit, the electrical characteristics between the nodes can be considered to be resistance, capacitance, and inductivity. Here, as an example, mainly resistance and capacitance are assumed,
In addition, we decided not to consider the time dependence represented by using the time constant, and as shown in Table 3, the condition (value)
Is also qualitatively (quantized). In addition, the change of the condition (value) of each node, that is, the change of the electric potential is assumed here as described above. However, this change is the change of the electric potential of the wiring or the movement of the electric charge based on the above assumption. It will be repeatedly described that this causes a change in potential as a result.

(B. Calculation of Conditions for Wiring and Nodes) The potential of each wiring is changed as determined by the inspection signal candidate data storage unit 15. At this time, the node on each wiring, that is, the WC and BC directly connected () to each wiring, have the same conditions as the wiring. However, when the wiring condition is “u”, the value of the node is held as it is. That is, the relationship of the following equation is established.

[0062]

[Equation 10]

(C. Calculation of Conditions for Nodes and Nodes) Calculation of conditions for connecting nodes and nodes becomes complicated. This is because the electrical characteristics are not accurately described like wiring. Therefore, in connect (N (i), N (j)), a calculation rule as shown in Table 5 below is provided. Also, each condition after calculation will be represented by value '().

[0064]

[Table 5]

(D. Calculation of Open and Short Circuit Conditions) In the abnormal terminal connection data, a situation of open (open ()) and short circuit (short ()) was assumed. In the case of an open circuit, the conditions of the two nodes are independent, that is, the respective values are held as they are, and for a short circuit, the following formula is obtained.

[Equation 11] value '(N (i)) = value' (N (j)) (15)

(E. Calculation of bit condition) The bit value (condition) is represented by the BC node condition. Note that the potential of BC is controlled from the outside by the wiring BL at the time of writing, but the wiring BL is controlled at the time of reading.
It is assumed that the condition of BC is read out via BL without applying a potential from the outside. Therefore, the following equation is established.

[0067]

[Equation 12]

Up to this point, the calculation of conditions for wirings, nodes, bits, etc. has been described, but this can of course be rewritten according to the characteristics of the circuit. In particular, consideration of time constants, more detailed setting of condition calculation rules between different types of nodes, and subdivision of conditions are important items. Then, these calculation rules are stored in the terminal condition calculation rule storage unit 14 in advance.

(F. Generation of Conditional Branch Table) These conditional calculation rules are used to create a conditional branch table for normal connection and abnormal connection. Regardless of whether the connection is normal or abnormal, there is no change in calculating the condition of the wiring, the node, and the bit according to the condition calculation rule described above. Therefore, here, the flow of a series of processes will be described with a specific example.

In order to simplify the description, as an example circuit, only the BIT1 and BIT3 portions will be taken out from FIG. 2, and a circuit composed of BIT1 and BIT3 as shown in FIG. 4 will be described. Note that, in order to simplify the explanation, in FIG. 4, since only the respective terminals constituting BIT1 and BIT3 are given consecutive node numbers, FIG.
Even if the terminals are in the same position, their node numbers are different from those of the terminals shown in FIG. In this respect, the consecutive node numbers are also different between Table 2 and Table 6 below.

First, the following table 6 is input from the terminal arrangement data storage unit 11 as arrangement data of the example circuit.

[0072]

[Table 6]

It is assumed that the inspection signal candidate data storage unit 15 is supplied with input signal series data as shown in Table 7 below. In addition, each input signal follows Equation 12 and
~ 22 (however, the AMP operation is omitted).

[0074]

[Table 7]

[0075]

[Equation 13]

The normal combination data is given by the following equation 23 from the normal combination data storage unit 12.

[Equation 14] connect (N (1), L (3)) connect (N (2), L (1)) connect (N (6), L (4)) connect (N (5), L (2)) connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p… (23)

Here, the connection relationship between the wiring and the node is calculated from the terminal arrangement data based on the relationship between the arrangement / type of the node and the wiring, even if it is not described as normal connection data (Equation 1, 2). It is included here in the combined data for ease of explanation.

In the example circuit, it is assumed that BC1 and DT3 have a short circuit. Suppose this is an abnormal combination. At this time, the abnormal terminal connection data is given by the following Equation 24 from the abnormal connection data storage unit 13.

[Equation 15] connect (N (1), L (3)) connect (N (2), L (1)) connect (N (6), L (4)) connect (N (5), L (2)) connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p short (N (1), N (4))… (24)

For these input data, the conditional branch tables for normal connection and abnormal connection are calculated as follows.

(G. Generation of Conditional Branch Table for Normal Coupling) In Table 7 showing the data from the test signal candidate data storage unit 15, one test signal sequence candidate is extracted. Then, a condition is calculated for each node from the wiring condition determined by the inspection signal sequence and the normal connection condition (Equation 23) according to the calculation rule held in the conditional branch table generation unit 16, and the bit condition is calculated. Wash out the conditional branch.

As shown in Table 7, candidate 1 of the inspection signal sequence
Is (write1 (B (3)), read (B (3)), read (B (1))), the normal connection condition may be calculated in the order of the expressions 21, 22, and 19.

Write1 (B (3)), 1: normal connection conditional expression 23
Then, the condition of the node to be connected is calculated from the condition of the wiring obtained from Expression 14. The initial conditions of the nodes are all "m" as shown in Table 8.

[0083]

[Table 8]

That is,

[Expression 16] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = m, (value (L (4)) = u) value (N (5)) = value (L (2)) = n… (25) Becomes

From the initial conditions and the above values,

[Expression 17] connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p ... ( The relationship of 26) does not hold. That is, from Equation 25, value
Since (N (2)) = n and value (N (5)) = n, the relationship of Expression 26 does not hold, and N (1) and N (3), N (6) and N (4)
Is not conducting. Therefore, the value (condition) that each node has at this point is as shown in the following Expression 27 from Table 5.

[0086]

[Equation 18] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = m value (N (5)) = n value (N (6)) = m… (27)

Further, from Expression 16, since the bit value (condition) is represented by the condition of the node of BC, the following Expression 28 is obtained.

[0088]

(19) Bit condition Therefore, this input signal "write1 (B (3)), 1" changes the bit condition as shown in the following Expression 29.

[0089]

[Equation 20]

Write1 (B (3)), 2: Based on the condition of this signal at time 1, the condition of the node to be combined is calculated from the normal connection conditional expression 23 and the wiring condition obtained from the expression 14. It

[Equation 21] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = m, (value (L (4)) = u) value (N (5)) = value (L (2)) = p… (30)

From the condition at time 1 and the value above

[Equation 22] connect (N (1), N (3)): value (N (2)) = p… (31) Does not hold, but

Since the relationship of connect (N (6), N (4)): value (N (5)) = p… (32) holds, the value (condition) of each node at this point is From 5, the following expression 33 is obtained.

[0092]

[Equation 24] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = m value (N (5)) = p value (N (6)) = m… (33)

Therefore, this input signal "write1 (B
(3)), 2 ”means that the bit condition is changed as shown in the following Expression 34.

[0094]

[Equation 25]

Write1 (B (3)), 3: Based on the condition of this signal at time 2, the condition of the node to be combined is calculated from the normal connection conditional expression 23 and the wiring condition obtained from the expression 14. It

[Expression 26] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = value (L (4)) = p value (N (5)) = value (L (2)) = p… (35)

From the condition at time 2 and the value above

[Equation 27] connect (N (1), N (3)): value (N (2)) = p… (36) Does not hold, but

Since the relationship of connect (N (6), N (4)): value (N (5)) = p… (37) holds, the value (condition) of each node at this point is From 5, the following expression 38 is obtained.

[0097]

[Equation 29] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = p value (N (6)) = p… (38)

Therefore, this input signal "write1 (B
(3)), 3 ”means that the bit condition is changed as shown in the following expression 39.

[0099]

[Equation 30]

Read (B (3)), 1: The condition of the node to be connected is calculated from the normal connection conditional expression 23 and the wiring condition obtained from the expression 14, assuming the condition of the previous signal at time 3. To be done.

[Equation 31] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = n… (40)

In this case,

## EQU00003 ## connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p ... ( Since the relationship of 41) is not established, the value (condition) of each node at this point is as shown in the following Expression 42 from Table 5.

[0102]

[Equation 33] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = n value (N (6)) = p… (42)

Therefore, this input signal "read (B (3)),
1 "means that the bit condition is changed as shown in the following Expression 43.

[0104]

[Equation 34]

Read (B (3)), 2: Based on the condition of this signal at time 1, the condition of the node to be combined is calculated from the normal connection conditional expression 23 and the wiring condition obtained from the expression 14. It

[Equation 35] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = p… (44)

From the condition at time 1 and the above value,

[Equation 36] connect (N (1), N (3)): value (N (2)) = p… (45) Does not hold, but

Since the relationship of connect (N (6), N (4)): value (N (5)) = p ... (46) holds, the value (condition) of each node at this point is From 5, the following expression 47 is obtained.

[0107]

[Equation 38] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = p value (N (6)) = p… (47)

Therefore, this input signal "read (B (3)),
The bit condition is changed as shown in the following expression 48 by 2 ″. At this time, BIT3 (p) is read.

[0109]

[Formula 39]

Read (B (1)), 1: Given the condition of the previous signal at time 2, the condition of the node to be connected is calculated from the normal connection conditional expression 23 and the wiring condition obtained from the expression 14. To be done.

[Equation 40] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = n… (49)

In this case,

[Expression 41] connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p ... ( Since the relationship of 50) does not hold, the value (condition) of each node at this point is as shown in the following expression 51 from Table 5.

[0112]

[Equation 42] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = n value (N (6)) = p… (51)

Therefore, this input signal "read (B (1)),
This means that the bit condition is changed as shown in the following Expression 52 by 1 ″.

[0114]

[Equation 43]

Read (B (1)), 2: Given the condition of the previous signal at time 1, the condition of the node to be combined is calculated from the normal connection conditional expression 23 and the wiring condition obtained from the expression 14. To be done.

[Expression 44] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = p value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = n… (53)

From the condition at time 1 and the value above

[Equation 45] connect (N (6), N (4)): value (N (5)) = p… (54) Does not hold, but

Since the relationship of connect (N (1), N (3)): value (N (2)) = p ... (55) holds, the value (condition) of each node at this point is From 5, the following expression 56 is obtained.

[0117]

[Equation 47] value (N (1)) = m value (N (2)) = p value (N (3)) = m value (N (4)) = p value (N (5)) = n value (N (6)) = p… (56)

Therefore, this input signal "read (B (1)),
The bit condition is changed by the following expression 57 by 2 ″. At this time, BIT1 (m) is read.

[0119]

[Equation 48]

As a result, the conditional branch table as shown in the following Table 9 is obtained from the expressions 29 to 57.

[0121]

[Table 9]

(H. Generation of Conditional Branch Table for Abnormal Join) The conditional branch table for abnormal join can be calculated in the same manner as the conditional branch table for normal join. The only difference is that the connection relation data only includes the abnormal connection. Similar to the above example, the conditional branch is calculated for the input of candidate 1 from the initial state.

Write1 (B (3)), 1: abnormal connection conditional expression 24
Then, the condition of the node to be connected is calculated from the condition of the wiring obtained from Expression 14. The initial conditions of the nodes are all "m" as shown in Table 8.

[Equation 49] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = m, (value (L (4)) = u) value (N (5)) = value (L (2)) = n… (58)

From the initial conditions and the values above

[Expression 50] connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p ... ( 59) does not hold, and in this example circuit, BC1
And there is a short circuit in DT3,

[Expression 51] Since short (N (1), N (4)) (60), the value (condition) of each node at this point is as shown in the following Expression 61 from Table 5.

[0125]

[Equation 52] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = m value (N (5)) = n value (N (6)) = m… (61)

Therefore, from Expression 16, the bit condition is expressed by the following Expression 62 by this input signal "write1 (B (3)), 1".
It has changed like.

[0127]

[Equation 53]

Write1 (B (3)), 2: Based on the condition of this signal at time 1, the condition of the node to be combined is calculated from the abnormal connection conditional expression 24 and the wiring condition obtained from the expression 14. It

[Equation 54] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = m, (value (L (4)) = u) value (N (5)) = value (L (2)) = p… (63)

From the condition at time 1 and the value above

[Equation 55] connect (N (1), N (3)): value (N (2)) = p… (64) Does not hold, but

[Equation 56] connect (N (6), N (4)): value (N (5)) = p… (65) The relationship of

[Equation 57] Since short (N (1), N (4)) (66), the value (condition) of each node at this point is as shown in the following expression 67 from Table 5.

[0130]

[Equation 58] value (N (1)) = m value (N (2)) = n value (N (3)) = m value (N (4)) = m value (N (5)) = p value (N (6)) = m… (67)

Therefore, this input signal "write1 (B
(3)), 2 ”means that the bit condition is changed as shown in the following expression 68.

[0132]

[Equation 59]

Write1 (B (3)), 3: Based on the condition of this signal at time 2, the condition of the node to be combined is calculated from the abnormal connection conditional expression 24 and the wiring condition obtained from the expression 14. It

[Equation 60] value (N (1)) = m, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = value (L (4)) = p value (N (5)) = value (L (2)) = p… (69)

From the condition at time 2 and the value above

[Equation 61] connect (N (1), N (3)): value (N (2)) = p… (70) Does not hold, but

[Equation 62] connect (N (6), N (4)): value (N (5)) = p… (71) The relationship of

[Equation 63] Since short (N (1), N (4)) (72), the value (condition) of each node at this point is as shown in the following expression 73 from Table 5.

[0135]

[Equation 64] value (N (1)) = p value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = p value (N (6)) = p… (73)

Therefore, this input signal "write1 (B
(3)), 3 ”means that the bit condition is changed as shown in the following expression 74.

[0137]

[Equation 65]

Read (B (3)), 1: The condition of the node to be connected is calculated from the abnormal connection conditional expression 24 and the wiring condition obtained from the expression 14, assuming the condition of the previous signal at time 3. To be done.

[Equation 66] value (N (1)) = p (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = n… (75)

In this case,

[Equation 67] connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p… (76) Relationship does not hold,

[Equation 68] Since short (N (1), N (4)) (77) holds, the value (condition) of each node at this point is as shown in the following expression 78 from Table 5.

[0140]

[Equation 69] value (N (1)) = p value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = n value (N (6)) = p… (78)

Therefore, this input signal "read (B (3)),
This means that the bit condition has changed as shown in the following Expression 79 due to "1".

[0142]

[Equation 70]

Read (B (3)), 2: Given the condition of the previous signal at time 1, the condition of the node to be connected is calculated from the abnormal connection conditional expression 24 and the wiring condition obtained from the expression 14. To be done.

[Equation 71] value (N (1)) = p, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = p… (80)

From the condition at time 1 and the value above

[Equation 72] connect (N (1), N (3)): value (N (2)) = p… (81) Does not hold, but

[Equation 73] connect (N (6), N (4)): value (N (5)) = p… (82) The relationship of

[Equation 74] Since short (N (1), N (4)) (83), the value (condition) of each node at this point is as shown in the following expression 84 from Table 5.

[0145]

[Equation 75] value (N (1)) = p value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = p value (N (6)) = p… (84)

Therefore, this input signal "read (B (3)),
The bit condition is changed by 2 ″ as shown in the following expression 85. At this time, BIT3 (p) is read.

[0147]

[Equation 76]

Read (B (1)), 1: The condition of the node to be connected is calculated from the abnormal connection conditional expression 24 and the wiring condition obtained from the expression 14 based on the condition of the previous signal at time 2. To be done.

[Equation 77] value (N (1)) = p, (value (L (3)) = u) value (N (2)) = value (L (1)) = n value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = n… (86)

In this case,

[Equation 78] connect (N (1), N (3)): value (N (2)) = p connect (N (6), N (4)): value (N (5)) = p… (87) Relationship does not hold, but

[Equation 79] Since short (N (1), N (4)) (88), the value (condition) of each node at this point is as shown in the following expression 89 from Table 5.

[0150]

[Equation 80] value (N (1)) = p value (N (2)) = n value (N (3)) = m value (N (4)) = p value (N (5)) = n value (N (6)) = p… (89)

Therefore, this input signal "read (B (1)),
By "1", the bit condition is changed as shown in the following Expression 90.

[0152]

[Equation 81]

Read (B (1)), 2: Assuming the condition of the previous signal at time 1, the condition of the node to be connected is calculated from the abnormal connection conditional expression 24 and the wiring condition obtained from the expression 14. To be done.

[Equation 82] value (N (1)) = p, (value (L (3)) = u) value (N (2)) = value (L (1)) = p value (N (6)) = p, value (L (4)) = u value (N (5)) = value (L (2)) = n… (91)

From the condition at time 1 and the value above

[Equation 83] connect (N (6), N (4)): value (N (5)) = p… (92) Does not hold, but

[Equation 84] connect (N (1), N (3)): value (N (2)) = p… (93) The relationship of

[Equation 85] Since short (N (1), N (4)) (94) holds, the value (condition) of each node at this point is as shown in the following expression 95 from Table 5.

[0155]

[Equation 86] value (N (1)) = p value (N (2)) = p value (N (3)) = p value (N (4)) = p value (N (5)) = n value (N (6)) = p… (95)

Therefore, this input signal "read (B (1)),
2 ″ means that the bit condition is changed as shown in the following Expression 96. At this time, BIT1 (p) is read. At this time, from Expressions 62 to 96, the following Table 10 is obtained. A conditional branch table is obtained.

[0157]

[Equation 87]

[0158]

[Table 10]

[1-6. Abnormal Branch Search Unit] The abnormal branch search unit 17 compares the normal condition branch table and the abnormal condition branch table obtained by the conditional branch table generation unit 16 to search for an abnormal branch point. In the example circuit, comparing Tables 9 and 10, the post-branch condition of BIT1 due to the third signal input is "m" when normal, but "p" when abnormal. Therefore, it can be seen that this point is an abnormal branch point. That is, it can be seen from the following expressions 97 and 98 that the abnormal branch point in the example circuit is immediately before the input of the signal (write1 (B (3), 3)).

[0160]

[Equation 88]

As a result of comparing the normal condition branch table and the abnormal condition branch table, the post-branch conditions may differ at two or more places. In that case, a test signal sequence corresponding to each abnormal branch point is generated.

[1-7. Pre-abnormal Branch Signal Sequence Generation Unit] The pre-abnormal branch signal sequence generation unit 18 generates a signal sequence from the initial state to the abnormal branch point. That is, as described in the previous section, in the example circuit, the signal (write1 (B (3),
Immediately before the input of 3) is an abnormal branch point, for example, (write1
Since (B (3), 1), (write1 (B (3), 2), and (write1 (B (3), 3)) are one check signal write1 (B (3)), the signal (write1 (B
Before and after (3) and 3), it is not possible to make a distinction as a test signal sequence. Therefore, regarding the example circuit, assuming that the conditions change before and after the check signal write1 (B (3)),

[Equation 89] {write1 (B (3))}… (99) Is the pre-abnormal branch signal sequence.

[1-8. Post-Abnormality Branch Signal Sequence Generation Unit] The post-abnormality branch signal sequence generation unit 19 generates a series of inspection signals from the abnormal branch point to the observation. That is,
For example circuits, it is a test signal sequence

[Equation 90] Of the above, the above-mentioned pre-abnormal branch signal sequence generation unit 18 uses
Since the pre-abnormal branch signal sequence is used, the post-abnormal branch signal sequence generation unit 19 uses read (B (3)), read (B ( 1))
Is selected. As a result, the post-abnormality branch signal sequence is expressed by the following equation.

[0164]

[Formula 91] read (B (1)) read (B (3)) read (B (1)), read (B (3)) read (B (3)), read (B (1))… (101)

Now, with reference to Tables 9 and 10, how to select the signals forming the signal sequence after the abnormal branch point will be described. First, as can be seen from Table 9, the post-branch condition of write1 (B (3)) in normal connection is {m, p}.
Therefore, there are two signals having a pre-branch condition that matches the post-branch condition, read (B (3)) and read (B (1)). In other words, write1 (B (3)) followed by read (B (3)) or read (B
Regardless of which signal sequence of (1)) is combined, the conditional branching due to the normal connection is executed equally.

On the other hand, from Table 10, writ in abnormal coupling
The post-branch condition of e1 (B (3)) is {p, p}, and the signal with the pre-branch condition that matches this post-branch condition is also read (B (3)).
These are read (B (1)). In this case as well, as in the case of normal join, the conditional branch of abnormal join is executed equally regardless of whether read (B (3)) or read (B (1)) is combined after write1 (B (3)). To be done. Then, these read (B (3)) and read (B (1)) signals commonly exist in the conditional branch table for normal connection and the conditional branch table for abnormal connection. In both cases, they can be combined with write1 (B (3)), which is the abnormal pre-branch signal sequence, so these read (B (3)) and read (B
(1)) is a signal that constitutes the post-abnormal branch signal sequence.

[1-9. Abnormality Detection Signal Sequence Generation Unit] The abnormality detection signal sequence generation unit 20 includes the respective signal sequences with the abnormal branch point obtained from the above-mentioned pre-abnormality branch signal sequence generation unit 18 and post-abnormality branch signal sequence generation unit 19 as a boundary. Are combined to form an abnormality detection signal sequence that is actually used. That is, for the example circuit, the abnormality detection signal sequence from the initial state (all node conditions have intermediate values) can be combined with the signal sequences such as the following equations 102 to 105 by the equations 99 and 101. The signal sequence is output. In the expression 102, only BIT3 is read, and BIT3 is read.
Since 1 is not read, in the example circuit, B
It is not possible to judge whether IT1 is "m" or "p", and it is unknown whether the observation itself is abnormal. That is, BIT
Even though the value of 1 is different between the normal time and the abnormal time, only the BIT3 is observed in the expression 102.
Since the observation of No. 1 is not executed, it is unknown whether the observation itself is abnormal. However, as the conditional branch of the present invention, it can be known that an abnormality has occurred.

[0168]

[Equation 92] write1 (B (3)), read (B (3))… (102) write1 (B (3)), read (B (1))… (103) write1 (B (3)), read (B (3)), read (B (1))… (104) write1 (B (3)), read (B (1)), read (B (3))… (105)

Here, the reason for combining the inspection signal sequences before and after the abnormal branch point will be described. That is, a test signal sequence candidate is not always created by determining whether or not it is valid as a test signal, and therefore the test signal sequence that can be directly adopted as a test signal is not included in the test signal candidate list. In some cases. Even in such a situation, in order to generate the inspection signal, the inspection signal sequences are combined before and after the abnormal branch point.

The case where the test signal sequence candidates shown in Table 11 are given under the same failure condition as in the above-mentioned example circuit will be described below.

[0171]

[Table 11]

At this time, the branch condition table for normal connection is as shown in Table 12, and the branch condition table for abnormal connection is as shown in Table 13.

[0173]

[Table 12]

[0174]

[Table 13]

Comparing Table 12 with Table 13, candidate 1
And for candidate 3, both data match, and candidate 1
And the test signal sequence of candidate 3 {write1 (B (1)), read (B
(1))}, {write1 (B (1)), write1 (B (3)), read (B (1)), r
No fault can be found with ead (B (3))}. On the other hand, candidate 2
And for candidate 4, the abnormal branch point is detected immediately before the input of the signal (write1 (B (3), 3).
The normal condition branch and the abnormal condition branch are as follows.

[0176]

[Equation 93]

As a result, the abnormal pre-branch signal sequence is given by the following equation.

[Equation 94] {write1 (B (3))} (108) On the other hand, the post-abnormality branch signal sequence is given by

[Equation 95] read (B (1)) read (B (3)) read (B (1)), read (B (3)) read (B (3)), read (B (1))… (109)

This post-abnormality branch signal sequence has the same value as the post-branch condition {p, p} of the abnormal conditional branch as the pre-branch condition, and the signal in the conditional branch table in the abnormal connection and the post-branch condition of the normal conditional branch. A signal that is common to the signals in the conditional branch table in the normal connection that has the same value as {m, p} as the pre-branch condition, that is, extracted from the conditional branch table in the normal connection.

[Equation 96] And extracted from the conditional branching table in abnormal connection

[Numerical Expression 97] The signals read (B (1)) and read (B (3)) that are common to all are selected, and these are combined to create a post-abnormality branch signal sequence.

Then, the equation 10 obtained as described above is used.
By combining the pre-abnormality branch signal sequence shown in 8 and the post-abnormality branch signal sequence shown in Expression 109, the following abnormality detection signal sequence is finally obtained.

[0180]

[Equation 98]

Here, the signal sequences of equations 114 and 115 are included as candidates 2 and 4 in the given list, but the detection signal sequences of equations 116 and 117 are given in the given list. It is not included in the above, and because it contains read (B (1)) and read (B (3)),
It is a signal that can observe the value of each bit from the outside. As described above, according to the present embodiment, even if there is no signal sequence that can be used as a detection signal in a given test signal candidate, a plurality of test signals that generate a branch condition table for normal coupling and abnormal coupling are provided. An appropriate detection signal can be obtained by comparing the sequences.

In the present embodiment, abnormal branch points of a plurality of faults may coincide with one inspection signal. In that case, it is not possible to specify which failure is caused by the inspection signal. In such cases, another test signal must be used to identify those faults. In addition, the same abnormal branch point may be obtained when the same inspection signal is used as a different fault candidate. However, in order to discriminate different faults, it is necessary to inspect by a test signal sequence including conditional branch unique to each fault. In such a case, the test signal candidates are changed so that different faults can be discriminated. .

[2. Operation] Hereinafter, the operation of the semiconductor integrated circuit test signal generating apparatus 10 of the present embodiment will be sequentially described according to the flowcharts shown in FIGS.

[2-1. Pre-abnormal Signal Sequence Generation / Storage] FIG. 5 shows steps from reading of terminal arrangement data to generation / storage of a pre-abnormal signal sequence in the present embodiment. As shown in FIG. 5, in the present embodiment, first, the terminal arrangement data as shown in Table 2 or Table 6 is read from the terminal arrangement data storage unit 11 to the conditional branch table generation unit 16 (step S01). . Then, the test signal sequence candidates as shown in Table 4 or Table 7 are read from the test signal candidate data storage unit 15 into the conditional branch table generation unit 16 (step S02).

Next, it is judged whether or not all the read inspection signal sequence candidates have been checked (step S
03), if all are checked, the conditional branch table generation processing ends. On the other hand, if there is an unchecked test signal sequence candidate, one is extracted from the candidates (step S04), and it is determined whether or not the normal condition branch table is created for the test signal sequence candidate. (Step S05).

If the normal condition branch table has not been created yet, the process advances to step S06 to read the normal combination data as shown in Expression 23 from the normal combination data storage unit 12 of the terminal connection data storage unit 12. , The normal connection condition is calculated as described in the above section (g. Generation of a normal connection conditional branch table) (step S07), and a normal condition branch table as shown in Table 9 is generated (step S07). S08).

Subsequently, returning to step S05, it is judged whether or not the normal condition branch table is created. Since it is already created, the process proceeds to step S09, and the abnormal connection data of the terminal connection data storage unit 12 is obtained. The abnormal connection data as shown in Expression 24 is read from the storage unit 13, and the abnormal connection condition is calculated as described in the above section (h. Generation of conditional branch table of abnormal connection) (step S10). An abnormal condition branch table as shown in Table 10 is generated (step S11).

Next, the abnormal branch search unit 17 compares the normal condition branch table with the abnormal condition branch table to search for an abnormal branch point (step S12). If there is an abnormal branch point, the process proceeds to step S13, and the signal sequence from the initial state to the abnormal branch point is set by the pre-abnormality branch signal sequence generation unit 18 with the abnormal branch point searched by the abnormal branch search unit 17 as a boundary. Is generated (step S13).

On the other hand, if there is no abnormal branch point in step S12, the process returns to step S03, and the operations of steps S04 to S15 are repeated until all the read inspection signal sequence candidates have been checked.

[2-2. Post-abnormality Signal Sequence and Abnormality Detection Signal Generation / Storing] After the pre-abnormality branch signal sequence is generated as described above, the abnormal-post branch signal sequence generation unit 19 performs the abnormal branching according to the steps shown in FIG. A series of inspection signals from the abnormal branch point to the observation is generated with the abnormal branch point searched by the search unit 17 as a boundary.

First, the abnormal condition branch table created in step S11 is read (step S21), and a signal having the same value as the post-branch condition of the abnormal branch point as the pre-branch condition is searched from this abnormal condition branch table (step S21). Step S22). If there is a signal having the same value as the pre-branch condition, that signal is stored and then the normal condition branch table is read (step S24).

After the normal condition branch table is read, a signal whose pre-branch condition is the same value as the post-branch condition at the position corresponding to the abnormal branch point is searched from the normal condition branch table (step S25). . If there is a signal having the same value as the pre-branch condition (step S26), the signal in the normal condition branch table is compared with the signal found in the abnormal condition branch table found in step S23. (Step S2
7) If a common signal is found in both branch tables (step S28), a post-abnormal signal sequence is generated based on the common signal (step S29).

If there is an abnormal branch point in step 12 of FIG. 5, there is at least one signal satisfying the conditions of steps S23, S26 and S28 (which is used to find the abnormal branch point. Among the signals included in the inspection signal candidates, the signal located immediately after the abnormal branch point), if no such signal is found, the processing is terminated as an error.

After the post-abnormality signal sequence is generated in this way, the abnormality detection signal sequence generation unit 20 sets the pre-abnormality signal sequence and the post-abnormality signal sequence generated according to the steps of FIG. By combining the branches as boundaries, an abnormality detection signal sequence that is actually used is generated (step S30).

[3. Effect of Embodiment] As shown in the above embodiment, the present embodiment is described in the above-mentioned Japanese Patent Laid-Open No. 6-16213.
It has the following features as compared with the prior art described in Japanese Patent Laid-Open No.

(1) The circuit element model itself is not used. (2) The cause of failure is the abnormal coupling between terminals. (3) The terminal state of the element in the finite area is calculated by using the geometrical arrangement data of the element. (4) Instead of following the time transition of the state of the entire circuit,
Find out all conditional branches of each terminal due to coupling conditions. In this case, since the conditions are qualitatively classified, it is possible to identify the conditional branch by searching the combination. (5) The state calculation of the entire sequential circuit at each input time of the signal sequence is not performed. (6) Only the input signal sequence reaching the conditional branch of abnormal coupling is selected.

As a result, in the present embodiment, by modeling the cause of the failure in the semiconductor integrated circuit as a coupling abnormality in units of terminals, it is possible to generate a signal sequence capable of detecting the failure. That is, at the terminal level, terminals are set at locations where the state of the integrated circuit can be described, and a test signal for detecting whether the relationship between the terminals is normal or abnormal is generated. By using the terminal arrangement data as shown in Table 6, it is found that the circuit elements BIT1 and BIT3 are adjacent to each other, and a defect including interference between these terminals can be easily expressed. Further, by referring to the result of the terminal level inspection, there is an advantage that the inspection efficiency including other inspections is improved in the manufacture of the semiconductor. When performing a terminal level inspection, it is possible to identify the location not only when there is a failure in the circuit element but also when there is a failure between the circuit elements. It becomes possible to intensively perform another highly accurate inspection such as an inspection by observing a defective portion or an electric potential measurement at a specific portion, thereby improving the inspection efficiency.

Further, in the present embodiment, a plurality of inspection signal candidates are randomly generated, an appropriate inspection signal is selected from the candidates, or even if the corresponding inspection signal is not included in the candidates, a plurality of inspection signals are selected. An appropriate inspection signal can be generated by combining the signal candidates. for that reason,
In generating the inspection signal, the troublesome work of finding out the failure characteristics of the output signal with reference to the accumulated know-how and creating the inspection signal from time to time while estimating the cause of each failure is no longer necessary. It is not necessary to repeat verification whether the inspection signal is correct or not, and the operation of generating the inspection signal becomes much easier as compared with the conventional technique that relies on humans.

[0199]

According to the present invention, in a semiconductor integrated circuit, it is possible to detect a failure between logic elements by adopting a collective model for characteristic terminals of the circuit rather than for each logic element. Furthermore, by comparing the conditions of the normal operation model and the abnormal operation model with the inspection signal, the inspection signal for failure detection can be automatically calculated,
It can be applied to various failure detection and analysis during development or in the early stage of manufacturing.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a semiconductor integrated circuit test signal generating apparatus of the present invention.

FIG. 2 is a plan view schematically showing an example of arrangement of terminals in a semiconductor integrated circuit.

FIG. 3 is a sectional view schematically showing the arrangement between terminals in FIG.

FIG. 4 is a diagram showing B taken out as an example for generating an inspection signal from the inter-terminal arrangement in the semiconductor integrated circuit of FIG.
The top view which shows typically the arrangement between terminals of IT1 and BIT3.

5 is a flowchart showing an operation up to a pre-abnormal signal sequence generation step in the semiconductor integrated circuit test signal generation device of FIG.

6 is a flowchart showing the operation after the abnormal signal sequence generation step in the semiconductor integrated circuit test signal generation device of FIG.

FIG. 7 is a connection diagram showing a configuration of a semiconductor integrated circuit using circuit elements.

8 is a connection diagram showing a circuit abnormality in the semiconductor integrated circuit of FIG.

[Explanation of symbols] 10 ... Semiconductor integrated circuit inspection signal generator 11 ... Terminal arrangement data storage unit 12 ... Normal combined data storage unit 13 ... Abnormal connection data storage unit 14 ... Terminal condition calculation rule storage unit 15 ... Inspection signal candidate data storage unit 16 ... Conditional branch table generation unit 17 ... Abnormal branch search section 18 ... Pre-abnormal branch signal sequence generator 19 ... Post-abnormality branch signal sequence generation unit 20 ... Abnormality detection signal sequence generation unit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) G01R 31/3183 G06F 17/50 670

Claims (6)

(57) [Claims] 1. In addition to the terminal arrangement data of a failure-inspected semiconductor integrated circuit, the inter-terminal normal connection data describing the connection relationship between the terminals when there is no failure in the integrated circuit, and the inter-terminal normal connection data. An abnormal coupling data including data describing a coupling relationship between terminals of the integrated circuit in which the integrated circuit is suspected to operate abnormally, and the normal coupling data between terminals or the abnormal coupling data between terminals, The terminal condition calculation rule for calculating the terminal condition of each terminal of the integrated circuit and the data regarding the candidate of the inspection signal to be input to the integrated circuit are acquired, and the candidate of each of the inspection signals is acquired for each of the terminals. Regarding the normal connection data between the terminals, the branch relationship of all the terminal conditions based on the abnormal connection data is calculated according to the terminal condition calculation rule, and the normal condition branching is performed. And an abnormal condition branch table are generated, and the generated normal condition branch table and abnormal condition branch table are compared to search for conditional branch points different from each other. From the condition of the state, one that reaches the abnormal condition branch point detected by the abnormal branch search means is selected, and an input signal sequence corresponding to the selected inspection signal from its initial state to the abnormal condition branch point is selected. Is output as a pre-abnormal branch signal sequence, and one of the inspection signal candidates that reaches the abnormal condition branch point is selected, and the input signal sequence of the candidate test signal corresponding to and after the abnormal condition branch point is abnormal. Output as a post-branch signal sequence, and generate a signal sequence of any length including the signal sequence corresponding to the abnormal condition branch point from the pre-abnormal branch signal sequence and the post-abnormal branch signal sequence. Te, semiconductor integrated circuit test signal generating method characterized by the abnormality detection signal sequence. 2. A signal in a conditional branch table in an abnormal connection in which the pre-branch condition has the same value as the post-branch condition of the abnormal conditional branch in generating the post-abnormal branch signal sequence,
The same value as the post-branch condition of the normal condition branch is taken as the pre-branch condition.The signal common to the signal in the conditional branch table in the normal connection is selected as the signal that constitutes the post-abnormal branch signal sequence, and these are combined and abnormal. The method for generating a semiconductor integrated circuit test signal according to claim 1, wherein a post-branch signal sequence is created. 3. The semiconductor integrated circuit inspection signal generating method according to claim 1, wherein the abnormal branch signal sequence includes an observation signal sequence capable of determining a terminal condition. 4. A terminal arrangement data storage means for storing terminal arrangement data of a fault-tested semiconductor integrated circuit, and a normal connection data storage for storing data describing a connection relationship between terminals when there is no failure in the integrated circuit. An abnormal coupling data storage unit that stores, in addition to the normal coupling data between terminals, data that describes a coupling relationship between terminals of the integrated circuit in which the integrated circuit is suspected to operate abnormally; Based on the inter-terminal coupling data stored in the inter-terminal normal coupling data storage means or the inter-terminal abnormal coupling data storage means, the inspection signal candidate data storage means for storing the candidate of the inspection signal to be input to the circuit, Terminal condition calculation rule storage means for storing a rule for calculating the terminal condition of each terminal of the integrated circuit; and as the search signal candidate data for each terminal. For each of the stored test signal candidates, the branch relations of all terminal conditions based on the normal coupling data and abnormal coupling data between the terminals are calculated according to the terminal condition calculation rule, and the normal condition branch table and the abnormality are calculated. Conditional branch table generating means for outputting a conditional branch table, normal condition branch table obtained from the conditional branch table generating means based on the normal coupling data, and abnormal condition branch table based on the abnormal coupling data are compared. Abnormal branch search means for searching for conditional branch points different from each other, for each test signal candidate created from the data stored in the test signal candidate list data storage means, from the condition of the pre-test initial state of the integrated circuit, The one that reaches the abnormal condition branch point detected by the abnormal branch search means is selected, and the selected inspection signal is selected from its initial state. Pre-abnormality branch signal sequence generation means for outputting an input signal sequence corresponding to the abnormal condition branch point as a pre-abnormality branch signal sequence, and each of the inspection signal candidates stored in the inspection signal candidate data storage means, A post-abnormality branch signal sequence generation unit that selects a signal that reaches a conditional branch point and outputs the input signal sequence of the candidate inspection signal corresponding to the abnormal condition branch point or later as a post-abnormality branch signal sequence; Abnormality detection signal series generation means for generating a signal series of an arbitrary length including a signal series corresponding to the abnormal condition branch point from the pre-branch signal series and the abnormal post-branch signal series to be an abnormality detection signal series And a semiconductor integrated circuit inspection signal generating device comprising: 5. The signal in the conditional branch table in the abnormal connection in which the post-abnormal-branch signal sequence generation means takes the same value as the post-branch condition of the abnormal conditional branch as the pre-branch condition and the post-branch condition of the normal conditional branch. Select the same signal as the signal in the conditional branch table in normal coupling that takes the same value as the pre-branch condition as the signal that constitutes the post-abnormal branch signal sequence, and combine these to create the post-abnormal branch signal sequence. 5. The semiconductor integrated circuit inspection signal generating device according to claim 4. 6. In addition to the terminal arrangement data of the fault-tested semiconductor integrated circuit, the inter-terminal normal connection data describing the connection relationship between the terminals when there is no failure in the integrated circuit, and the inter-terminal normal connection data. An abnormal coupling data including data describing a coupling relationship between terminals of the integrated circuit in which the integrated circuit is suspected to operate abnormally, and the normal coupling data between terminals or the abnormal coupling data between terminals, The terminal condition calculation rule for calculating the terminal condition of each terminal of the integrated circuit and the data regarding the candidate of the inspection signal to be input to the integrated circuit are acquired, and the candidate of each of the inspection signals is acquired for each of the terminals. Regarding the normal connection data between the terminals, the branch relationship of all the terminal conditions based on the abnormal connection data is calculated according to the terminal condition calculation rule, and the normal condition branching is performed. And an abnormal condition branch table are generated, and the generated normal condition branch table and abnormal condition branch table are compared to search for conditional branch points different from each other. From the condition of the state, one that reaches the abnormal condition branch point detected by the abnormal branch search means is selected, and an input signal sequence corresponding to the selected inspection signal from its initial state to the abnormal condition branch point is selected. Is output as a pre-abnormal branch signal sequence, and one of the inspection signal candidates that reaches the abnormal condition branch point is selected, and the input signal sequence of the candidate test signal corresponding to and after the abnormal condition branch point is abnormal. Output as a post-branch signal sequence, and generate a signal sequence of any length including the signal sequence corresponding to the abnormal condition branch point from the pre-abnormal branch signal sequence and the post-abnormal branch signal sequence. Te, the abnormality detection signal series to be medium in which a semiconductor integrated circuit test signal generation program characterized.