JP2003107134A - Failure diagnostic device for semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make performable failure diagnosis even on a failure of a semiconductor integrated circuit device except a degenerate failure, and to calculate the probability of a diagnosis result. SOLUTION: A failure of an internal circuit having a possibility of causing a failure in an inspection using a test pattern is extracted as a preliminary suspectable failure by a preliminary suspectable failure extraction means 102, and a failure simulation is executed to the preliminary suspectable failure by a failure certification means 104, to thereby detect candidates of the internal circuit failure causing each failure in the inspection. Hereby, the failure diagnosis can be performed even on a failure of the semiconductor integrated circuit device except the degenerate failure, and the probability of the diagnosis result can be calculated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a failure diagnosis apparatus for extracting a suspected failure inside a circuit from a test result of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device manufactured by a tester is discriminated into a good product and a defective product by a tester, and a chip which is judged as a defective product is analyzed as to what causes the manufacturing process. Help improve. Such an analysis is generally called a failure analysis.

In the failure analysis, for a semiconductor integrated circuit device determined to be a defective product by a tester, a failure diagnosis is performed by extracting suspected failure points in the circuit, and the suspected failure points on the netlist are compared with the layout pattern. The physical suspicious failure position inside the circuit is specified, the signal waveform of the internal node is directly observed by the electron beam tester, and the physical failure is compared with the signal waveform of the internal node obtained by simulation in advance. Identify the position, and finally,
Each step of confirming the state of physical defects based on the image observed with the scanning electron microscope and estimating the cause of the manufacturing failure is sequentially performed.

Here, a conventional failure diagnosing device for a semiconductor integrated circuit device diagnoses a failure point by a correspondence table with a failure point in a tester corresponding to the internal circuit when the internal circuit fails and a failure simulation. .

FIG. 9 is a block diagram showing the structure of a conventional semiconductor integrated circuit device failure diagnosis apparatus. As shown in FIG. 9, a fail location storage unit 301, a correspondence table generation unit 302, a correspondence table storage unit 303, a correspondence table search unit 3
04, initial suspected failure storage means 305, failure location narrowing means 306, and final suspected failure output means 307.

The respective functions of the failure diagnosing device for the semiconductor integrated circuit device having the above-mentioned structure will be described below. Correspondence table generation means 302 generates in advance a correspondence table of all circuit locations in the semiconductor integrated circuit device in which stuck-at faults may occur, the time at which each failure in the inspection by the tester first affects, or the external pins. Then, the created correspondence table is stored in the correspondence table storage means 303.

First, in the test, the semiconductor integrated circuit device to be inspected is inspected by a tester, and the failed portion in the tester is stored in the failed portion storage means 301. next,
The individual fail locations stored in the fail location storage means 301 are compared with the contents of the correspondence table stored in the correspondence table storage means 303 by the correspondence table search means 304, and all circuits that may affect the fail locations in the tester are identified. Initial suspected failure storage means 3 extracted from the correspondence table and regarded as the initial suspected failure.
Store in 05.

The fault location narrowing means 306 narrows down the external terminals that fail in the inspection by the tester and their times among the external terminals affected by this initial suspected failure, and selects the final suspected failure from the initial suspected failures. To do.

Finally, the final suspected faults selected by the fault location narrowing means 306 are passed to the final suspected fault output means 307.
To output. However, in the conventional failure diagnosis device, since the diagnosis is performed on the assumption that the failure is a single stuck-at failure, there is a problem that the failure location cannot be identified in the case of a failure other than the stuck-at failure. Was.

As an example, a failure diagnosis apparatus for a semiconductor integrated circuit device in the case where a bridge failure exists as a failure other than the stuck-at failure will be described below. FIG. 2 is a logic circuit diagram showing a semiconductor integrated circuit device to be inspected.

In the circuit of FIG. 2, it is assumed that a bridging fault exists between the signal line j and the signal line k. A bridging fault is defined as a fault in which a plurality of adjacent signal lines always have the same logical value. Here, the signal line j is affected by the signal line k, and the signal line j is always the same as the signal line k. Consider the case of the logical value of. In this case, the signal line k operates normally,
The signal line j will behave abnormally.

FIG. 3 is a diagram showing a test pattern used for inspecting the tester. First, for the circuit of FIG.
Using the test pattern of, a failure simulation is carried out to examine the external terminal and the time when it affects each internal circuit of the semiconductor integrated circuit device. Here, since the conventional failure diagnosis device is intended to diagnose stuck-at faults, it outputs the external output terminal and time that are detected first for each stuck-at fault and stuck-at-0 fault for each internal circuit.

FIG. 4 is a diagram showing a fail portion in the tester which is first detected when a stuck-at fault of each internal circuit. In FIG. 4, in the columns of “detection failure at output 20”, “detection failure at output 21”, and “detection failure at output 22”, the left side of “/” is a signal line and the right side numbers are The failure content of the signal line is shown. "1" indicates a stuck-at-1 fault, and "0" indicates a stuck-at-0 fault.

FIG. 5 is a diagram showing a correspondence table in the semiconductor integrated circuit device of FIG. 2. From FIG. 4, a table showing a failure of each internal circuit, a time when each failure is first detected, and an external pin is shown. It is represented by.

Here, assuming that there is a bridging fault between the signal line j and the signal line k, the fail point when the circuit of FIG. 2 is inspected by the tester using the test pattern of FIG. 3 is time 5 21 and the output 21 at time 6.

However, from this fail information, FIG.
Even if the contents of the correspondence table shown in are collated, since there is no corresponding failing part, the initial suspected failure is not extracted at all,
Failure diagnosis cannot be performed for this failure.

As described above, in the conventional failure detection apparatus for the semiconductor integrated circuit device, since the stuck-at failure is assumed as a failure in creating the correspondence table, all the fail points that affect the failure of each internal circuit are described. Therefore, in the case of a failure other than the stuck-at failure such as a bridge failure, there has been a problem that the failure location of the internal circuit necessary for the failure diagnosis leaks from the suspected failure candidate. Further, even if the final suspected failure is obtained, there is a problem that the probability cannot be calculated.

[0018]

In order to solve the above problems, the failure diagnosing device for a semiconductor integrated circuit device according to the present invention is capable of diagnosing a failure of a semiconductor integrated circuit device other than the stuck-at fault and also diagnosing the failure. The purpose is to calculate the probability of the result.

[0019]

In order to achieve the above object, a failure diagnosing device for a semiconductor integrated circuit device according to a first aspect of the present invention uses the semiconductor integrated circuit device by a simulation based on an inspection result of the semiconductor integrated circuit device. Which is a failure diagnosis device for estimating a failure location of the semiconductor integrated circuit device, and a failure location storage means for storing a failure location in a tester inspection of the semiconductor integrated circuit device, and a failure of an internal circuit which may cause the failure location. Initial suspected failure extraction means for extracting as an initial suspected failure, initial suspected failure storage means for storing the initial suspected failure, and the initial suspected failure and the fail portion using the test pattern used for the inspection by the tester. The failure simulation for investigating the correlation between the initial suspected failure and the failure that may cause the failure is performed. Failure verification means for outputting the relationship with the failure location as detected failure information, and comparing the detected failure information with the failure location to calculate the probability that each initial suspected failure is the failure location causing the failure. It has a failure possibility index calculation means and a diagnostic result output means for outputting the information obtained by the failure possibility index calculation means.

According to a second aspect of the present invention, there is provided a fault diagnosing device for a semiconductor integrated circuit device according to the first aspect, wherein the initial suspected fault extracting means uses a netlist of the semiconductor integrated circuit device. It is characterized in that all the faults of the internal circuit which may cause the fail are extracted as the initial suspected faults from the fail portion by performing a route search.

A failure diagnosis apparatus for a semiconductor integrated circuit device according to a third aspect is the failure diagnosis apparatus for a semiconductor integrated circuit device according to the first aspect, wherein the initial suspected failure extraction means uses a netlist of the semiconductor integrated circuit apparatus. The failure of the internal circuit that may cause the fail is searched from the fail location by performing a route search, and further, the failure of the internal circuit that is diagnosed as the cause of the fail location by the failure simulation. Is extracted as an initial suspicious failure.

A failure diagnosing device for a semiconductor integrated circuit device according to a fourth aspect is the failure diagnosing device for a semiconductor integrated circuit device according to the first, second or third aspect, wherein the failure possibility index calculating means is For each initial suspected failure,
It is characterized in that the ratio of the number of locations output in the detected failure information to the number of locations failed by the tester is calculated.

A failure diagnosing device for a semiconductor integrated circuit device according to a fifth aspect is the failure diagnosing device for a semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the failure possibility index calculating means is: For each initial suspected failure,
The ratio of the number of locations output to the detected failure information to the number of failed locations on the tester is calculated, and it is determined whether the failure is a single stuck-at failure by comparing the failed locations on the tester with the detected failure information. It is characterized by

As described above, it is possible to perform a failure diagnosis for a failure of the semiconductor integrated circuit device other than the stuck-at failure and to calculate the probability of the diagnosis result.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION (Embodiment 1) Hereinafter, a failure diagnosing apparatus for a semiconductor integrated circuit device according to Embodiment 1 of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a failure diagnosing device for a semiconductor integrated circuit device according to a first embodiment of the present invention. Figure 1
As shown in FIG. 3, it comprises a fail location storage means 101, an initial suspected failure extraction means 102, an initial suspected failure storage means 103, a failure verification means 104, a failure possibility index calculation means 105, and a diagnosis result output means 106.

First, a target semiconductor integrated circuit device is inspected by a tester, and a fail portion in the tester is stored by the fail portion storage means 101. Next, the initial suspicious failure extraction unit 102 extracts an internal circuit that may affect the fail location detected by the tester's inspection as an initial suspicious failure and stores it in the initial suspicious failure storage unit 103.

The fault verification means 104 performs a fault simulation using the test pattern used in the inspection,
All the external terminals affected by the initial suspicious failure extracted by the initial suspicious failure extracting unit 102 and their times are output as detected failure information.

Comparing the detected failure information by the failure verification means 104 with the failed portion in the tester, the probability of failure of each internal circuit is determined by the failure possibility index calculation means 1
05, and the obtained information is used as the diagnostic result output means 1
It outputs by 06.

An example of a specific operation of the failure diagnosing device for a semiconductor integrated circuit device according to the first embodiment, which is configured as described above, will be described. Here, it is assumed that the test pattern shown in FIG. 3 is used to check the presence or absence of a single stuck-at fault in the semiconductor integrated circuit device shown in FIG. Also,
In the circuit of FIG. 2, there is a bridging fault between the signal line j and the signal line k, and the signal line j is affected by the signal line k.
Consider the case where is always the same logical value as the signal line k. In this case, the signal line k operates normally, but the signal line j operates abnormally.

At this time, the fail location of the tester when the circuit of FIG. 2 is inspected using the test pattern of FIG. 3 is output 21 at time 5 and output 21 at time 6, and the fail location storage means 101. Remember.

First, the initial suspicious failure extracting unit 102 extracts the initial suspicious failure from the fail information. here,
Since the only external output terminal in which a failure is detected is the output 21, the circuit that propagates the signal to the output 21 is searched from the netlist of the semiconductor integrated circuit device, and the signal line name that may affect the output 21 is searched. Ask for. In this case, since c, d, h, and j, the failures assumed on the searched route are c / 0, c / 1, d / 0, d / 1, h / 0,
It becomes h / 1, j / 0, j / 1 and is stored in the initial suspected failure storage means 103. These are considered as initial suspected failures, and even if the target failure is a failure other than a stuck-at failure such as a bridge failure, it is analyzed only from the netlist, so the initial suspected failure must always be the cause of the failure. There is a failure in the internal circuit.

Next, with respect to the circuit of FIG. 2, the failure verification means 104 detects all the external terminals and the times when the initial suspected failure has an influence, using the test pattern of FIG.
FIG. 6 is a diagram showing the detected failure information in the first embodiment and shows the relationship between the detected external terminal and time and the initial suspected failure.

Next, the detected failure information is compared with the failed portion in the tester, and the probability that the internal circuit stored as the initial suspected failure actually fails is calculated by the failure possibility index calculation means 105. . Here, the failure points of the tester are the output 21 at the time 5 and the output 21 at the time 6, and in the failure possibility index calculating means 105, when the ratio of each initial suspected failure affecting these failure points is examined, Since j / 0 may affect both the output 21 at time 5 and the output 21 at time 6, 100%, c / 0 is output 21 at time 6, d / 0 is output 21 at time 5, h Since / 0 may affect the output 21 at the time 6, each is 50%, and c / 1, d / 1, h / 1 and j / 1 are 0% respectively. Therefore, j / 0 has the highest probability of failure. Furthermore, j / 0 is detected in all the fail parts of the tester, but by referring to FIG.
It is also found that the fault is not a single stuck-at fault because it is detected at a place other than the failing place of the tester such as the output 21 at time 1.

Finally, this information is displayed by the diagnostic result output means 106. (Second Embodiment) The second embodiment of the present invention will be described below.

The failure diagnosing device for a semiconductor integrated circuit device according to the second embodiment has the same structure as the failure diagnosing device for a semiconductor integrated circuit device according to the first embodiment except for the initial suspicious failure extracting means. The initial suspected failure extraction means in the second embodiment first detects an internal circuit that may affect the fail part of the tester from the netlist of the semiconductor integrated circuit device. Next, a failure simulation is performed on this internal circuit, and as a result of the failure simulation, the internal circuit that affects the fail portion of the tester is stored as an initial suspected failure.

Next, an example of a specific operation of the failure diagnosing device for a semiconductor integrated circuit device according to the second embodiment will be described with reference to FIG. Here, in order to check the existence of a single stuck-at fault in the semiconductor integrated circuit device shown in FIG.
The test pattern shown in shall be used. Further, in the circuit of FIG. 2, there is a bridging fault between the signal line j and the signal line k, the signal line j is affected by the signal line k, and the signal line j always has the same logical value as that of the signal line k. Think about when. In this case, the signal line k operates normally, but the signal line j operates abnormally.

At this time, when the circuit of FIG. 2 is inspected by using the test pattern of FIG. 3, the fail portion of the tester is output 21 at time 5 and output 21 at time 6.

First, the initial suspicious failure extracting unit 102 extracts the initial suspicious failure from the fail information. here,
Since the only external output terminal in which a failure is detected is the output 21, the circuit that propagates the signal to the output 21 is searched from the netlist of the semiconductor integrated circuit device, and the signal line name that may affect the output 21 is searched. Ask for. In this case, since c, d, h, and j, the failures assumed on the searched route are c / 0, c / 1, d / 0, d / 1, h / 0,
h / 1, j / 0, j / 1. Next, using the pattern of FIG. 3, a failure simulation is performed to detect the external terminal and time at which this assumed failure has an effect, and the output at time 5 which fails at the tester 21
Then, only those that match the two locations of the output 21 at time 6 are extracted. At this time, only the external terminals and the times at which each possible failure has an effect first are extracted.

FIG. 7 is a diagram showing the external terminals and the times when each of the supposed failures has an effect first. Here, these failures (c / 0, d / 0, h / 0, j / 0)
Is extracted as an initial suspected failure. In this way, in order to extract the initial suspected failure in consideration of the tester's fail status, even if the target failure is a failure other than the stuck-at failure such as a bridge failure, the internal suspected failure always causes a failure. There is a circuit failure.

Next, using the test pattern shown in FIG. 3 for the circuit shown in FIG. 2, all the external terminals and the times affected by the initial suspected failure are detected by the failure verification means 104 as the detected failure information. .

FIG. 8 is a diagram showing the detected failure information in the second embodiment. Next, the detected failure information is compared with the failed portion in the tester, and the probability that the internal circuit stored as the initial suspected failure actually fails is calculated by the failure possibility index calculation means 105. Here, the failing part of the tester is output 21 at time 5, time 6
Is the output 21 and the failure possibility index calculation means 10
In 5, the ratio of each initial suspicious failure affecting these fail points is examined, and since j / 0 may affect both the output 21 at time 5 and the output 21 at time 6, 100%, c / 0 is output 21 at time 6, d / 0 is output 21 at time 5, h /
Since 0 may affect the output 21 at time 6, they are 50% each. Therefore, j / 0 has the highest probability of failure. Further, j / 0 is detected in all the fail parts of the tester, but by referring to FIG. 8, the j / 0 is also detected in the parts other than the fail part of the tester such as the output 21 at the time 1, so that the single degeneration is performed. It turns out that it is not a malfunction.

Finally, this information is displayed by the diagnostic result output means 106. With the above configuration, it is possible to perform a failure diagnosis for a failure of the semiconductor integrated circuit device other than the stuck-at failure, and also to calculate the probability of the diagnosis result.

Although the bridge fault has been described as an example here, not only the stuck-at fault but also other faults can be diagnosed by the same method.

[0045]

As described above, according to the failure diagnosing device for a semiconductor integrated circuit device of the present invention, a failure of an internal circuit which may cause a failure in an inspection using a test pattern is extracted as an initial suspected failure. Then, a failure simulation is performed for this initial suspected failure to detect a candidate for an internal circuit failure that causes each failure in the inspection. As a result, it is possible to perform a failure diagnosis for a failure of the semiconductor integrated circuit device other than the stuck-at failure, and it is possible to calculate the probability of the diagnosis result.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a failure diagnosing device for a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a logic circuit diagram showing a semiconductor integrated circuit device to be inspected.

FIG. 3 is a diagram showing a test pattern used to inspect a tester.

FIG. 4 is a diagram showing a fail portion in a tester that is first detected when a stuck-at fault occurs in each internal circuit.

5 is a diagram showing a correspondence table in the semiconductor integrated circuit device of FIG.

FIG. 6 is a diagram showing detected failure information according to the first embodiment.

FIG. 7 is a diagram showing the external terminals and the times when each of the assumed failures has an effect first.

FIG. 8 is a diagram showing detected failure information according to the second embodiment.

FIG. 9 is a block diagram showing the configuration of a conventional semiconductor integrated circuit device failure diagnosis apparatus.

[Explanation of symbols]

a Signal line b signal line c signal line d signal line e Signal line f signal line g Signal line h signal line i signal line j signal line k signal line 10 External input terminal 11 External input terminal 12 External input terminal 13 External input terminal 14 External input terminal 20 External output terminal 21 External output terminal 22 External output terminal 101 Fail location storage means 102 initial suspected failure extraction means 103 initial suspected failure memory means 104 Failure verification means 105 Failure possibility index calculation means 106 diagnostic result output means 301 Failing point storage means 302 correspondence table generating means 303 correspondence table storage means 304 Correspondence table search means 305 Means of initial suspected failure storage 306 Failure point narrowing means 307 Last Suspected Failure Output Means

Claims (5)

[Claims] 1. A failure diagnosing apparatus for estimating a failure location of the semiconductor integrated circuit device by simulation from a test result of the semiconductor integrated circuit apparatus, wherein a failure location in a tester inspection of the semiconductor integrated circuit device is stored. Location storage means, initial suspected failure extraction means for extracting a failure of an internal circuit that may cause the fail location as an initial suspected failure, initial suspected failure storage means for storing the initial suspected failure, and the tester The relationship between the initial suspected failure and the failing point that may cause the failure simulation is performed by examining the correlation between the initial suspected failure and the failing point using the test pattern used for the inspection in Failure detection means for outputting as detected failure information, the detected failure information and the fail location A failure possibility index calculation unit that calculates the probability that each initial suspected failure is a failure location that causes the failure by comparison, and a diagnostic result output unit that outputs the information obtained by the failure possibility index calculation unit A semiconductor integrated circuit device failure diagnosis apparatus having: 2. The initial suspected failure extraction means searches for a route using a netlist of a semiconductor integrated circuit device to detect all suspected internal circuit failures that may cause the fail from the fail location. The fault diagnosis device for a semiconductor integrated circuit device according to claim 1, wherein the fault diagnosis device is extracted as a fault. 3. The initial suspected failure extraction means searches for a failure of an internal circuit that may cause the fail from the fail location by performing a path search using a netlist of a semiconductor integrated circuit device, 2. The failure diagnosis apparatus for a semiconductor integrated circuit device according to claim 1, further comprising extracting a failure of an internal circuit diagnosed as a cause of the fail portion from the failure simulation as an initial suspected failure. 4. The failure possibility index calculating means calculates, for each initial suspicious failure, the ratio of the number of locations output in the detected failure information to the number of locations failed by the tester. A failure diagnostic device for a semiconductor integrated circuit device according to claim 1, claim 2, or claim 3. 5. The failure possibility index calculating means calculates, for each initial suspected failure, the ratio of the number of locations output to the detected failure information to the number of locations failed by the tester, and the number of failed locations in the tester. 4. The failure diagnosis device for a semiconductor integrated circuit device according to claim 1, wherein it is judged whether the fault is a single stuck-at fault by comparing the detected fault information with the detected fault information.