JP3517112B2 - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JP3517112B2 JP3517112B2 JP11758298A JP11758298A JP3517112B2 JP 3517112 B2 JP3517112 B2 JP 3517112B2 JP 11758298 A JP11758298 A JP 11758298A JP 11758298 A JP11758298 A JP 11758298A JP 3517112 B2 JP3517112 B2 JP 3517112B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- conductors
- power supply
- capacitor
- insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は、複数の絶縁層を積
層して成る絶縁基体の絶縁層間に半導体素子の電源用電
極に接続される電源用配線導体が埋設されているととも
に、この絶縁基体の表面に容量素子の電極が接続される
容量素子接続用導体が被着されており、かつ電源用配線
導体と容量素子接続用導体とが絶縁層を貫通して設けら
れた貫通導体により接続されて成る配線基板に関するも
のである。
【０００２】
【従来の技術】従来、例えば半導体集積回路素子を搭載
するための配線基板は、図２に断面図で示すように、例
えば酸化アルミニウム質焼結体等の電気絶縁材料から成
る複数の絶縁層31ａ〜31ｅを積層して成る絶縁基体31の
上面中央部に半導体集積回路素子32が搭載される搭載部
Ａが形成されているとともに、この絶縁基体31の各絶縁
層31ａ〜31ｅ間に、半導体集積回路素子32に電源を供給
するための電源用配線導体33・34や半導体集積回路素子
32に信号の出し入れをするための信号用配線導体35が配
設されている。
【０００３】そして、絶縁基体31には電源用配線導体33
・34および信号用配線導体35から絶縁基体31上面中央部
の搭載部Ａにかけて多数の貫通導体36・37・38が各絶縁
層31ａ〜31ｅを貫通して設けられており、これらの貫通
導体36・37・38により電源用配線導体33・34および信号
用配線導体35が絶縁基体31上面中央部の搭載部Ａに電気
的に導出され、この搭載部Ａに導出された貫通導体36・
37・38の上端に半導体集積回路素子32の電源用電極や信
号用電極が半田等の電気的接続手段39を介して接続され
るようになっている。
【０００４】なお、半導体集積回路素子32に電源を供給
するための電源用配線導体33・34としては、接地電位お
よびこれと異なる電位に接続される少なくとも２つの電
源用配線導体33・34があり、通常これらの電源用配線導
体33・34はそれぞれ互いに異なる絶縁層31ａ〜31ｅ間に
広面積のパターンに形成されている。
【０００５】そして、近時の高集積化および高速化した
半導体集積回路素子32を搭載する配線基板においては、
これらの接地電位およびこれと異なる電位に接続される
２つの電源用配線導体33・34間に、電源電位の変動によ
る半導体集積回路素子32の誤動作を防止するためのデカ
ップリングコンデンサと呼ばれる容量素子40が接続さ
れ、この容量素子40から電源用配線導体33・34に電荷を
供給することにより電源電位の変動を抑えるように構成
されている。
【０００６】この容量素子40としては、通常は例えばチ
ップコンデンサが好適に使用される。そして、容量素子
40の電極と各電源用配線導体33・34とを接続するには、
絶縁基体31上面の搭載部Ａ周辺に容量素子40の電極が接
続される一対の容量素子接続用導体41・42を設けるとと
もに、この一対の容量素子接続用導体41・42と各電源用
配線導体33・34とをこれらの容量素子接続用導体41・42
から電源用配線導体33・34に絶縁基体31の絶縁層31ａ・
31ｂを貫通して延びる貫通導体43・44を設けることによ
り電気的に接続しておき、各電源用配線導体33・34に電
気的に接続された一対の容量素子接続用導体41・42に容
量素子40の各電極をそれぞれ半田を介して接続する方法
が採用されている。
【０００７】なお、絶縁基体31の上面に設けられる一対
の容量素子接続用導体41・42は容量素子40の電極に対応
した大きさを有しており、その面積は一般に0.2 〜２ｍ
ｍ2程度である。また、各容量素子接続用導体41・42と
電源用配線導体33・34とを接続する貫通導体43・44はそ
の直径が100 〜200 μｍ程度であり、貫通導体43・44を
隣接して複数設ける場合には、絶縁層31ａ・31ｂにクラ
ックが発生するのを防止するために貫通導体43・44間の
隣接間隔を500 μｍ以上とする必要がある。
【０００８】
【発明が解決しようとする課題】しかしながら、この従
来の配線基板は、絶縁基体の上面に設けた各容量素子接
続用導体の面積が0.2 〜２ｍｍ2 と小さいことから、各
容量素子接続用導体と電源用配線導体とを接続するため
の貫通導体を１個の容量素子接続用導体につき１〜数個
程度しか設けることができず、そのため、容量素子接続
用導体と電源用配線導体との間のインダクタンスが大き
なものとなって容量素子から電源用配線導体に電荷を良
好かつ迅速に供給することができなくなってしまい、例
えば作動周波数が200 ＭＨｚを超えるような超高速で作
動する半導体集積回路素子を搭載した場合には、半導体
集積回路素子を正常に作動させることができないという
欠点を有していた。
【０００９】本発明は上記事情に鑑みて案出されたもの
であり、その目的は、複数の絶縁層を積層して成る絶縁
基体の絶縁層間に半導体素子の電源用電極に接続される
電源用配線導体が埋設され、この絶縁基体の表面に容量
素子の電極が接続される容量素子接続用導体が被着され
ており、かつ電源用配線導体と容量素子接続用導体とが
絶縁層を貫通して設けられた貫通導体により接続されて
成る配線基板について、容量素子接続用導体と電源用配
線導体との間のインダクタンスを小さいものとして、そ
れにより容量素子から電源用配線導体に電荷を良好かつ
迅速に供給することができ、搭載する半導体集積回路素
子を常に正常に作動させることが可能な配線基板を提供
することにある。
【００１０】
【課題を解決するための手段】本発明の配線基板は、複
数の絶縁層を積層して成る絶縁基体の前記絶縁層間に半
導体素子の電源用電極に接続される電源用配線導体を埋
設するとともに、該絶縁基体の表面に容量素子の電極が
接続される容量素子接続用導体を被着しており、前記電
源用配線導体と容量素子接続用導体とを前記絶縁層を貫
通して設けられた貫通導体により接続して成る配線基板
において、前記容量素子接続用導体と前記電源用配線導
体との間に少なくとも２層の絶縁層を配置するとともに
該少なくとも２層の絶縁層間に前記容量素子接続用導体
よりも広い面積の中継用導体を形成し、該中継用導体と
前記容量素子接続用導体とを第１の数の貫通導体で接続
するとともに、前記中継用導体と前記電源用配線導体と
を前記第１の数よりも多い第２の数の貫通導体で接続し
て成ることを特徴とするものである。
【００１１】本発明の配線基板によれば、容量素子接続
用導体と電源用配線導体との間に少なくとも２層の絶縁
層を設けるとともにこの少なくとも２層の絶縁層間に容
量素子接続用導体よりも広い面積の中継用導体を形成
し、容量素子接続用導体と中継用導体とを第１の数の貫
通導体で接続するとともに中継用導体と電源用配線導体
とを第１の数よりも多い第２の数の貫通導体で接続した
ことから、中継用導体および第２の数の貫通導体により
容量素子接続用導体と電源用配線導体との間のインダク
タンスが小さいものとなり、それにより、容量素子から
電源用配線導体に電荷を良好かつ迅速に供給することが
でき、搭載する半導体集積回路素子を常に正常に作動さ
せることが可能となる。
【００１２】
【発明の実施の形態】以下、本発明の配線基板を添付の
図面に基づき詳細に説明する。
【００１３】図１は本発明の配線基板の実施の形態の一
例を示す断面図であり、同図において１は絶縁基体であ
る。
【００１４】絶縁基体１は、例えば酸化アルミニウム質
焼結体・窒化アルミニウム質焼結体・ムライト質焼結体
・炭化珪素質焼結体・窒化珪素質焼結体・ガラスセラミ
ックス等の電気絶縁材料から成る６層の絶縁層１ａ・１
ｂ・１ｃ・１ｄ・１ｅ・１ｆを積層一体化して成り、上
面中央部には、半導体集積回路素子２が搭載される搭載
部Ａを有し、下面は図示しない外部電気回路基板に接続
される接続面を形成している。
【００１５】絶縁基体１は、例えば各絶縁層１ａ〜１ｆ
が酸化アルミニウム質焼結体から成る場合であれば、酸
化アルミニウム・酸化珪素・酸化カルシウム・酸化マグ
ネシウム等の原料粉末に適当な有機バインダおよび溶剤
を添加混合して泥漿状となすとともに、これを従来周知
のドクターブレード法を採用してシート状に形成してそ
れぞれ各絶縁層１ａ〜１ｆとなるセラミックグリーンシ
ートを準備し、しかる後、これらのセラミックグリーン
シートに適当な打ち抜き加工を施すとともに所定の順に
積層してセラミックグリーンシート積層体となし、最後
にこのセラミックグリーンシート積層体を還元雰囲気中
約1600℃の温度で焼成することによって製作される。
【００１６】また絶縁基体１の絶縁層１ｂと１ｃとの間
および１ｃと１ｄとの間には半導体集積回路素子２に電
源を供給するための電源用配線導体３・４が略全面にわ
たり被着されており、絶縁層１ｄと１ｅとの間および１
ｅと１ｆとの間には半導体集積回路素子２に信号の出し
入れをするための信号用配線導体５が所定の配線パター
ンに被着されている。
【００１７】なお、電源用配線導体３および４は、それ
ぞれ互いに異なる電位の電源を半導体集積回路素子２に
供給するための電源用配線導体であり、いずれか一方が
接地電位に接続される。
【００１８】さらに絶縁基体１の絶縁層１ａ〜１ｄ・１
ｆには電源用配線導体３・４および信号用配線導体５か
ら絶縁層１ａ〜１ｅを上下に貫通して絶縁基体１上面の
搭載部Ａに導出する電源用貫通導体６ａ・７ａおよび信
号用貫通導体８ａが形成されており、これら電源用貫通
導体６ａ・７ａおよび信号用貫通導体８ａを介して電源
用配線導体３・４および信号用配線導体５が絶縁基体１
上面中央部の搭載部Ａに電気的に導出されている。
【００１９】そして、絶縁基体１の上面中央部の搭載部
Ａに導出した電源用貫通導体６ａ・７ａ上面および信号
用貫通導体８ａ上面には、半導体集積回路素子２の電源
用電極および信号用電極が半田バンプ等の電気的接続手
段９を介して接続され、これにより半導体集積回路素子
２の電源用電極および信号用電極と電源用配線導体３・
４および信号用配線導体５とが電気的に接続されるとと
もに半導体集積回路素子２が絶縁基体１の搭載部Ａに固
定されることとなる。
【００２０】また、絶縁基体１の上面で搭載部Ａの周辺
には容量素子10の電極が接続される一対の容量素子接続
用導体11・12が被着形成されている。
【００２１】一対の容量素子接続用導体11・12は、容量
素子10の電極が接続される接続用電極として機能し、こ
れらの容量素子接続用導体11・12には容量素子10の電極
が半田13を介してそれぞれ電気的に接続される。
【００２２】さらに、絶縁基体１の絶縁層１ａと１ｂと
の間には、容量素子接続用導体11・12よりも広い面積の
中継用導体14・15が形成されている。
【００２３】この中継用導体14・15は、容量素子接続用
導体11・12と電源用配線導体３・４とを電気的に接続す
るための中継用電極として機能し、中継用導体14・15と
容量素子接続用導体11・12とが第１の数の貫通導体16・
17で電気的に接続されているとともに、中継用導体14・
15と電源用配線導体３・４とが第１の数よりも多い第２
の数の貫通導体18・19を介して電気的に接続されてい
る。
【００２４】この場合、中継用導体14・15は、容量素子
接続用導体11・12よりも広い面積を有することから、中
継用導体14・15と電源用配線導体３・４との間に多数の
貫通導体18・19を設けることができる。そしてその結
果、本発明の配線基板によれば、容量素子接続用導体11
・12と電源用配線導体３・４との間のインダクタンスが
小さなものとなり、容量素子10から電源用配線導体３・
４に電荷を良好かつ迅速に供給することができ、半導体
集積回路素子２を常に正常に作動させることが可能とな
る。
【００２５】さらに、絶縁層１ｆの下面には外部電気回
路基板に接続される外部接続用導体20が被着されてお
り、絶縁層１ｂ〜１ｆには電源用配線導体３・４および
信号用配線導体５から外部接続用導体20に導出する電源
用貫通導体６ｂ・７ｂおよび信号用貫通導体８ｂが形成
されている。
【００２６】これによって、電源用配線導体３・４およ
び信号用配線導体５が外部接続用導体20に電気的に接続
され、外部接続用導体20を図示しない外部電気回路基板
の配線導体に例えば半田を介して接続することにより、
絶縁基体１の搭載部Ａに搭載された半導体集積回路素子
２の各電極が外部電気回路に電気的に接続されることと
なる。
【００２７】なお、電源用配線導体３・４および信号用
配線導体５、容量素子接続用導体11・12、中継用導体14
・15、外部接続用導体20ならびに貫通導体６ａ・６ｂ・
７ａ・７ｂ・８ａ・８ｂ・16〜19は、タングステンやモ
リブデン・銅・銀等の金属粉末焼結体から成り、例えば
これらがタングステンやモリブデンから成る場合、電源
用配線導体３・４および信号用配線導体５、容量素子接
続用導体11・12、中継用導体14・15ならびに外部接続用
導体20であれば、絶縁基体１の絶縁層１ａ〜１ｅとなる
セラミックグリーンシートの上面および絶縁層１ｆとな
るセラミックグリーンシートの下面に、タングステン粉
末やモリブデン粉末に適当な有機バインダおよび溶剤を
添加混合して得た金属ペーストを従来周知のスクリーン
印刷法を採用して所定のパターンに印刷塗布し、これを
絶縁基体１の絶縁層１ａ〜１ｆとなるセラミックグリー
ンシートとともに焼成することによって絶縁基体１の所
定位置に所定のパターンに被着され、また貫通導体６ａ
・６ｂ・７ａ・７ｂ・８ａ・８ｂ・16〜19であれば、絶
縁層１ａ〜１ｆとなるセラミックグリーンシートの各々
に貫通孔を打ち抜いておくとともに、この貫通孔内にタ
ングステン粉末やモリブデン粉末に適当な有機バインダ
および溶剤を添加混合して得た金属ペーストを従来周知
の圧入法や吸引法等により充填しておき、これを絶縁基
体１の絶縁層１ａ〜１ｆとなるセラミックグリーンシー
トとともに焼成することによって絶縁基体１の所定位置
に形成される。
【００２８】なお、本発明は上記の実施の形態の例に限
定されるものではなく、本発明の要旨を逸脱しない範囲
で種々の変更・改良を施すことは何ら差し支えない。
【００２９】例えば、上記の例では絶縁基体が各種のセ
ラミックスやガラスセラミックス等の電気絶縁材料から
成る場合を例にとって説明したが、絶縁基体には有機絶
縁性材料や有機絶縁性材料と無機絶縁物粉末との混合物
を用いてもよく、各配線導体や各貫通導体をそれに合っ
た導体材料に変更してもよい。
【００３０】
【発明の効果】本発明の配線基板によれば、容量素子接
続用導体と電源用配線導体との間に少なくとも２層の絶
縁層を設けるとともに、この少なくとも２層の絶縁層間
に容量素子接続用導体よりも広い面積の中継用導体を形
成し、容量素子接続用導体と中継用導体とを第１の数の
貫通導体で接続するとともに、中継用導体と電源用配線
導体とを第１の数よりも多い第２の数の貫通導体で接続
したことから、容量素子接続用導体と電源用配線導体と
の間のインダクタンスが小さいものとなり、その結果、
容量素子から電源用配線導体に電荷を良好かつ迅速に供
給することができ、搭載する半導体集積回路素子を常に
正常に作動させることが可能となる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply wiring conductor connected to a power supply electrode of a semiconductor element between insulating layers of an insulating base formed by laminating a plurality of insulating layers. Is embedded, and a capacitor connecting conductor to which an electrode of the capacitor is connected is attached to the surface of the insulating base, and the power supply wiring conductor and the capacitor connecting conductor penetrate the insulating layer. The present invention relates to a wiring board connected by through conductors provided as described above. 2. Description of the Related Art Conventionally, as shown in a sectional view of FIG. 2, for example, a wiring board for mounting a semiconductor integrated circuit element is formed of a plurality of electrically insulating materials such as an aluminum oxide sintered body. A mounting portion A on which the semiconductor integrated circuit element 32 is mounted is formed at the center of the upper surface of the insulating base 31 formed by laminating the insulating layers 31a to 31e, and between the insulating layers 31a to 31e of the insulating base 31. , Power supply wiring conductors 33 and 34 for supplying power to the semiconductor integrated circuit element 32 and the semiconductor integrated circuit element
A signal wiring conductor 35 for putting signals in and out is provided at 32. A power supply wiring conductor 33 is provided on the insulating base 31.
A large number of through conductors 36, 37, and 38 are provided through the insulating layers 31 a to 31 e from the signal wiring conductor 35 and the signal wiring conductor 35 to the mounting portion A at the center of the upper surface of the insulating base 31. The power supply wiring conductors 33 and 34 and the signal wiring conductor 35 are electrically led out to the mounting portion A at the center of the upper surface of the insulating base 31 by the 37 and 38, and the through conductors 36 led out to the mounting portion A.
Power supply electrodes and signal electrodes of the semiconductor integrated circuit element 32 are connected to the upper ends of 37 and 38 via electrical connection means 39 such as solder. The power supply wiring conductors 33 and 34 for supplying power to the semiconductor integrated circuit element 32 include at least two power supply wiring conductors 33 and 34 connected to a ground potential and a different potential. Normally, these power supply wiring conductors 33 and 34 are formed in a wide area pattern between different insulating layers 31a to 31e. In recent years, in a wiring board on which a semiconductor integrated circuit element 32 of high integration and high speed is mounted,
A capacitance element 40 called a decoupling capacitor for preventing a malfunction of the semiconductor integrated circuit element 32 due to a fluctuation of the power supply potential is provided between the two power supply wiring conductors 33 and 34 connected to these ground potentials and different potentials. Is connected to the power supply wiring conductors 33 and 34 so as to suppress the fluctuation of the power supply potential. For example, a chip capacitor is preferably used as the capacitance element 40. And the capacitive element
To connect the 40 electrodes and the power supply wiring conductors 33 and 34,
A pair of capacitance element connection conductors 41 and 42 to which the electrodes of the capacitance element 40 are connected are provided around the mounting portion A on the upper surface of the insulating base 31, and the pair of capacitance element connection conductors 41 and 42 and each power supply wiring conductor 33 and 34 are connected to these conductors 41 and 42
From the power supply wiring conductors 33 and 34 to the insulating layer 31a of the insulating base 31.
By providing through conductors 43 and 44 extending through the base 31b, they are electrically connected to each other, and a pair of capacitive element connecting conductors 41 and 42 electrically connected to the power supply wiring conductors 33 and 34 are provided with capacitance. A method of connecting each electrode of the element 40 via solder is adopted. The pair of capacitive element connecting conductors 41 and 42 provided on the upper surface of the insulating base 31 has a size corresponding to the electrodes of the capacitive element 40, and the area thereof is generally 0.2 to 2 m.
m 2 . The diameter of the through conductors 43 and 44 for connecting the capacitance element connecting conductors 41 and 42 and the power supply wiring conductors 33 and 34 is about 100 to 200 μm. In the case of providing, the adjacent space between the through conductors 43 and 44 needs to be 500 μm or more in order to prevent the occurrence of cracks in the insulating layers 31a and 31b. However, in this conventional wiring board, since the area of each capacitor element connecting conductor provided on the upper surface of the insulating base is as small as 0.2 to 2 mm 2 , each of the capacitor element connecting conductors is small. Only about one to several through conductors for connecting the power conductor and the power supply wiring conductor can be provided for one capacitance element connection conductor, so that the capacitance element connection conductor and the power supply wiring conductor Between the capacitor and the capacitor cannot supply good and quick electric charge from the capacitor to the power supply wiring conductor. For example, semiconductor integrated circuits that operate at ultra-high speeds such as operating frequencies exceeding 200 MHz When a circuit element is mounted, there is a disadvantage that the semiconductor integrated circuit element cannot be operated normally. The present invention has been made in view of the above circumstances, and has as its object to provide a power supply for a power supply connected to a power supply electrode of a semiconductor element between insulating layers of an insulating base formed by laminating a plurality of insulating layers. A wiring conductor is buried, a capacitor element connecting conductor to which an electrode of the capacitor is connected is attached to the surface of the insulating base, and the power source wiring conductor and the capacitor element connecting conductor penetrate the insulating layer. The wiring board formed by the through conductors provided in this manner has a small inductance between the capacitor element connecting conductor and the power supply wiring conductor so that electric charges can be transferred from the capacitor element to the power supply wiring conductor in a good and quick manner. It is an object of the present invention to provide a wiring board which can supply the semiconductor integrated circuit element to be normally operated normally. [0010] A wiring board according to the present invention comprises a power supply wiring conductor connected to a power supply electrode of a semiconductor element between the insulating layers of an insulating base formed by laminating a plurality of insulating layers. A capacitor connecting conductor to which an electrode of a capacitor is connected is attached to the surface of the insulating base while being buried, and the power supply wiring conductor and the capacitor connecting conductor are passed through the insulating layer. In a wiring board connected by the provided through conductors, at least two insulating layers are disposed between the capacitor element connecting conductor and the power supply wiring conductor, and the capacitor is provided between the at least two insulating layers. A relay conductor having an area larger than the element connection conductor is formed, the relay conductor and the capacitor element connection conductor are connected by a first number of through conductors, and the relay conductor and the power supply wiring are connected. In front of the conductor It is characterized by being connected by a second number of through conductors greater than the first number. According to the wiring board of the present invention, at least two insulating layers are provided between the conductor for connecting the capacitor and the wiring conductor for power supply, and the at least two insulating layers are provided between the conductor for connecting the capacitor and the conductor for connecting the capacitor. A relay conductor having a large area is formed, the capacitor connection conductor and the relay conductor are connected by a first number of through conductors, and the relay conductor and the power supply wiring conductor are larger than the first number. Since the connection is made with two through conductors, the inductance between the capacitor element connection conductor and the power supply wiring conductor is reduced by the relay conductor and the second number of through conductors. The electric charge can be supplied to the power supply wiring conductor satisfactorily and promptly, and the semiconductor integrated circuit element to be mounted can always operate normally. Hereinafter, a wiring board according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing an embodiment of a wiring board according to the present invention. In FIG. 1, reference numeral 1 denotes an insulating base. The insulating substrate 1 is made of an electrical insulating material such as a sintered body of aluminum oxide, a sintered body of aluminum nitride, a sintered body of mullite, a sintered body of silicon carbide, a sintered body of silicon nitride, and glass ceramic. Insulating layers 1a and 1 made of
b, 1c, 1d, 1e, 1f are laminated and integrated, and a mounting portion A on which the semiconductor integrated circuit element 2 is mounted is provided at the center of the upper surface, and the lower surface is connected to an external electric circuit board (not shown). The connection surface is formed. The insulating base 1 is made of, for example, each of the insulating layers 1a to 1f.
Is made of an aluminum oxide sintered body, a suitable organic binder and a solvent are added to the raw material powder such as aluminum oxide, silicon oxide, calcium oxide, magnesium oxide, etc., and the mixture is formed into a slurry. A ceramic green sheet which is formed into a sheet shape by employing a well-known doctor blade method and which becomes each of the insulating layers 1a to 1f is prepared, and thereafter, these ceramic green sheets are subjected to a suitable punching process and in a predetermined order. The ceramic green sheet laminate is formed by laminating, and finally, the ceramic green sheet laminate is fired at a temperature of about 1600 ° C. in a reducing atmosphere. Power supply wiring conductors 3 and 4 for supplying power to the semiconductor integrated circuit element 2 are provided over substantially the entire surface between the insulating layers 1b and 1c and between 1c and 1d of the insulating base 1. Between the insulating layers 1d and 1e and 1
Between e and 1f, a signal wiring conductor 5 for putting signals into and out of the semiconductor integrated circuit element 2 is attached to a predetermined wiring pattern. The power supply wiring conductors 3 and 4 are power supply wiring conductors for supplying power of different potentials to the semiconductor integrated circuit element 2, and one of them is connected to the ground potential. Further, the insulating layers 1a to 1d-1 of the insulating base 1
In f, the power supply through conductors 6a and 7a and the signal through hole which penetrate vertically through the insulating layers 1a to 1e from the power supply wiring conductors 3 and 4 and the signal wiring conductor 5 and lead to the mounting portion A on the upper surface of the insulating base 1. A conductor 8a is formed, and the power supply wiring conductors 3 and 4 and the signal wiring conductor 5 are connected to the insulating base 1 via the power supply through conductors 6a and 7a and the signal through conductor 8a.
It is electrically led to the mounting portion A at the center of the upper surface. The power supply electrodes and the signal electrodes of the semiconductor integrated circuit element 2 are provided on the upper surfaces of the power supply through-conductors 6a and 7a and the signal through-conductor 8a which are led out to the mounting portion A at the center of the upper surface of the insulating base 1. Are connected via electrical connection means 9 such as solder bumps, whereby the power supply electrode and signal electrode of the semiconductor integrated circuit element 2 and the power supply wiring conductor 3.
4 and the signal wiring conductor 5 are electrically connected, and the semiconductor integrated circuit element 2 is fixed to the mounting portion A of the insulating base 1. A pair of capacitor element connecting conductors 11 and 12 to which electrodes of the capacitor element 10 are connected are formed on the upper surface of the insulating base 1 and around the mounting portion A. The pair of capacitive element connecting conductors 11 and 12 function as connecting electrodes to which the electrodes of the capacitive element 10 are connected, and the electrodes of the capacitive element 10 are soldered to these capacitive element connecting conductors 11 and 12. Each is electrically connected via 13. Further, between the insulating layers 1a and 1b of the insulating base 1, relay conductors 14 and 15 having an area larger than the conductors 11 and 12 for connecting the capacitance elements are formed. The relay conductors 14 and 15 function as relay electrodes for electrically connecting the capacitive element connection conductors 11 and 12 and the power supply wiring conductors 3 and 4, and the relay conductors 14 and 15 And the first and second through conductors 16 and
17 are electrically connected, and the relay conductors 14
15 and the power supply wiring conductors 3 and 4 are larger than the first number.
Are electrically connected through the number of through conductors 18 and 19. In this case, since the relay conductors 14 and 15 have a larger area than the capacitive element connection conductors 11 and 12, a large number of conductors are provided between the relay conductors 14 and 15 and the power supply wiring conductors 3 and 4. Of the through conductors 18 and 19 can be provided. As a result, according to the wiring board of the present invention, the conductor 11
The inductance between the power supply wiring conductors 3 and 4 becomes small, and the power supply wiring conductors 3
4 can be satisfactorily and quickly supplied to the semiconductor integrated circuit device 4, and the semiconductor integrated circuit device 2 can always be normally operated. Further, an external connection conductor 20 connected to an external electric circuit board is attached to the lower surface of the insulating layer 1f, and the power supply wiring conductors 3 and 4 and the signal wiring are provided on the insulating layers 1b to 1f. The power supply through conductors 6b and 7b and the signal through conductor 8b are formed to extend from the conductor 5 to the external connection conductor 20. As a result, the power supply wiring conductors 3 and 4 and the signal wiring conductor 5 are electrically connected to the external connection conductor 20, and the external connection conductor 20 is soldered to the wiring conductor of the external electric circuit board (not shown). By connecting via
Each electrode of the semiconductor integrated circuit element 2 mounted on the mounting portion A of the insulating base 1 is electrically connected to an external electric circuit. The power supply wiring conductors 3 and 4, the signal wiring conductor 5, the capacitor element connection conductors 11 and 12, and the relay conductor 14
· 15, conductor 20 for external connection and through conductors 6a · 6b ·
7a, 7b, 8a, 8b, and 16 to 19 are made of a sintered metal powder such as tungsten, molybdenum, copper, or silver. For example, when these are made of tungsten or molybdenum, the power supply wiring conductors 3, 4 and the signal If the wiring conductor 5, the capacitor element connecting conductors 11 and 12, the relay conductors 14 and 15, and the external connecting conductor 20, the upper surface of the ceramic green sheet to be the insulating layers 1a to 1e of the insulating base 1 and the insulating layer 1f On the lower surface of the ceramic green sheet, a metal paste obtained by adding and mixing an appropriate organic binder and a solvent to a tungsten powder or a molybdenum powder is printed and applied in a predetermined pattern by using a conventionally known screen printing method. By firing together with the ceramic green sheets to be the insulating layers 1a to 1f of the insulating substrate 1, a predetermined pattern is formed at a predetermined position on the insulating substrate 1. It is deposited, also through the conductor 6a
In the case of 6b, 7a, 7b, 8a, 8b, 16 to 19, through holes are punched in each of the ceramic green sheets to be the insulating layers 1a to 1f, and tungsten powder or molybdenum powder is formed in the through holes. A metal paste obtained by adding and mixing an appropriate organic binder and a solvent is filled by a well-known press-fitting method, a suction method, or the like, and is fired together with ceramic green sheets to be the insulating layers 1a to 1f of the insulating base 1. Thus, the insulating substrate 1 is formed at a predetermined position. It should be noted that the present invention is not limited to the above-described embodiment, and that various changes and improvements can be made without departing from the spirit of the present invention. For example, in the above example, the case where the insulating base is made of an electrically insulating material such as various ceramics and glass ceramics has been described as an example. However, the insulating base is made of an organic insulating material or an organic insulating material and an inorganic insulating material. A mixture with a powder may be used, and each wiring conductor or each through conductor may be changed to a conductor material suitable for it. According to the wiring board of the present invention, at least two insulating layers are provided between the capacitor element connecting conductor and the power supply wiring conductor, and the capacitance is provided between the at least two insulating layers. A relay conductor having a larger area than the element connection conductor is formed, the capacitor element connection conductor and the relay conductor are connected by the first number of through conductors, and the relay conductor and the power supply wiring conductor are connected to each other by the first number. Since the connection is made with the second number of through conductors larger than the number of 1, the inductance between the capacitor element connection conductor and the power supply wiring conductor becomes small, and as a result,
Electric charges can be satisfactorily and quickly supplied from the capacitance element to the power supply wiring conductor, and the semiconductor integrated circuit element to be mounted can always operate normally.
【図面の簡単な説明】
【図１】本発明の配線基板の実施の形態の一例を示す断
面図である。
【図２】従来の配線基板の例を示す断面図である。
【符号の説明】
１・・・・絶縁基体
１ａ〜１ｆ・・絶縁層
２・・・・半導体集積回路素子（半導体素子）
３、４・・電源用配線導体
10・・・・容量素子
11、12・・容量素子接続用導体
14、15・・中継用導体
16、17・・第１の数の貫通導体
18、19・・第２の数の貫通導体BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing an example of an embodiment of a wiring board of the present invention. FIG. 2 is a cross-sectional view illustrating an example of a conventional wiring board. [Description of Signs] 1... Insulating bases 1a to 1f... Insulating layer 2... Semiconductor integrated circuit element (semiconductor element) 3, 4. 12 ··· Capacitor connection conductors 14, 15 ··· Relay conductors 16, 17 ··· First number of through conductors 18, 19 ··· Second number of through conductors
Claims (1)
前記絶縁層間に半導体素子の電源用電極に接続される電
源用配線導体を埋設するとともに、該絶縁基体の表面に
容量素子の電極が接続される容量素子接続用導体を被着
しており、前記電源用配線導体と容量素子接続用導体と
を前記絶縁層を貫通して設けられた貫通導体により接続
して成る配線基板において、 前記容量素子接続用導体と前記電源用配線導体との間に
少なくとも２層の絶縁層を配置するとともに該少なくと
も２層の絶縁層間に前記容量素子接続用導体よりも広い
面積の中継用導体を形成し、該中継用導体と前記容量素
子接続用導体とを第１の数の貫通導体で接続するととも
に、前記中継用導体と前記電源用配線導体とを前記第１
の数よりも多い第２の数の貫通導体で接続して成ること
を特徴とする配線基板。(57) Claims 1. A power supply wiring conductor connected to a power supply electrode of a semiconductor element is buried between the insulating layers of an insulating substrate formed by laminating a plurality of insulating layers. A conductor for connecting a capacitor connected to an electrode of the capacitor on a surface of an insulating base, and a through conductor provided with the power supply wiring conductor and the capacitor connecting conductor penetrating the insulating layer And at least two insulating layers are disposed between the capacitive element connecting conductor and the power source wiring conductor, and the capacitive element connecting conductor is disposed between the at least two insulating layers. Forming a relay conductor having a large area, connecting the relay conductor and the capacitor element connection conductor with a first number of through conductors, and connecting the relay conductor and the power supply wiring conductor to each other. 1
A wiring board connected by a second number of through conductors greater than the number of through conductors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11758298A JP3517112B2 (en) | 1998-04-27 | 1998-04-27 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11758298A JP3517112B2 (en) | 1998-04-27 | 1998-04-27 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11312752A JPH11312752A (en) | 1999-11-09 |
| JP3517112B2 true JP3517112B2 (en) | 2004-04-05 |
Family
ID=14715397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11758298A Expired - Fee Related JP3517112B2 (en) | 1998-04-27 | 1998-04-27 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3517112B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002185141A (en) * | 2000-12-15 | 2002-06-28 | Ibiden Co Ltd | Multilayer printed board |
| JP2007508688A (en) * | 2003-10-10 | 2007-04-05 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Electronic device and carrier substrate therefor |
-
1998
- 1998-04-27 JP JP11758298A patent/JP3517112B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11312752A (en) | 1999-11-09 |
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